Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>master
TsiChungLiew
18 years ago
committed by
John Rigby
parent
a605aacd83
commit
a1436a8426
@ -0,0 +1,44 @@ |
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(BOARD).a
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COBJS = $(BOARD).o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) |
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$(AR) $(ARFLAGS) $@ $(OBJS)
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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@ -0,0 +1,25 @@ |
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#
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# (C) Copyright 2000-2003
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
|
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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TEXT_BASE = 0xffe00000
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@ -0,0 +1,133 @@ |
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/*
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* (C) Copyright 2000-2003 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* Copyright (C) 2004-2007 Freescale Semiconductor, Inc. |
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* Hayden Fraser (Hayden.Fraser@freescale.com) |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <asm/immap.h> |
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int checkboard(void) |
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{ |
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puts("Board: "); |
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puts("Freescale MCF5253 EVBE\n"); |
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return 0; |
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}; |
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long int initdram(int board_type) |
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{ |
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int i; |
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/*
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* Check to see if the SDRAM has already been initialized |
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* by a run control tool |
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*/ |
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if (!(mbar_readLong(MCFSIM_DCR) & 0x8000)) { |
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u32 RC, dramsize; |
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RC = (CFG_CLK / 1000000) >> 1; |
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RC = (RC * 15) >> 4; |
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/* Initialize DRAM Control Register: DCR */ |
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mbar_writeShort(MCFSIM_DCR, (0x8400 | RC)); |
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mbar_writeLong(MCFSIM_DACR0, 0x00003224); |
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/* Initialize DMR0 */ |
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dramsize = ((CFG_SDRAM_SIZE << 20) - 1) & 0xFFFC0000; |
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mbar_writeLong(MCFSIM_DMR0, dramsize | 1); |
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mbar_writeLong(MCFSIM_DACR0, 0x0000322c); |
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/* Write to this block to initiate precharge */ |
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*(u32 *) (CFG_SDRAM_BASE) = 0xa5a5a5a5; |
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/* Set RE bit in DACR */ |
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mbar_writeLong(MCFSIM_DACR0, |
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mbar_readLong(MCFSIM_DACR0) | 0x8000); |
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/* Wait for at least 8 auto refresh cycles to occur */ |
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udelay(500); |
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/* Finish the configuration by issuing the MRS */ |
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mbar_writeLong(MCFSIM_DACR0, |
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mbar_readLong(MCFSIM_DACR0) | 0x0040); |
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*(u32 *) (CFG_SDRAM_BASE + 0x800) = 0xa5a5a5a5; |
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} |
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return CFG_SDRAM_SIZE * 1024 * 1024; |
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} |
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int testdram(void) |
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{ |
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/* TODO: XXX XXX XXX */ |
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printf("DRAM test not implemented!\n"); |
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return (0); |
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} |
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#ifdef CONFIG_CMD_IDE |
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#include <ata.h> |
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int ide_preinit(void) |
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{ |
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return (0); |
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} |
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void ide_set_reset(int idereset) |
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{ |
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volatile atac_t *ata = (atac_t *) CFG_ATA_BASE_ADDR; |
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long period; |
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/* t1, t2, t3, t4, t5, t6, t9, tRD, tA */ |
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int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */ |
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{50, 125, 45, 20, 35, 5, 15, 0, 35}, /* PIO 1 */ |
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{30, 100, 30, 15, 20, 5, 10, 0, 35}, /* PIO 2 */ |
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{30, 80, 30, 10, 20, 5, 10, 0, 35}, /* PIO 3 */ |
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{25, 70, 20, 10, 20, 5, 10, 0, 35} /* PIO 4 */ |
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}; |
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if (idereset) { |
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ata->cr = 0; /* control reset */ |
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udelay(100); |
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} else { |
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mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND); |
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#define CALC_TIMING(t) (t + period - 1) / period |
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period = 1000000000 / (CFG_CLK / 2); /* period in ns */ |
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/*ata->ton = CALC_TIMING (180); */ |
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ata->t1 = CALC_TIMING(piotms[2][0]); |
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ata->t2w = CALC_TIMING(piotms[2][1]); |
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ata->t2r = CALC_TIMING(piotms[2][1]); |
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ata->ta = CALC_TIMING(piotms[2][8]); |
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ata->trd = CALC_TIMING(piotms[2][7]); |
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ata->t4 = CALC_TIMING(piotms[2][3]); |
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ata->t9 = CALC_TIMING(piotms[2][6]); |
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ata->cr = 0x40; /* IORDY enable */ |
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udelay(2000); |
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ata->cr |= 0x01; /* IORDY enable */ |
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} |
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} |
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#endif /* CONFIG_CMD_IDE */ |
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@ -0,0 +1,144 @@ |
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/* |
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* (C) Copyright 2000 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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OUTPUT_ARCH(m68k) |
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SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); |
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/* Do we need any of these for elf? |
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__DYNAMIC = 0; */ |
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SECTIONS |
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{ |
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/* Read-only sections, merged into text segment: */ |
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. = + SIZEOF_HEADERS; |
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.interp : { *(.interp) } |
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.hash : { *(.hash) } |
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.dynsym : { *(.dynsym) } |
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.dynstr : { *(.dynstr) } |
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.rel.text : { *(.rel.text) } |
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.rela.text : { *(.rela.text) } |
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.rel.data : { *(.rel.data) } |
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.rela.data : { *(.rela.data) } |
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.rel.rodata : { *(.rel.rodata) } |
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.rela.rodata : { *(.rela.rodata) } |
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.rel.got : { *(.rel.got) } |
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.rela.got : { *(.rela.got) } |
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.rel.ctors : { *(.rel.ctors) } |
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.rela.ctors : { *(.rela.ctors) } |
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.rel.dtors : { *(.rel.dtors) } |
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.rela.dtors : { *(.rela.dtors) } |
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.rel.bss : { *(.rel.bss) } |
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.rela.bss : { *(.rela.bss) } |
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.rel.plt : { *(.rel.plt) } |
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.rela.plt : { *(.rela.plt) } |
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.init : { *(.init) } |
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.plt : { *(.plt) } |
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.text : |
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{ |
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/* WARNING - the following is hand-optimized to fit within */ |
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/* the sector layout of our flash chips! XXX FIXME XXX */ |
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cpu/mcf52x2/start.o (.text) |
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lib_m68k/traps.o (.text) |
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cpu/mcf52x2/interrupts.o (.text) |
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common/dlmalloc.o (.text) |
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lib_generic/zlib.o (.text) |
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. = DEFINED(env_offset) ? env_offset : .; |
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common/environment.o (.text) |
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*(.text) |
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*(.fixup) |
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*(.got1) |
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} |
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_etext = .; |
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PROVIDE (etext = .); |
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.rodata : |
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{ |
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*(.rodata) |
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*(.rodata1) |
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} |
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.fini : { *(.fini) } =0 |
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.ctors : { *(.ctors) } |
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.dtors : { *(.dtors) } |
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/* Read-write section, merged into data segment: */ |
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. = (. + 0x00FF) & 0xFFFFFF00; |
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_erotext = .; |
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PROVIDE (erotext = .); |
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.reloc : |
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{ |
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__got_start = .; |
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*(.got) |
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__got_end = .; |
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_GOT2_TABLE_ = .; |
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*(.got2) |
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_FIXUP_TABLE_ = .; |
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*(.fixup) |
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} |
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__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; |
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__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
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.data : |
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{ |
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*(.data) |
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*(.data1) |
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*(.sdata) |
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*(.sdata2) |
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*(.dynamic) |
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CONSTRUCTORS |
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} |
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_edata = .; |
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PROVIDE (edata = .); |
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. = .; |
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__u_boot_cmd_start = .; |
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.u_boot_cmd : { *(.u_boot_cmd) } |
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__u_boot_cmd_end = .; |
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. = .; |
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__start___ex_table = .; |
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__ex_table : { *(__ex_table) } |
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__stop___ex_table = .; |
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. = ALIGN(256); |
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__init_begin = .; |
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.text.init : { *(.text.init) } |
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.data.init : { *(.data.init) } |
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. = ALIGN(256); |
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__init_end = .; |
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__bss_start = .; |
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.bss : |
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{ |
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_sbss = .; |
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*(.sbss) *(.scommon) |
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*(.dynbss) |
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*(.bss) |
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*(COMMON) |
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. = ALIGN(4); |
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_ebss = .; |
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} |
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_end = . ; |
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PROVIDE (end = .); |
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} |
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@ -0,0 +1,103 @@ |
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Freescale Amadeus Plus M5253EVBE board |
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====================================== |
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Hayden Fraser(Hayden.Fraser@freescale.com) |
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Created 06/05/2007 |
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=========================================== |
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1. SWITCH SETTINGS |
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================== |
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1.1 N/A |
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2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL |
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=========================================== |
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2.1. For the initial bringup, we adopted a consistent memory scheme between u-boot and |
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linux kernel, you can customize it based on your system requirements: |
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SDR: 0x00000000-0x00ffffff |
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SRAM0: 0x20010000-0x20017fff |
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SRAM1: 0x20000000-0x2000ffff |
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MBAR1: 0x10000000-0x4fffffff |
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MBAR2: 0x80000000-0xCfffffff |
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Flash: 0xffe00000-0xffffffff |
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3. DEFINITIONS AND COMPILATION |
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============================== |
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3.1 Explanation on NEW definitions in include/configs/M5253EVBE.h |
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CONFIG_MCF52x2 Processor family |
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CONFIG_MCF5253 MCF5253 specific |
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CONFIG_M5253EVBE Amadeus Plus board specific |
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CFG_CLK Define Amadeus Plus CPU Clock |
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CFG_MBAR MBAR base address |
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CFG_MBAR2 MBAR2 base address |
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3.2 Compilation |
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export CROSS_COMPILE=/usr/local/freescale-coldfire-4.1-elf/bin/m68k-elf- |
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cd u-boot-1-2-x |
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make distclean |
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make M5253EVBE_config |
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make |
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4. SCREEN DUMP |
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============== |
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4.1 U-Boot 1.2.0 (Jun 18 2007 - 18:20:00) |
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CPU: Freescale Coldfire MCF5253 at 62 MHz |
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Board: Freescale MCF5253 EVBE |
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DRAM: 16 MB |
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FLASH: 2 MB |
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In: serial |
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Out: serial |
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Err: serial |
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=> flinfo |
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Bank # 1: CFI conformant FLASH (16 x 16) Size: 2 MB in 35 Sectors |
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AMD Standard command set, Manufacturer ID: 0x01, Device ID: 0x49 |
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Erase timeout: 16384 ms, write timeout: 1 ms |
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|
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Sector Start Addresses: |
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FFE00000 RO FFE04000 RO FFE06000 RO FFE08000 RO FFE10000 RO |
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FFE20000 FFE30000 FFE40000 FFE50000 FFE60000 |
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FFE70000 FFE80000 FFE90000 FFEA0000 FFEB0000 |
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FFEC0000 FFED0000 FFEE0000 FFEF0000 FFF00000 |
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FFF10000 FFF20000 FFF30000 FFF40000 FFF50000 |
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FFF60000 FFF70000 FFF80000 FFF90000 FFFA0000 |
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FFFB0000 FFFC0000 FFFD0000 FFFE0000 FFFF0000 |
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|
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=> bdinfo |
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boot_params = 0x00F62F90 |
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memstart = 0x00000000 |
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memsize = 0x01000000 |
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flashstart = 0xFFE00000 |
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flashsize = 0x00200000 |
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flashoffset = 0x00000000 |
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baudrate = 19200 bps |
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|
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=> printenv |
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bootdelay=5 |
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baudrate=19200 |
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stdin=serial |
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stdout=serial |
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stderr=serial |
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|
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Environment size: 134/8188 bytes |
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=> saveenv |
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Saving Environment to Flash... |
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Un-Protected 1 sectors |
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Erasing Flash... |
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. done |
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Erased 1 sectors |
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Writing to Flash... done |
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Protected 1 sectors |
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=> |
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|
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5. COMPILER |
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----------- |
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To create U-Boot the CodeSourcery's version of the GNU Toolchain for the ColdFire architecture |
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compiler set (freescale-coldfire-4.1-elf) from www.codesourcery.com was used. |
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You can download it from:http://www.codesourcery.com/gnu_toolchains/coldfire/download.html |
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|
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compiler that you used - for example, codesourcery_elf requires -MQ in rules.mk, old M68K 2.95.3 just -M |
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codesourcery_elf requires -MQ in rules.mk, old M68K 2.95.3 just -M |
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@ -0,0 +1,95 @@ |
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/*
|
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* MCF5253 Internal Memory Map |
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* |
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* Copyright (C) 2004-2007 Freescale Semiconductor, Inc. |
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com) |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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|
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#ifndef __IMMAP_5249__ |
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#define __IMMAP_5249__ |
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|
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#define MMAP_INTC (CFG_MBAR + 0x00000040) |
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#define MMAP_DTMR0 (CFG_MBAR + 0x00000140) |
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#define MMAP_DTMR1 (CFG_MBAR + 0x00000180) |
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#define MMAP_UART0 (CFG_MBAR + 0x000001C0) |
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#define MMAP_UART1 (CFG_MBAR + 0x00000200) |
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#define MMAP_I2C0 (CFG_MBAR + 0x00000280) |
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#define MMAP_QSPI (CFG_MBAR + 0x00000400) |
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#define MMAP_CAN0 (CFG_MBAR + 0x00010000) |
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#define MMAP_CAN1 (CFG_MBAR + 0x00011000) |
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|
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#define MMAP_I2C1 (CFG_MBAR2 + 0x00000440) |
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#define MMAP_UART2 (CFG_MBAR2 + 0x00000C00) |
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|
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/*********************************************************************
|
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* ATA Module (ATAC) |
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*********************************************************************/ |
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|
||||
/* Register read/write struct */ |
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typedef struct atac { |
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/* PIO */ |
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u8 toff; /* 0x00 */ |
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u8 ton; /* 0x01 */ |
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u8 t1; /* 0x02 */ |
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u8 t2w; /* 0x03 */ |
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u8 t2r; /* 0x04 */ |
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u8 ta; /* 0x05 */ |
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u8 trd; /* 0x06 */ |
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u8 t4; /* 0x07 */ |
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u8 t9; /* 0x08 */ |
||||
|
||||
/* DMA */ |
||||
u8 tm; /* 0x09 */ |
||||
u8 tn; /* 0x0A */ |
||||
u8 td; /* 0x0B */ |
||||
u8 tk; /* 0x0C */ |
||||
u8 tack; /* 0x0D */ |
||||
u8 tenv; /* 0x0E */ |
||||
u8 trp; /* 0x0F */ |
||||
u8 tzah; /* 0x10 */ |
||||
u8 tmli; /* 0x11 */ |
||||
u8 tdvh; /* 0x12 */ |
||||
u8 tdzfs; /* 0x13 */ |
||||
u8 tdvs; /* 0x14 */ |
||||
u8 tcvh; /* 0x15 */ |
||||
u8 tss; /* 0x16 */ |
||||
u8 tcyc; /* 0x17 */ |
||||
|
||||
/* FIFO */ |
||||
u32 fifo32; /* 0x18 */ |
||||
u16 fifo16; /* 0x1C */ |
||||
u8 rsvd0[2]; |
||||
u8 ffill; /* 0x20 */ |
||||
u8 rsvd1[3]; |
||||
|
||||
/* ATA */ |
||||
u8 cr; /* 0x24 */ |
||||
u8 rsvd2[3]; |
||||
u8 isr; /* 0x28 */ |
||||
u8 rsvd3[3]; |
||||
u8 ier; /* 0x2C */ |
||||
u8 rsvd4[3]; |
||||
u8 icr; /* 0x30 */ |
||||
u8 rsvd5[3]; |
||||
u8 falarm; /* 0x34 */ |
||||
} atac_t; |
||||
|
||||
#endif /* __IMMAP_5249__ */ |
||||
@ -0,0 +1,73 @@ |
||||
/*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc. |
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com) |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef m5253_h |
||||
#define m5253_h |
||||
/****************************************************************************/ |
||||
|
||||
/*
|
||||
* PLL Module (PLL) |
||||
*/ |
||||
|
||||
/* Register read/write macros */ |
||||
#define PLL_PLLCR (0x000180) |
||||
|
||||
#define SIM_RSR (0x000000) |
||||
#define SIM_SYPCR (0x000001) |
||||
#define SIM_SWIVR (0x000002) |
||||
#define SIM_SWSR (0x000003) |
||||
#define SIM_MPARK (0x00000C) |
||||
|
||||
/* Bit definitions and macros for RSR */ |
||||
#define SIM_RSR_SWTR (0x20) |
||||
#define SIM_RSR_HRST (0x80) |
||||
|
||||
/* Register read/write macros */ |
||||
#define CIM_MISCCR (0x000500) |
||||
#define CIM_ATA_DADDR (0x000504) |
||||
#define CIM_ATA_DCOUNT (0x000508) |
||||
#define CIM_RTC_TIME (0x00050C) |
||||
#define CIM_USB_CANCLK (0x000510) |
||||
|
||||
/* Bit definitions and macros for MISCCR */ |
||||
#define CIM_MISCCR_ADTA (0x00000001) |
||||
#define CIM_MISCCR_ADTD (0x00000002) |
||||
#define CIM_MISCCR_ADIE (0x00000004) |
||||
#define CIM_MISCCR_ADIC (0x00000008) |
||||
#define CIM_MISCCR_ADIP (0x00000010) |
||||
#define CIM_MISCCR_CPUEND (0x00000020) |
||||
#define CIM_MISCCR_DMAEND (0x00000040) |
||||
#define CIM_MISCCR_RTCCLR (0x00000080) |
||||
#define CIM_MISCCR_RTCPL (0x00000100) |
||||
#define CIM_MISCCR_URIE (0x00000800) |
||||
#define CIM_MISCCR_URIC (0x00001000) |
||||
#define CIM_MISCCR_URIP (0x00002000) |
||||
|
||||
/* Bit definitions and macros for ATA_DADDR */ |
||||
#define CIM_ATA_DADDR_ATAADDR(x) (((x)&0x00003FFF)<<2) |
||||
#define CIM_ATA_DADDR_RAMADDR(x) (((x)&0x00003FFF)<<18) |
||||
|
||||
/* Bit definitions and macros for ATA_DCOUNT */ |
||||
#define CIM_ATA_DCOUNT_COUNT(x) (((x)&0x0000FFFF)) |
||||
|
||||
#endif /* m5253_h */ |
||||
@ -0,0 +1,213 @@ |
||||
/*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc. |
||||
* Hayden Fraser (Hayden.Fraser@freescale.com) |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef _M5253EVBE_H |
||||
#define _M5253EVBE_H |
||||
|
||||
#define CONFIG_MCF52x2 /* define processor family */ |
||||
#define CONFIG_M5253 /* define processor type */ |
||||
#define CONFIG_M5253EVBE /* define board type */ |
||||
|
||||
#define CONFIG_MCFTMR |
||||
|
||||
#define CONFIG_MCFUART |
||||
#define CFG_UART_PORT (0) |
||||
#define CONFIG_BAUDRATE 19200 |
||||
#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } |
||||
|
||||
#undef CONFIG_WATCHDOG /* disable watchdog */ |
||||
|
||||
#define CONFIG_BOOTDELAY 5 |
||||
|
||||
/* Configuration for environment
|
||||
* Environment is embedded in u-boot in the second sector of the flash |
||||
*/ |
||||
#ifndef CONFIG_MONITOR_IS_IN_RAM |
||||
#define CFG_ENV_OFFSET 0x4000 |
||||
#define CFG_ENV_SECT_SIZE 0x2000 |
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#else |
||||
#define CFG_ENV_ADDR 0xffe04000 |
||||
#define CFG_ENV_SECT_SIZE 0x2000 |
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#endif |
||||
|
||||
/*
|
||||
* BOOTP options |
||||
*/ |
||||
#undef CONFIG_BOOTP_BOOTFILESIZE |
||||
#undef CONFIG_BOOTP_BOOTPATH |
||||
#undef CONFIG_BOOTP_GATEWAY |
||||
#undef CONFIG_BOOTP_HOSTNAME |
||||
|
||||
/*
|
||||
* Command line configuration. |
||||
*/ |
||||
#include <config_cmd_default.h> |
||||
#undef CONFIG_CMD_NET |
||||
#define CONFIG_CMD_LOADB |
||||
#define CONFIG_CMD_LOADS |
||||
#define CONFIG_CMD_EXT2 |
||||
#define CONFIG_CMD_FAT |
||||
#define CONFIG_CMD_IDE |
||||
#define CONFIG_CMD_MEMORY |
||||
#define CONFIG_CMD_MISC |
||||
|
||||
/* ATA */ |
||||
#define CONFIG_DOS_PARTITION |
||||
#define CONFIG_MAC_PARTITION |
||||
#define CONFIG_IDE_RESET 1 |
||||
#define CONFIG_IDE_PREINIT 1 |
||||
#define CONFIG_ATAPI |
||||
#undef CONFIG_LBA48 |
||||
|
||||
#define CFG_IDE_MAXBUS 1 |
||||
#define CFG_IDE_MAXDEVICE 2 |
||||
|
||||
#define CFG_ATA_BASE_ADDR (CFG_MBAR2 + 0x800) |
||||
#define CFG_ATA_IDE0_OFFSET 0 |
||||
|
||||
#define CFG_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */ |
||||
#define CFG_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ |
||||
#define CFG_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ |
||||
#define CFG_ATA_STRIDE 4 /* Interval between registers */ |
||||
#define _IO_BASE 0 |
||||
|
||||
#define CFG_PROMPT "=> " |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
|
||||
#if defined(CONFIG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_LOAD_ADDR 0x00100000 |
||||
|
||||
#define CFG_MEMTEST_START 0x400 |
||||
#define CFG_MEMTEST_END 0x380000 |
||||
|
||||
#define CFG_HZ 1000 |
||||
|
||||
#undef CFG_PLL_BYPASS /* bypass PLL for test purpose */ |
||||
#define CFG_FAST_CLK |
||||
#ifdef CFG_FAST_CLK |
||||
# define CFG_PLLCR 0x1243E054 |
||||
# define CFG_CLK 140000000 |
||||
#else |
||||
# define CFG_PLLCR 0x135a4140 |
||||
# define CFG_CLK 70000000 |
||||
#endif |
||||
|
||||
/*
|
||||
* Low Level Configuration Settings |
||||
* (address mappings, register initial values, etc.) |
||||
* You should know what you are doing if you make changes here. |
||||
*/ |
||||
|
||||
#define CFG_MBAR 0x10000000 /* Register Base Addrs */ |
||||
#define CFG_MBAR2 0x80000000 /* Module Base Addrs 2 */ |
||||
|
||||
/*
|
||||
* Definitions for initial stack pointer and data area (in DPRAM) |
||||
*/ |
||||
#define CFG_INIT_RAM_ADDR 0x20000000 |
||||
#define CFG_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */ |
||||
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
/*
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0 |
||||
*/ |
||||
#define CFG_SDRAM_BASE 0x00000000 |
||||
#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */ |
||||
|
||||
#ifdef CONFIG_MONITOR_IS_IN_RAM |
||||
#define CFG_MONITOR_BASE 0x20000 |
||||
#else |
||||
#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) |
||||
#endif |
||||
|
||||
#define CFG_MONITOR_LEN 0x40000 |
||||
#define CFG_MALLOC_LEN (256 << 10) |
||||
#define CFG_BOOTPARAMS_LEN (64*1024) |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization ?? |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20)) |
||||
|
||||
/* FLASH organization */ |
||||
#define CFG_FLASH_BASE 0xffe00000 |
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
||||
#define CFG_MAX_FLASH_SECT 35 /* max number of sectors on one chip */ |
||||
#define CFG_FLASH_ERASE_TOUT 1000 |
||||
|
||||
#define CFG_FLASH_CFI 1 |
||||
#define CFG_FLASH_CFI_DRIVER 1 |
||||
#define CFG_FLASH_SIZE 0x200000 |
||||
#define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT |
||||
|
||||
/* Cache Configuration */ |
||||
#define CFG_CACHELINE_SIZE 16 |
||||
|
||||
/* Port configuration */ |
||||
#define CFG_FECI2C 0xF0 |
||||
|
||||
#define CFG_CSAR0 0xFFE0 |
||||
#define CFG_CSMR0 0x001F0021 |
||||
#define CFG_CSCR0 0x1D80 |
||||
|
||||
#define CFG_CSAR1 0 |
||||
#define CFG_CSMR1 0 |
||||
#define CFG_CSCR1 0 |
||||
|
||||
#define CFG_CSAR2 0 |
||||
#define CFG_CSMR2 0 |
||||
#define CFG_CSCR2 0 |
||||
|
||||
#define CFG_CSAR3 0 |
||||
#define CFG_CSMR3 0 |
||||
#define CFG_CSCR3 0 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Port configuration |
||||
*/ |
||||
#define CFG_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ |
||||
#define CFG_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */ |
||||
#define CFG_GPIO_EN 0x00000008 /* Set gpio output enable */ |
||||
#define CFG_GPIO1_EN 0x00c70000 /* Set gpio output enable */ |
||||
#define CFG_GPIO_OUT 0x00000008 /* Set outputs to default state */ |
||||
#define CFG_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ |
||||
#define CFG_GPIO1_LED 0x00400000 /* user led */ |
||||
|
||||
#endif /* _M5253EVB_H */ |
||||
|
||||
Loading…
Reference in new issue