diff --git a/arch/arm/dts/stm32h7-u-boot.dtsi b/arch/arm/dts/stm32h7-u-boot.dtsi new file mode 100644 index 0000000..2525035 --- /dev/null +++ b/arch/arm/dts/stm32h7-u-boot.dtsi @@ -0,0 +1,88 @@ +/{ + clocks { + u-boot,dm-pre-reloc; + }; + + soc { + u-boot,dm-pre-reloc; + pin-controller { + u-boot,dm-pre-reloc; + }; + }; +}; + +&clk_hse { + u-boot,dm-pre-reloc; +}; + +&clk_lse { + u-boot,dm-pre-reloc; +}; + +&clk_i2s { + u-boot,dm-pre-reloc; +}; + +&pwrcfg { + u-boot,dm-pre-reloc; +}; + +&rcc { + u-boot,dm-pre-reloc; +}; + +&fmc { + u-boot,dm-pre-reloc; +}; + +&clk_hsi { + u-boot,dm-pre-reloc; +}; + +&clk_csi { + u-boot,dm-pre-reloc; +}; + +&gpioa { + u-boot,dm-pre-reloc; +}; + +&gpiob { + u-boot,dm-pre-reloc; +}; + +&gpioc { + u-boot,dm-pre-reloc; +}; + +&gpiod { + u-boot,dm-pre-reloc; +}; + +&gpioe { + u-boot,dm-pre-reloc; +}; + +&gpiof { + u-boot,dm-pre-reloc; +}; + +&gpiog { + u-boot,dm-pre-reloc; +}; + +&gpioh { + u-boot,dm-pre-reloc; +}; + +&gpioi { + u-boot,dm-pre-reloc; +}; + +&gpioj { + u-boot,dm-pre-reloc; +}; + +&gpiok { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/stm32h743-pinctrl.dtsi b/arch/arm/dts/stm32h743-pinctrl.dtsi index 76bbd65..d3e11d5 100644 --- a/arch/arm/dts/stm32h743-pinctrl.dtsi +++ b/arch/arm/dts/stm32h743-pinctrl.dtsi @@ -54,88 +54,99 @@ gpioa: gpio@58020000 { gpio-controller; #gpio-cells = <2>; + compatible = "st,stm32-gpio"; reg = <0x0 0x400>; - clocks = <&timer_clk>; + clocks = <&rcc GPIOA_CK>; st,bank-name = "GPIOA"; }; gpiob: gpio@58020400 { gpio-controller; #gpio-cells = <2>; + compatible = "st,stm32-gpio"; reg = <0x400 0x400>; - clocks = <&timer_clk>; + clocks = <&rcc GPIOB_CK>; st,bank-name = "GPIOB"; }; gpioc: gpio@58020800 { gpio-controller; #gpio-cells = <2>; + compatible = "st,stm32-gpio"; reg = <0x800 0x400>; - clocks = <&timer_clk>; + clocks = <&rcc GPIOC_CK>; st,bank-name = "GPIOC"; }; gpiod: gpio@58020c00 { gpio-controller; #gpio-cells = <2>; + compatible = "st,stm32-gpio"; reg = <0xc00 0x400>; - clocks = <&timer_clk>; + clocks = <&rcc GPIOD_CK>; st,bank-name = "GPIOD"; }; gpioe: gpio@58021000 { gpio-controller; #gpio-cells = <2>; + compatible = "st,stm32-gpio"; reg = <0x1000 0x400>; - clocks = <&timer_clk>; + clocks = <&rcc GPIOE_CK>; st,bank-name = "GPIOE"; }; gpiof: gpio@58021400 { gpio-controller; #gpio-cells = <2>; + compatible = "st,stm32-gpio"; reg = <0x1400 0x400>; - clocks = <&timer_clk>; + clocks = <&rcc GPIOF_CK>; st,bank-name = "GPIOF"; }; gpiog: gpio@58021800 { gpio-controller; #gpio-cells = <2>; + compatible = "st,stm32-gpio"; reg = <0x1800 0x400>; - clocks = <&timer_clk>; + clocks = <&rcc GPIOG_CK>; st,bank-name = "GPIOG"; }; gpioh: gpio@58021c00 { gpio-controller; #gpio-cells = <2>; + compatible = "st,stm32-gpio"; reg = <0x1c00 0x400>; - clocks = <&timer_clk>; + clocks = <&rcc GPIOH_CK>; st,bank-name = "GPIOH"; }; gpioi: gpio@58022000 { gpio-controller; #gpio-cells = <2>; + compatible = "st,stm32-gpio"; reg = <0x2000 0x400>; - clocks = <&timer_clk>; + clocks = <&rcc GPIOI_CK>; st,bank-name = "GPIOI"; }; gpioj: gpio@58022400 { gpio-controller; #gpio-cells = <2>; + compatible = "st,stm32-gpio"; reg = <0x2400 0x400>; - clocks = <&timer_clk>; + clocks = <&rcc GPIOJ_CK>; st,bank-name = "GPIOJ"; }; gpiok: gpio@58022800 { gpio-controller; #gpio-cells = <2>; + compatible = "st,stm32-gpio"; reg = <0x2800 0x400>; - clocks = <&timer_clk>; + clocks = <&rcc GPIOK_CK>; st,bank-name = "GPIOK"; }; @@ -164,6 +175,75 @@ bias-disable; }; }; + + fmc_pins: fmc@0 { + pins { + pinmux = , + , + , + , + , + , + , + + , + , + , + , + , + , + , + , + , + , + , + + , + , + , + , + , + , + , + , + , + , + , + + , + , + , + , + , + , + , + + , + , + , + , + , + , + , + , + , + , + , + + , + , + , + , + , + , + , + , + , + ; + + slew-rate = <3>; + }; + }; }; }; }; diff --git a/arch/arm/dts/stm32h743.dtsi b/arch/arm/dts/stm32h743.dtsi index 36a99db..16e9308 100644 --- a/arch/arm/dts/stm32h743.dtsi +++ b/arch/arm/dts/stm32h743.dtsi @@ -42,45 +42,83 @@ #include "skeleton.dtsi" #include "armv7-m.dtsi" +#include / { clocks { clk_hse: clk-hse { #clock-cells = <0>; compatible = "fixed-clock"; - clock-frequency = <0>; + clock-frequency = <25000000>; + }; + + clk_lse: clk-lse { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; }; - timer_clk: timer-clk { + clk_i2s: i2s_ckin { #clock-cells = <0>; compatible = "fixed-clock"; - clock-frequency = <125000000>; + clock-frequency = <0>; }; }; soc { + rcc: rcc@58024400 { + #clock-cells = <1>; + #reset-cells = <1>; + compatible = "st,stm32h743-rcc", "st,stm32-rcc"; + reg = <0x58024400 0x400>; + clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s>, <&clk_hsi>, <&clk_csi>; + st,syscfg = <&pwrcfg>; + }; + usart1: serial@40011000 { - compatible = "st,stm32f7-usart", "st,stm32f7-uart"; + compatible = "st,stm32h7-usart", "st,stm32h7-uart"; reg = <0x40011000 0x400>; interrupts = <37>; status = "disabled"; - clocks = <&timer_clk>; - + clocks = <&rcc USART1_CK>; }; usart2: serial@40004400 { - compatible = "st,stm32f7-usart", "st,stm32f7-uart"; + compatible = "st,stm32h7-usart", "st,stm32h7-uart"; reg = <0x40004400 0x400>; interrupts = <38>; status = "disabled"; - clocks = <&timer_clk>; + clocks = <&rcc USART2_CK>; }; timer5: timer@40000c00 { compatible = "st,stm32-timer"; reg = <0x40000c00 0x400>; interrupts = <50>; - clocks = <&timer_clk>; + clocks = <&rcc TIM5_CK>; + }; + + pwrcfg: power-config@58024800 { + compatible = "syscon"; + reg = <0x58024800 0x400>; + }; + + fmc: fmc@52004000 { + compatible = "st,stm32h7-fmc"; + reg = <0x52004000 0x1000>; + clocks = <&rcc FMC_CK>; + }; + + clk_hsi: clk-hsi { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <64000000>; + }; + + clk_csi: clk-csi { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <4000000>; }; }; }; diff --git a/arch/arm/dts/stm32h743i-disco.dts b/arch/arm/dts/stm32h743i-disco.dts index 79e841d..bef7e90 100644 --- a/arch/arm/dts/stm32h743i-disco.dts +++ b/arch/arm/dts/stm32h743i-disco.dts @@ -43,6 +43,7 @@ /dts-v1/; #include "stm32h743.dtsi" #include "stm32h743-pinctrl.dtsi" +#include / { model = "STMicroelectronics STM32H743i-Discovery board"; @@ -59,15 +60,41 @@ aliases { serial0 = &usart2; + gpio0 = &gpioa; + gpio1 = &gpiob; + gpio2 = &gpioc; + gpio3 = &gpiod; + gpio4 = &gpioe; + gpio5 = &gpiof; + gpio6 = &gpiog; + gpio7 = &gpioh; + gpio8 = &gpioi; + gpio9 = &gpioj; + gpio10 = &gpiok; }; }; -&clk_hse { - clock-frequency = <125000000>; -}; - &usart2 { pinctrl-0 = <&usart2_pins>; pinctrl-names = "default"; status = "okay"; }; + +&fmc { + pinctrl-0 = <&fmc_pins>; + pinctrl-names = "default"; + status = "okay"; + + /* + * Memory configuration from sdram datasheet IS42S32800G-6BLI + * firsct bank is bank@0 + * second bank is bank@1 + */ + bank1: bank@1 { + st,sdram-control = /bits/ 8 ; + st,sdram-timing = /bits/ 8 ; + st,sdram-refcount = <1539>; + }; +}; diff --git a/arch/arm/dts/stm32h743i-eval.dts b/arch/arm/dts/stm32h743i-eval.dts index c6effbb..0e01ce5 100644 --- a/arch/arm/dts/stm32h743i-eval.dts +++ b/arch/arm/dts/stm32h743i-eval.dts @@ -43,6 +43,7 @@ /dts-v1/; #include "stm32h743.dtsi" #include "stm32h743-pinctrl.dtsi" +#include / { model = "STMicroelectronics STM32H743i-EVAL board"; @@ -59,16 +60,41 @@ aliases { serial0 = &usart1; + gpio0 = &gpioa; + gpio1 = &gpiob; + gpio2 = &gpioc; + gpio3 = &gpiod; + gpio4 = &gpioe; + gpio5 = &gpiof; + gpio6 = &gpiog; + gpio7 = &gpioh; + gpio8 = &gpioi; + gpio9 = &gpioj; + gpio10 = &gpiok; }; }; -&clk_hse { - clock-frequency = <125000000>; -}; - &usart1 { pinctrl-0 = <&usart1_pins>; pinctrl-names = "default"; status = "okay"; }; +&fmc { + pinctrl-0 = <&fmc_pins>; + pinctrl-names = "default"; + status = "okay"; + + /* + * Memory configuration from sdram datasheet IS42S32800G-6BLI + * firsct bank is bank@0 + * second bank is bank@1 + */ + bank2: bank@1 { + st,sdram-control = /bits/ 8 ; + st,sdram-timing = /bits/ 8 ; + st,sdram-refcount = <1539>; + }; +}; diff --git a/include/dt-bindings/memory/stm32-sdram.h b/include/dt-bindings/memory/stm32-sdram.h index 89b719a..c2b911f 100644 --- a/include/dt-bindings/memory/stm32-sdram.h +++ b/include/dt-bindings/memory/stm32-sdram.h @@ -18,7 +18,9 @@ #define CAS_1 0x1 #define CAS_2 0x2 #define CAS_3 0x3 +#define SDCLK_DIS 0x0 #define SDCLK_2 0x2 +#define SDCLK_3 0x3 #define RD_BURST_EN 0x1 #define RD_BURST_DIS 0x0 #define RD_PIPE_DL_0 0x0 @@ -26,12 +28,17 @@ #define RD_PIPE_DL_2 0x2 /* Timing = value +1 cycles */ +#define TMRD_1 (1 - 1) #define TMRD_2 (2 - 1) +#define TXSR_1 (1 - 1) #define TXSR_6 (6 - 1) +#define TRAS_1 (1 - 1) #define TRAS_4 (4 - 1) #define TRC_6 (6 - 1) +#define TWR_1 (1 - 1) #define TWR_2 (2 - 1) #define TRP_2 (2 - 1) +#define TRCD_1 (1 - 1) #define TRCD_2 (2 - 1) #endif