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@ -1678,14 +1678,6 @@ struct e1000_hw { |
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#define EEPROM_EWEN_OPCODE 0x13 /* EERPOM erase/write enable */ |
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#define EEPROM_EWDS_OPCODE 0x10 /* EERPOM erast/write disable */ |
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/* EEPROM Word Offsets */ |
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#define EEPROM_COMPAT 0x0003 |
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#define EEPROM_ID_LED_SETTINGS 0x0004 |
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#define EEPROM_INIT_CONTROL1_REG 0x000A |
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#define EEPROM_INIT_CONTROL2_REG 0x000F |
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#define EEPROM_FLASH_VERSION 0x0032 |
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#define EEPROM_CHECKSUM_REG 0x003F |
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/* Word definitions for ID LED Settings */ |
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#define ID_LED_RESERVED_0000 0x0000 |
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#define ID_LED_RESERVED_FFFF 0xFFFF |
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@ -2479,7 +2471,6 @@ struct e1000_hw { |
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#define ADVERTISE_100_FULL 0x0008 |
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#define ADVERTISE_1000_HALF 0x0010 |
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#define ADVERTISE_1000_FULL 0x0020 |
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#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* Everything but 1000-Half */ |
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#define ICH_FLASH_GFPREG 0x0000 |
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#define ICH_FLASH_HSFSTS 0x0004 |
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@ -2504,7 +2495,6 @@ struct e1000_hw { |
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#define ICH_GFPREG_BASE_MASK 0x1FFF |
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#define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF |
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#define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */ |
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#define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */ |
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/* SPI EEPROM Status Register */ |
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@ -2599,7 +2589,6 @@ struct e1000_hw { |
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#define PHY_CFG_TIMEOUT 100 |
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#define DEFAULT_80003ES2LAN_TIPG_IPGT_10_100 0x00000009 |
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#define DEFAULT_80003ES2LAN_TIPG_IPGT_1000 0x00000008 |
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#define E1000_TXDMAC_DPP 0x00000001 |
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#define AUTO_ALL_MODES 0 |
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#ifndef E1000_MASTER_SLAVE |
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