diff --git a/CHANGELOG b/CHANGELOG
index cbc18d9..6edcd25 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,11 @@
 Changes since U-Boot 1.1.4:
 ======================================================================
 
+* Update for NC650 board:
+  - Support rev1 and rev2 hardware
+  - adapt to new NAND layer
+  - add CP850 configuration based on NC650
+
 * MPC5200: enable snooping of DMA transactions on XLB even if no PCI
   is configured; othrwise DMA accesses aren't cache coherent which
   causes for example USB to fail.
diff --git a/Makefile b/Makefile
index 9b93463..249c9f0 100644
--- a/Makefile
+++ b/Makefile
@@ -633,8 +633,21 @@ NETTA2_config:		unconfig
 		 }
 	@./mkconfig -a $(call xtract_NETTA2,$@) ppc mpc8xx netta2
 
-NC650_config:	unconfig
-	@./mkconfig $(@:_config=) ppc mpc8xx nc650
+NC650_Rev1_config \
+NC650_Rev2_config \
+CP850_config:	unconfig
+	@ >include/config.h
+	@[ -z "$(findstring CP850,$@)" ] || \
+		 { echo "#define CONFIG_CP850 1" >>include/config.h ; \
+		   echo "#define CONFIG_IDS852_REV2 1" >>include/config.h ; \
+		 }
+	@[ -z "$(findstring Rev1,$@)" ] || \
+		 { echo "#define CONFIG_IDS852_REV1 1" >>include/config.h ; \
+		 }
+	@[ -z "$(findstring Rev2,$@)" ] || \
+		 { echo "#define CONFIG_IDS852_REV2 1" >>include/config.h ; \
+		 }
+	@./mkconfig -a NC650 ppc mpc8xx nc650
 
 NX823_config:		unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx nx823
diff --git a/board/nc650/Makefile b/board/nc650/Makefile
index a4dd85f..8dc4934 100644
--- a/board/nc650/Makefile
+++ b/board/nc650/Makefile
@@ -1,4 +1,5 @@
 #
+# (C) Copyright 2006 Detlev Zundel, dzu@denx.de
 # (C) Copyright 2004
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
@@ -25,7 +26,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= lib$(BOARD).a
 
-OBJS	= $(BOARD).o flash.o
+OBJS	= $(BOARD).o nand.o flash.o
 
 $(LIB):	.depend $(OBJS)
 	$(AR) crv $@ $(OBJS)
diff --git a/board/nc650/config.mk b/board/nc650/config.mk
index fa8ba31..5b2284a 100644
--- a/board/nc650/config.mk
+++ b/board/nc650/config.mk
@@ -1,4 +1,5 @@
 #
+# (C) Copyright 2006 Detlev Zundel, dzu@denx.de
 # (C) Copyright 2004
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
@@ -26,3 +27,4 @@
 #
 
 TEXT_BASE = 0x40700000
+BOARDLIBS = drivers/nand/libnand.a
diff --git a/board/nc650/nc650.c b/board/nc650/nc650.c
index fe96b93..c90ac9c 100644
--- a/board/nc650/nc650.c
+++ b/board/nc650/nc650.c
@@ -1,4 +1,5 @@
 /*
+ * (C) Copyright 2006 Detlev Zundel, dzu@denx.de
  * (C) Copyright 2001
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
@@ -108,7 +109,16 @@ const uint nand_flash_table[] = {
 
 int checkboard (void)
 {
-	puts ("Board: NC650\n");
+#if !defined(CONFIG_CP850)
+	puts ("Board: NC650");
+#else
+	puts ("Board: CP850");
+#endif
+#if defined(CONFIG_IDS852_REV1)
+	puts (" with IDS852 rev 1 module\n");
+#elif defined(CONFIG_IDS852_REV2)
+	puts (" with IDS852 rev 2 module\n");
+#endif
 	return 0;
 }
 
@@ -241,13 +251,61 @@ static long int dram_size (long int mamr_value, long int *base, long int maxsize
 	return (get_ram_size(base, maxsize));
 }
 
-#if (CONFIG_COMMANDS & CFG_CMD_NAND)
-void nand_init(void)
-{
-	extern unsigned long nand_probe(unsigned long physadr);
 
-	unsigned long totlen = nand_probe(CFG_NAND_BASE);
+#if defined(CONFIG_CP850)
+
+#define DPRAM_VARNAME           "KP850DIP"
+#define PARAM_ADDR              0x7C0
+#define NAME_ADDR               0x7F8
+#define BOARD_NAME              "KP01"
+#define DEFAULT_LB              "241111"
 
-	printf ("%4lu MB\n", totlen >> 20);
+int misc_init_r(void)
+{
+	int             iCompatMode = 0;
+	char            *pParam = NULL;
+	char            *envlb;
+	
+	/* 
+	   First byte in CPLD read address space signals compatibility mode
+	   0 - cp850
+	   1 - kp852
+	*/
+	pParam = (char*)(CFG_CPLD_BASE);
+	if( *pParam != 0)
+		iCompatMode = 1;
+	
+	if ( iCompatMode != 0) {
+		/* 
+		   In KP852 compatibility mode we have to write to
+		   DPRAM as early as possible the binary coded
+		   line config and board name.
+		   The line config is derived from the environment
+		   variable DPRAM_VARNAME by converting from ASCII
+		   to binary per character.
+		*/
+		if ( (envlb = getenv ( DPRAM_VARNAME )) == 0) {
+			setenv( DPRAM_VARNAME, DEFAULT_LB);
+			envlb = DEFAULT_LB;
+		}
+		
+		/* Status string */
+		printf("Mode:  KP852(LB=%s)\n", envlb);
+
+		/* copy appl init */
+		pParam = (char*)(DPRAM_BASE_ADDR + PARAM_ADDR);
+		while (*envlb) {
+			*(pParam++) = *(envlb++) - '0';
+		}
+		*pParam = '\0';
+
+		/* copy board id */
+		pParam = (char*)(DPRAM_BASE_ADDR + NAME_ADDR);
+		strcpy( pParam, BOARD_NAME);
+	} else {
+		puts("Mode:  CP850\n");
+	}
+	
+	return 0;
 }
 #endif
diff --git a/include/configs/NC650.h b/include/configs/NC650.h
index 3c59df4..8da29c4 100644
--- a/include/configs/NC650.h
+++ b/include/configs/NC650.h
@@ -1,4 +1,5 @@
 /*
+ * (C) Copyright 2006 Detlev Zundel, dzu@denx.de
  * (C) Copyright 2005
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
@@ -65,6 +66,11 @@
 #define CFG_8XX_XIN			CONFIG_8xx_OSCLK
 
 #define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_PROMPT		"\nEnter password - autoboot in %d seconds...\n"
+#define CONFIG_AUTOBOOT_DELAY_STR	"ids"
+#define CONFIG_BOOT_RETRY_TIME		900
+#define CONFIG_BOOT_RETRY_MIN		30
 
 #define CONFIG_PREBOOT	"echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
 
@@ -75,7 +81,7 @@
 	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" 	\
 	"bootm"
 
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+#define CONFIG_WATCHDOG			/* watchdog enabled 		*/
 
 #undef	CONFIG_STATUS_LED		/* Status LED disabled		*/
 
@@ -96,12 +102,26 @@
 /*
  * Software (bit-bang) I2C driver configuration
  */
+#if defined(CONFIG_IDS852_REV1)
+
 #define SCL		0x1000		/* PA 3 */
 #define SDA		0x2000		/* PA 2 */
 
 #define __I2C_DIR	immr->im_ioport.iop_padir
 #define __I2C_DAT	immr->im_ioport.iop_padat
 #define __I2C_PAR	immr->im_ioport.iop_papar
+
+#elif defined(CONFIG_IDS852_REV2)
+
+#define SCL		0x0002		/* PB 30 */
+#define SDA		0x0001		/* PB 31 */
+
+#define __I2C_PAR	immr->im_cpm.cp_pbpar
+#define __I2C_DIR	immr->im_cpm.cp_pbdir
+#define __I2C_DAT	immr->im_cpm.cp_pbdat
+
+#endif
+
 #define	I2C_INIT	{ __I2C_PAR &= ~(SDA|SCL);	\
 			  __I2C_DIR |= (SDA|SCL);	}
 #define	I2C_READ	((__I2C_DAT & SDA) ? 1 : 0)
@@ -229,17 +249,6 @@
 #define ADDR_COLUMN		1
 #define NAND_NO_RB
 
-#define NAND_WAIT_READY(nand)		udelay(12)
-#define WRITE_NAND_COMMAND(d, adr)	WRITE_NAND(d, adr + 2)
-#define WRITE_NAND_ADDRESS(d, adr)	WRITE_NAND(d, adr + 1)
-#define WRITE_NAND(d, adr)		(*(volatile uint8_t *)(adr) = (uint8_t)(d))
-#define READ_NAND(adr)			(*(volatile uint8_t *)(adr))
-#define NAND_DISABLE_CE(nand)		/* nop */
-#define NAND_ENABLE_CE(nand)		/* nop */
-#define NAND_CTL_CLRALE(nandptr)	/* nop */
-#define NAND_CTL_SETALE(nandptr)	/* nop */
-#define NAND_CTL_CLRCLE(nandptr)	/* nop */
-#define NAND_CTL_SETCLE(nandptr)	/* nop */
 
 /*-----------------------------------------------------------------------
  * SYPCR - System Protection Control					11-9
@@ -312,7 +321,8 @@
 #define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V)
 
 /*
- * BR2 and OR2 (NAND Flash) - now addressed through UPMB
+ * BR2 and OR2 (NAND Flash) - addressed through UPMB on rev 1
+ * rev2 only uses the chipselect
  */
 #define CFG_NAND_BASE		0x50000000
 #define CFG_NAND_SIZE		0x04000000
@@ -338,6 +348,18 @@
 #define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V)
 
 /*
+ * BR4 and OR4 (CPLD)
+ */
+#define CFG_CPLD_BASE           0x80000000      /* CPLD                 */
+#define CFG_CPLD_SIZE           0x10000         /* only 16 used         */
+
+#define CFG_OR_TIMING_CPLD	(OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
+				 OR_SCY_1_CLK)
+
+#define CFG_BR4_PRELIM  ((CFG_CPLD_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
+#define CFG_OR4_PRELIM  (((-CFG_CPLD_SIZE) & OR_AM_MSK) | CFG_OR_TIMING_CPLD)
+
+/*
  * BR5 and OR5 (SRAM)
  */
 #define CFG_SRAM_BASE		0x60000000
@@ -349,6 +371,16 @@
 #define CFG_BR5_PRELIM  ((CFG_SRAM_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
 #define CFG_OR5_PRELIM  (((-CFG_SRAM_SIZE) & OR_AM_MSK) | CFG_OR_TIMING_SRAM)
 
+#if defined(CONFIG_CP850)
+/*
+ *  BR6 and OR6 (DPRAM) - only on CP850
+ */
+#define CFG_OR6_PRELIM          0xffff8170
+#define CFG_BR6_PRELIM          0xa0000401
+#define DPRAM_BASE_ADDR         0xa0000000
+
+#define CONFIG_MISC_INIT_R      1
+#endif
 
 /*
  * 4096 Rows from SDRAM example configuration
@@ -413,14 +445,12 @@
 #define CONFIG_JFFS2_PART_OFFSET	0x00000000
 
 /* mtdparts command line support */
-/*
 #define CONFIG_JFFS2_CMDLINE
 #define MTDIDS_DEFAULT		"nor0=nc650-0,nand0=nc650-nand"
 
 #define MTDPARTS_DEFAULT	"mtdparts=nc650-0:1m(kernel1),1m(kernel2)," \
-					"2560k(cramfs1),2560k(cramfs2)," \
-					"256k(u-boot),256k(env);" \
-				"nc650-nand:4m(nand1),28m(nand2)"
-*/
+					"4m(cramfs1),1m(cramfs2)," \
+					"256k(u-boot),128k(env);" \
+				"nc650-nand:4m(jffs1),28m(jffs2)"
 
 #endif	/* __CONFIG_H */