PDM360NG is a MPC5121E based board by ifm ecomatic gmbh. Signed-off-by: Michael Weiss <michael.weiss@ifm.com> Signed-off-by: Detlev Zundel <dzu@denx.de> Signed-off-by: Anatolij Gustschin <agust@denx.de>master
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#
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# (C) Copyright 2007
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(BOARD).a
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COBJS-y := $(BOARD).o
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COBJS := $(COBJS-y)
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) |
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$(AR) $(ARFLAGS) $@ $(OBJS)
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clean: |
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rm -f $(SOBJS) $(OBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak $(obj).depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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#
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# (C) Copyright 2009
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# Michael Weiß, ifm ecomatic gmbh, michael.weiss@ifm.com
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
|
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
|
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#
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
|
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#
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# You should have received a copy of the GNU General Public License
|
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# along with this program; if not, write to the Free Software
|
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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TEXT_BASE = 0xF0000000
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/*
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* (C) Copyright 2009, 2010 Wolfgang Denk <wd@denx.de> |
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* |
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* (C) Copyright 2009-2010 |
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* Michael Weiß, ifm ecomatic gmbh, michael.weiss@ifm.com |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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* |
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*/ |
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#include <common.h> |
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#include <asm/bitops.h> |
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#include <command.h> |
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#include <asm/io.h> |
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#include <asm/processor.h> |
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#include <asm/mpc512x.h> |
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#include <fdt_support.h> |
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#include <flash.h> |
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#ifdef CONFIG_MISC_INIT_R |
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#include <i2c.h> |
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#endif |
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#include <serial.h> |
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#include <jffs2/load_kernel.h> |
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#include <mtd_node.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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extern flash_info_t flash_info[]; |
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ulong flash_get_size (phys_addr_t base, int banknum); |
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/* Clocks in use */ |
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#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \ |
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CLOCK_SCCR1_LPC_EN | \
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CLOCK_SCCR1_NFC_EN | \
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CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
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CLOCK_SCCR1_PSCFIFO_EN | \
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CLOCK_SCCR1_DDR_EN | \
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CLOCK_SCCR1_FEC_EN | \
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CLOCK_SCCR1_TPR_EN) |
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#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \ |
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CLOCK_SCCR2_SPDIF_EN | \
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CLOCK_SCCR2_DIU_EN | \
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CLOCK_SCCR2_I2C_EN) |
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int board_early_init_f(void) |
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{ |
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volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; |
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/*
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* Initialize Local Window for FLASH-Bank1 access (CS1) |
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*/ |
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out_be32(&im->sysconf.lpcs1aw, |
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CSAW_START(CONFIG_SYS_FLASH1_BASE) | |
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CSAW_STOP(CONFIG_SYS_FLASH1_BASE, CONFIG_SYS_FLASH_SIZE) |
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); |
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out_be32(&im->lpc.cs_cfg[1], CONFIG_SYS_CS1_CFG); |
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/*
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* Local Window for MRAM access (CS2) |
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*/ |
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out_be32(&im->sysconf.lpcs2aw, |
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CSAW_START(CONFIG_SYS_MRAM_BASE) | |
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CSAW_STOP(CONFIG_SYS_MRAM_BASE, CONFIG_SYS_MRAM_SIZE) |
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); |
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out_be32(&im->lpc.cs_cfg[2], CONFIG_SYS_CS2_CFG); |
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sync_law(&im->sysconf.lpcs2aw); |
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/*
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* Configure Flash Speed |
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*/ |
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out_be32(&im->lpc.cs_cfg[0], CONFIG_SYS_CS0_CFG); |
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out_be32(&im->lpc.altr, CONFIG_SYS_CS_ALETIMING); |
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/*
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* Enable clocks |
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*/ |
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out_be32(&im->clk.sccr[0], SCCR1_CLOCKS_EN); |
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out_be32(&im->clk.sccr[1], SCCR2_CLOCKS_EN); |
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#if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE) |
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setbits_be32(&im->clk.sccr[1], CLOCK_SCCR2_IIM_EN); |
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#endif |
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return 0; |
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} |
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sdram_conf_t mddrc_config[] = { |
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{ |
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(512 << 20), /* 512 MB RAM configuration */ |
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{ |
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CONFIG_SYS_MDDRC_SYS_CFG, |
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CONFIG_SYS_MDDRC_TIME_CFG0, |
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CONFIG_SYS_MDDRC_TIME_CFG1, |
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CONFIG_SYS_MDDRC_TIME_CFG2 |
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} |
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}, |
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{ |
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(128 << 20), /* 128 MB RAM configuration */ |
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{ |
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CONFIG_SYS_MDDRC_SYS_CFG_ALT1, |
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CONFIG_SYS_MDDRC_TIME_CFG0_ALT1, |
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CONFIG_SYS_MDDRC_TIME_CFG1_ALT1, |
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CONFIG_SYS_MDDRC_TIME_CFG2_ALT1 |
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} |
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}, |
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}; |
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phys_size_t initdram (int board_type) |
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{ |
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int i; |
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u32 msize = 0; |
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u32 pdm360ng_init_seq[] = { |
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CONFIG_SYS_DDRCMD_NOP, |
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CONFIG_SYS_DDRCMD_NOP, |
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CONFIG_SYS_DDRCMD_NOP, |
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CONFIG_SYS_DDRCMD_NOP, |
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CONFIG_SYS_DDRCMD_NOP, |
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CONFIG_SYS_DDRCMD_NOP, |
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CONFIG_SYS_DDRCMD_NOP, |
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CONFIG_SYS_DDRCMD_NOP, |
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CONFIG_SYS_DDRCMD_NOP, |
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CONFIG_SYS_DDRCMD_NOP, |
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CONFIG_SYS_DDRCMD_PCHG_ALL, |
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CONFIG_SYS_DDRCMD_NOP, |
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CONFIG_SYS_DDRCMD_RFSH, |
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CONFIG_SYS_DDRCMD_NOP, |
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CONFIG_SYS_DDRCMD_RFSH, |
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CONFIG_SYS_DDRCMD_NOP, |
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CONFIG_SYS_MICRON_INIT_DEV_OP, |
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CONFIG_SYS_DDRCMD_NOP, |
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CONFIG_SYS_DDRCMD_EM2, |
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CONFIG_SYS_DDRCMD_NOP, |
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CONFIG_SYS_DDRCMD_PCHG_ALL, |
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CONFIG_SYS_DDRCMD_EM2, |
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CONFIG_SYS_DDRCMD_EM3, |
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CONFIG_SYS_DDRCMD_EN_DLL, |
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CONFIG_SYS_DDRCMD_RES_DLL, |
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CONFIG_SYS_DDRCMD_PCHG_ALL, |
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CONFIG_SYS_DDRCMD_RFSH, |
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CONFIG_SYS_DDRCMD_RFSH, |
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CONFIG_SYS_MICRON_INIT_DEV_OP, |
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CONFIG_SYS_DDRCMD_OCD_DEFAULT, |
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CONFIG_SYS_DDRCMD_OCD_EXIT, |
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CONFIG_SYS_DDRCMD_PCHG_ALL, |
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CONFIG_SYS_DDRCMD_NOP |
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}; |
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for (i = 0; i < ARRAY_SIZE(mddrc_config); i++) { |
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msize = fixed_sdram(&mddrc_config[i].cfg, pdm360ng_init_seq, |
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ARRAY_SIZE(pdm360ng_init_seq)); |
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if (msize == mddrc_config[i].size) |
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break; |
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} |
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return msize; |
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} |
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#if defined(CONFIG_SERIAL_MULTI) |
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static int set_lcd_brightness(char *); |
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#endif |
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int misc_init_r(void) |
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{ |
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volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; |
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/*
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* Re-configure flash setup using auto-detected info |
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*/ |
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if (flash_info[1].size > 0) { |
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out_be32(&im->sysconf.lpcs1aw, |
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CSAW_START(gd->bd->bi_flashstart + flash_info[1].size) | |
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CSAW_STOP(gd->bd->bi_flashstart + flash_info[1].size, |
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flash_info[1].size)); |
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sync_law(&im->sysconf.lpcs1aw); |
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/*
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* Re-check to get correct base address |
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*/ |
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flash_get_size (gd->bd->bi_flashstart + flash_info[1].size, 1); |
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} else { |
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/* Disable Bank 1 */ |
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out_be32(&im->sysconf.lpcs1aw, 0x01000100); |
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sync_law(&im->sysconf.lpcs1aw); |
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} |
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out_be32(&im->sysconf.lpcs0aw, |
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CSAW_START(gd->bd->bi_flashstart) | |
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CSAW_STOP(gd->bd->bi_flashstart, flash_info[0].size)); |
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sync_law(&im->sysconf.lpcs0aw); |
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/*
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* Re-check to get correct base address |
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*/ |
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flash_get_size (gd->bd->bi_flashstart, 0); |
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/*
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* Re-do flash protection upon new addresses |
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*/ |
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flash_protect (FLAG_PROTECT_CLEAR, |
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gd->bd->bi_flashstart, 0xffffffff, |
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&flash_info[0]); |
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/* Monitor protection ON by default */ |
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flash_protect (FLAG_PROTECT_SET, |
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CONFIG_SYS_MONITOR_BASE, |
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CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1, |
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&flash_info[0]); |
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/* Environment protection ON by default */ |
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flash_protect (FLAG_PROTECT_SET, |
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CONFIG_ENV_ADDR, |
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CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, |
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&flash_info[0]); |
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#ifdef CONFIG_ENV_ADDR_REDUND |
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/* Redundant environment protection ON by default */ |
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flash_protect (FLAG_PROTECT_SET, |
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CONFIG_ENV_ADDR_REDUND, |
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CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, |
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&flash_info[0]); |
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#endif |
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#ifdef CONFIG_FSL_DIU_FB |
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# if !(defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)) |
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mpc5121_diu_init(); |
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#endif |
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#if defined(CONFIG_SERIAL_MULTI) |
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set_lcd_brightness(0); |
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#endif |
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/* Switch LCD-Backlight and LVDS-Interface on */ |
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setbits_be32(&im->gpio.gpdir, 0x01040000); |
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clrsetbits_be32(&im->gpio.gpdat, 0x01000000, 0x00040000); |
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#endif |
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#if defined(CONFIG_HARD_I2C) |
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if (!getenv("ethaddr")) { |
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uchar buf[6]; |
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uchar ifm_oui[3] = { 0, 2, 1, }; |
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int ret; |
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/* I2C-0 for on-board eeprom */ |
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i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS_NUM); |
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/* Read ethaddr from EEPROM */ |
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ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, |
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CONFIG_SYS_I2C_EEPROM_MAC_OFFSET, 1, buf, 6); |
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if (ret != 0) { |
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printf("Error: Unable to read MAC from I2C" |
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" EEPROM at address %02X:%02X\n", |
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CONFIG_SYS_I2C_EEPROM_ADDR, |
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CONFIG_SYS_I2C_EEPROM_MAC_OFFSET); |
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return 1; |
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} |
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/* Owned by IFM ? */ |
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if (memcmp(buf, ifm_oui, sizeof(ifm_oui))) { |
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printf("Illegal MAC address in EEPROM: %pM\n", buf); |
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return 1; |
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} |
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eth_setenv_enetaddr("ethaddr", buf); |
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} |
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#endif /* defined(CONFIG_HARD_I2C) */ |
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return 0; |
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} |
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static iopin_t ioregs_init[] = { |
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/* FUNC1=LPC_CS4 */ |
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{ |
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offsetof(struct ioctrl512x, io_control_pata_ce1), 1, 0, |
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IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(1) | |
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IO_PIN_PUE(1) | IO_PIN_ST(0) | IO_PIN_DS(3) |
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}, |
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/* FUNC3=GPIO10 */ |
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{ |
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offsetof(struct ioctrl512x, io_control_pata_ce2), 1, 0, |
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IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0) |
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}, |
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/* FUNC1=CAN3_TX */ |
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{ |
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offsetof(struct ioctrl512x, io_control_pata_isolate), 1, 0, |
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IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0) |
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}, |
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/* FUNC3=GPIO14 */ |
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{ |
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offsetof(struct ioctrl512x, io_control_pata_iochrdy), 1, 0, |
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IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0) |
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}, |
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/* FUNC2=DIU_LD22 Sets Next 2 to DIU_LD pads */ |
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/* DIU_LD22-DIU_LD23 */ |
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{ |
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offsetof(struct ioctrl512x, io_control_pci_ad31), 2, 0, |
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IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1) |
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}, |
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/* FUNC2=USB1_DATA7 Sets Next 12 to USB1 pads */ |
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/* USB1_DATA7-USB1_DATA0, USB1_STOP, USB1_NEXT, USB1_CLK, USB1_DIR */ |
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{ |
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offsetof(struct ioctrl512x, io_control_pci_ad29), 12, 0, |
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IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1) |
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}, |
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/* FUNC1=VIU_DATA0 Sets Next 3 to VIU_DATA pads */ |
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/* VIU_DATA0-VIU_DATA2 */ |
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{ |
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offsetof(struct ioctrl512x, io_control_pci_ad17), 3, 0, |
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IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1) |
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}, |
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/* FUNC2=FEC_TXD_0 */ |
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{ |
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offsetof(struct ioctrl512x, io_control_pci_ad14), 1, 0, |
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IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1) |
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}, |
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/* FUNC1=VIU_DATA3 Sets Next 2 to VIU_DATA pads */ |
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/* VIU_DATA3, VIU_DATA4 */ |
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{ |
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offsetof(struct ioctrl512x, io_control_pci_ad13), 2, 0, |
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IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1) |
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}, |
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/* FUNC2=FEC_RXD_1 Sets Next 12 to FEC pads */ |
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/* FEC_RXD_1, FEC_RXD_0, FEC_RX_CLK, FEC_TX_CLK, FEC_RX_ER, FEC_RX_DV */ |
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/* FEC_TX_EN, FEC_TX_ER, FEC_CRS, FEC_MDC, FEC_MDIO, FEC_COL */ |
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{ |
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offsetof(struct ioctrl512x, io_control_pci_ad11), 12, 0, |
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IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1) |
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}, |
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/* FUNC2=DIU_LD03 Sets Next 25 to DIU pads */ |
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/* DIU_LD00-DIU_LD21 */ |
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{ |
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offsetof(struct ioctrl512x, io_control_pci_cbe0), 22, 0, |
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IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1) |
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}, |
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/* FUNC2=DIU_CLK Sets Next 3 to DIU pads */ |
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/* DIU_CLK, DIU_VSYNC, DIU_HSYNC */ |
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{ |
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offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0, |
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IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) |
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}, |
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/* FUNC2=CAN3_RX */ |
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{ |
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offsetof(struct ioctrl512x, io_control_irq1), 1, 0, |
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IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0) |
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}, |
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/* Sets lowest slew on 2 CAN_TX Pins*/ |
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{ |
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offsetof(struct ioctrl512x, io_control_can1_tx), 2, 0, |
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IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | |
||||
IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0) |
||||
}, |
||||
/* FUNC3=CAN4_TX Sets Next 2 to CAN4 pads */ |
||||
/* CAN4_TX, CAN4_RX */ |
||||
{ |
||||
offsetof(struct ioctrl512x, io_control_j1850_tx), 2, 0, |
||||
IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | |
||||
IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0) |
||||
}, |
||||
/* FUNC3=GPIO8 Sets Next 2 to GPIO pads */ |
||||
/* GPIO8, GPIO9 */ |
||||
{ |
||||
offsetof(struct ioctrl512x, io_control_psc0_0), 2, 0, |
||||
IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | |
||||
IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0) |
||||
}, |
||||
/* FUNC1=FEC_TXD_1 Sets Next 3 to FEC pads */ |
||||
/* FEC_TXD_1, FEC_TXD_2, FEC_TXD_3 */ |
||||
{ |
||||
offsetof(struct ioctrl512x, io_control_psc0_4), 3, 0, |
||||
IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | |
||||
IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) |
||||
}, |
||||
/* FUNC1=FEC_RXD_3 Sets Next 2 to FEC pads */ |
||||
/* FEC_RXD_3, FEC_RXD_2 */ |
||||
{ |
||||
offsetof(struct ioctrl512x, io_control_psc1_4), 2, 0, |
||||
IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | |
||||
IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) |
||||
}, |
||||
/* FUNC3=GPIO17 */ |
||||
{ |
||||
offsetof(struct ioctrl512x, io_control_psc2_1), 1, 0, |
||||
IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | |
||||
IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0) |
||||
}, |
||||
/* FUNC3=GPIO2/GPT2 Sets Next 3 to GPIO pads */ |
||||
/* GPIO2, GPIO20, GPIO21 */ |
||||
{ |
||||
offsetof(struct ioctrl512x, io_control_psc2_4), 3, 0, |
||||
IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | |
||||
IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0) |
||||
}, |
||||
/* FUNC2=VIU_PIX_CLK */ |
||||
{ |
||||
offsetof(struct ioctrl512x, io_control_psc3_4), 1, 0, |
||||
IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | |
||||
IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) |
||||
}, |
||||
/* FUNC3=GPIO24 Sets Next 2 to GPIO pads */ |
||||
/* GPIO24, GPIO25 */ |
||||
{ |
||||
offsetof(struct ioctrl512x, io_control_psc4_0), 2, 0, |
||||
IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | |
||||
IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0) |
||||
}, |
||||
/* FUNC1=NFC_CE2 */ |
||||
{ |
||||
offsetof(struct ioctrl512x, io_control_psc4_4), 1, 0, |
||||
IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(1) | |
||||
IO_PIN_PUE(1) | IO_PIN_ST(0) | IO_PIN_DS(0) |
||||
}, |
||||
/* FUNC2=VIU_DATA5 Sets Next 5 to VIU_DATA pads */ |
||||
/* VIU_DATA5-VIU_DATA9 */ |
||||
{ |
||||
offsetof(struct ioctrl512x, io_control_psc5_0), 5, 0, |
||||
IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | |
||||
IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) |
||||
}, |
||||
/* FUNC1=LPC_TSIZ1 Sets Next 2 to LPC_TSIZ pads */ |
||||
/* LPC_TSIZ1-LPC_TSIZ2 */ |
||||
{ |
||||
offsetof(struct ioctrl512x, io_control_psc6_0), 2, 0, |
||||
IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | |
||||
IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) |
||||
}, |
||||
/* FUNC1=LPC_TS */ |
||||
{ |
||||
offsetof(struct ioctrl512x, io_control_psc6_4), 1, 0, |
||||
IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | |
||||
IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) |
||||
}, |
||||
/* FUNC3=GPIO16 */ |
||||
{ |
||||
offsetof(struct ioctrl512x, io_control_psc7_0), 1, 0, |
||||
IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | |
||||
IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0) |
||||
}, |
||||
/* FUNC3=GPIO18 Sets Next 3 to GPIO pads */ |
||||
/* GPIO18-GPIO19, GPT7/GPIO7 */ |
||||
{ |
||||
offsetof(struct ioctrl512x, io_control_psc7_2), 3, 0, |
||||
IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | |
||||
IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0) |
||||
}, |
||||
/* FUNC3=GPIO0/GPT0 */ |
||||
{ |
||||
offsetof(struct ioctrl512x, io_control_psc8_4), 1, 0, |
||||
IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | |
||||
IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0) |
||||
}, |
||||
/* FUNC3=GPIO11 Sets Next 4 to GPIO pads */ |
||||
/* GPIO11, GPIO2, GPIO12, GPIO13 */ |
||||
{ |
||||
offsetof(struct ioctrl512x, io_control_psc10_3), 4, 0, |
||||
IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | |
||||
IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0) |
||||
}, |
||||
/* FUNC2=DIU_DE */ |
||||
{ |
||||
offsetof(struct ioctrl512x, io_control_psc11_4), 1, 0, |
||||
IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | |
||||
IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) |
||||
} |
||||
}; |
||||
|
||||
int checkboard (void) |
||||
{ |
||||
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; |
||||
|
||||
puts("Board: PDM360NG\n"); |
||||
|
||||
/* initialize function mux & slew rate IO inter alia on IO Pins */ |
||||
|
||||
iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init)); |
||||
|
||||
/* initialize IO_CONTROL_GP (GPIO/GPT-mux-register) */ |
||||
setbits_be32(&im->io_ctrl.io_control_gp, |
||||
(1 << 0) | /* GP_MUX7->GPIO7 */ |
||||
(1 << 5)); /* GP_MUX2->GPIO2 */ |
||||
|
||||
/* configure GPIO24 (VIU_CE), output/high */ |
||||
setbits_be32(&im->gpio.gpdir, 0x80); |
||||
setbits_be32(&im->gpio.gpdat, 0x80); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) |
||||
#ifdef CONFIG_FDT_FIXUP_PARTITIONS |
||||
struct node_info nodes[] = { |
||||
{ "fsl,mpc5121-nfc", MTD_DEV_TYPE_NAND, }, |
||||
{ "cfi-flash", MTD_DEV_TYPE_NOR, }, |
||||
}; |
||||
#endif |
||||
|
||||
void ft_board_setup(void *blob, bd_t *bd) |
||||
{ |
||||
u32 val[8]; |
||||
int rc, i = 0; |
||||
|
||||
ft_cpu_setup(blob, bd); |
||||
fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); |
||||
#ifdef CONFIG_FDT_FIXUP_PARTITIONS |
||||
fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); |
||||
#endif |
||||
|
||||
/* Fixup NOR FLASH mapping */ |
||||
val[i++] = 0; /* chip select number */ |
||||
val[i++] = 0; /* always 0 */ |
||||
val[i++] = gd->bd->bi_flashstart; |
||||
val[i++] = gd->bd->bi_flashsize; |
||||
|
||||
/* Fixup MRAM mapping */ |
||||
val[i++] = 2; /* chip select number */ |
||||
val[i++] = 0; /* always 0 */ |
||||
val[i++] = CONFIG_SYS_MRAM_BASE; |
||||
val[i++] = CONFIG_SYS_MRAM_SIZE; |
||||
|
||||
rc = fdt_find_and_setprop(blob, "/localbus", "ranges", |
||||
val, i * sizeof(u32), 1); |
||||
if (rc) |
||||
printf("Unable to update localbus ranges, err=%s\n", |
||||
fdt_strerror(rc)); |
||||
|
||||
/* Fixup reg property in NOR Flash node */ |
||||
i = 0; |
||||
val[i++] = 0; /* always 0 */ |
||||
val[i++] = 0; /* start at offset 0 */ |
||||
val[i++] = flash_info[0].size; /* size of Bank 0 */ |
||||
|
||||
/* Second Bank available? */ |
||||
if (flash_info[1].size > 0) { |
||||
val[i++] = 0; /* always 0 */ |
||||
val[i++] = flash_info[0].size; /* offset of Bank 1 */ |
||||
val[i++] = flash_info[1].size; /* size of Bank 1 */ |
||||
} |
||||
|
||||
rc = fdt_find_and_setprop(blob, "/localbus/flash", "reg", |
||||
val, i * sizeof(u32), 1); |
||||
if (rc) |
||||
printf("Unable to update flash reg property, err=%s\n", |
||||
fdt_strerror(rc)); |
||||
} |
||||
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ |
||||
|
||||
#if defined(CONFIG_SERIAL_MULTI) |
||||
/*
|
||||
* If argument is NULL, set the LCD brightness to the |
||||
* value from "brightness" environment variable. Set |
||||
* the LCD brightness to the value specified by the |
||||
* argument otherwise. Default brightness is zero. |
||||
*/ |
||||
#define MAX_BRIGHTNESS 99 |
||||
static int set_lcd_brightness(char *brightness) |
||||
{ |
||||
struct stdio_dev *cop_port; |
||||
char *env; |
||||
char cmd_buf[20]; |
||||
int val = 0; |
||||
int cs = 0; |
||||
int len, i; |
||||
|
||||
if (brightness) { |
||||
val = simple_strtol(brightness, NULL, 10); |
||||
} else { |
||||
env = getenv("brightness"); |
||||
if (env) |
||||
val = simple_strtol(env, NULL, 10); |
||||
} |
||||
|
||||
if (val < 0) |
||||
val = 0; |
||||
|
||||
if (val > MAX_BRIGHTNESS) |
||||
val = MAX_BRIGHTNESS; |
||||
|
||||
sprintf(cmd_buf, "$SB;%04d;", val); |
||||
|
||||
len = strlen(cmd_buf); |
||||
for (i = 1; i <= len; i++) |
||||
cs += cmd_buf[i]; |
||||
|
||||
cs = (~cs + 1) & 0xff; |
||||
sprintf(cmd_buf + len, "%02X\n", cs); |
||||
|
||||
/* IO Coprocessor communication */ |
||||
cop_port = open_port(4, CONFIG_SYS_PDM360NG_COPROC_BAUDRATE); |
||||
if (!cop_port) { |
||||
printf("Error: Can't open IO Coprocessor port.\n"); |
||||
return -1; |
||||
} |
||||
|
||||
debug("%s: cmd: %s", __func__, cmd_buf); |
||||
write_port(cop_port, cmd_buf); |
||||
/*
|
||||
* Wait for transmission and maybe response data |
||||
* before closing the port. |
||||
*/ |
||||
udelay(CONFIG_SYS_PDM360NG_COPROC_READ_DELAY); |
||||
memset(cmd_buf, 0, sizeof(cmd_buf)); |
||||
len = read_port(cop_port, cmd_buf, sizeof(cmd_buf)); |
||||
if (len) |
||||
printf("Error: %s\n", cmd_buf); |
||||
|
||||
close_port(4); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int cmd_lcd_brightness(cmd_tbl_t *cmdtp, int flag, |
||||
int argc, char *argv[]) |
||||
{ |
||||
if (argc < 2) { |
||||
cmd_usage(cmdtp); |
||||
return 1; |
||||
} |
||||
|
||||
return set_lcd_brightness(argv[1]); |
||||
} |
||||
|
||||
U_BOOT_CMD(lcdbr, 2, 1, cmd_lcd_brightness, |
||||
"set LCD brightness", |
||||
"<brightness> - set LCD backlight level to <brightness>.\n" |
||||
); |
||||
#endif /* CONFIG_SERIAL_MULTI */ |
@ -0,0 +1,53 @@ |
||||
/*
|
||||
* (C) Copyright 2010 DENX Software Engineering |
||||
* Anatolij Gustschin <agust@denx.de> |
||||
* |
||||
* Common configuration options for MPC5121 based boards |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __MPC5121_COMMON_H |
||||
#define __MPC5121_COMMON_H |
||||
|
||||
/* Use SRAM for initial stack */ |
||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE /* Init RAM base */ |
||||
#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_SRAM_SIZE /* End of area */ |
||||
|
||||
#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes of initial data */ |
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \ |
||||
CONFIG_SYS_GBL_DATA_SIZE) |
||||
#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 0x4) |
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_POST_WORD_ADDR |
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ |
||||
#define CONFIG_SYS_MEMTEST_END 0x00400000 |
||||
|
||||
/*
|
||||
* Serial console |
||||
*/ |
||||
#define CONFIG_BAUDRATE 115200 |
||||
#define CONFIG_SYS_BAUDRATE_TABLE \ |
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} |
||||
|
||||
#define CONFIG_CMDLINE_EDITING 1 /* command line history */ |
||||
/* Use the HUSH parser */ |
||||
#define CONFIG_SYS_HUSH_PARSER |
||||
#ifdef CONFIG_SYS_HUSH_PARSER |
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " |
||||
#endif |
||||
|
||||
#endif /* __MPC5121_COMMON_H */ |
@ -0,0 +1,481 @@ |
||||
/*
|
||||
* (C) Copyright 2009-2010 |
||||
* Michael Weiß, ifm ecomatic gmbh, michael.weiss@ifm.com |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* pdm360ng board configuration file |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
#define CONFIG_PDM360NG 1 |
||||
|
||||
/*
|
||||
* Memory map for the PDM360NG board: |
||||
* |
||||
* 0x0000_0000 - 0x1FFF_FFFF DDR RAM (512 MB) |
||||
* 0x2000_0000 - 0x3FFF_FFFF reserved (DDR RAM (512 MB) |
||||
* 0x5000_0000 - 0x5001_FFFF SRAM (128 KB) |
||||
* 0x5004_0000 - 0x5005_FFFF MRAM (CS2) (128 KB) |
||||
* 0x8000_0000 - 0x803F_FFFF IMMR (4 MB) |
||||
* 0xF000_0000 - 0xF7FF_FFFF NOR FLASH (CS0) (128 MB) |
||||
* 0xF800_0000 - 0xFFFF_FFFF NOR FLASH (CS1) (128 MB) optional |
||||
*/ |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
*/ |
||||
#define CONFIG_E300 1 /* E300 Family */ |
||||
#define CONFIG_MPC512X 1 /* MPC512X family */ |
||||
#define CONFIG_FSL_DIU_FB 1 /* FSL DIU */ |
||||
|
||||
/* Used for silent command in environment */ |
||||
#define CONFIG_SYS_DEVICE_NULLDEV |
||||
#define CONFIG_SILENT_CONSOLE |
||||
|
||||
/* Video */ |
||||
#define CONFIG_VIDEO |
||||
|
||||
#if defined(CONFIG_VIDEO) |
||||
#define CONFIG_CFB_CONSOLE |
||||
#define CONFIG_VGA_AS_SINGLE_DEVICE |
||||
#define CONFIG_SPLASH_SCREEN |
||||
#define CONFIG_VIDEO_LOGO |
||||
#define CONFIG_VIDEO_BMP_RLE8 |
||||
#define CONFIG_VIDEO_XRES 800 |
||||
#define CONFIG_VIDEO_YRES 480 |
||||
#endif |
||||
|
||||
#define CONFIG_SYS_MPC512X_CLKIN 33333333 /* in Hz */ |
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */ |
||||
#define CONFIG_MISC_INIT_R |
||||
|
||||
#define CONFIG_SYS_IMMR 0x80000000 |
||||
#define CONFIG_SYS_DIU_ADDR ((CONFIG_SYS_IMMR) + 0x2100) |
||||
|
||||
/*
|
||||
* DDR Setup |
||||
*/ |
||||
|
||||
/* DDR is system memory */ |
||||
#define CONFIG_SYS_DDR_BASE 0x00000000 |
||||
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE |
||||
#define CONFIG_SYS_MAX_RAM_SIZE 0x40000000 |
||||
|
||||
/* DDR pin mux and slew rate */ |
||||
#define CONFIG_SYS_IOCTRL_MUX_DDR 0x00000012 |
||||
|
||||
/* Manually set all parameters as there's no SPD etc. */ |
||||
/*
|
||||
* DDR Controller Configuration for Micron DDR2 SDRAM MT47H128M8-3 |
||||
* |
||||
* SYS_CFG: |
||||
* [31:31] MDDRC Soft Reset: Diabled |
||||
* [30:30] DRAM CKE pin: Enabled |
||||
* [29:29] DRAM CLK: Enabled |
||||
* [28:28] Command Mode: Enabled (For initialization only) |
||||
* [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10] |
||||
* [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10] |
||||
* [20:19] Read Test: DON'T USE |
||||
* [18:18] Self Refresh: Enabled |
||||
* [17:17] 16bit Mode: Disabled |
||||
* [16:13] Read Delay: 3 |
||||
* [12:12] Half DQS Delay: Disabled |
||||
* [11:11] Quarter DQS Delay: Disabled |
||||
* [10:08] Write Delay: 2 |
||||
* [07:07] Early ODT: Disabled |
||||
* [06:06] On DIE Termination: Enabled |
||||
* [05:05] FIFO Overflow Clear: DON'T USE here |
||||
* [04:04] FIFO Underflow Clear: DON'T USE here |
||||
* [03:03] FIFO Overflow Pending: DON'T USE here |
||||
* [02:02] FIFO Underlfow Pending: DON'T USE here |
||||
* [01:01] FIFO Overlfow Enabled: Enabled |
||||
* [00:00] FIFO Underflow Enabled: Enabled |
||||
* TIME_CFG0 |
||||
* [31:16] DRAM Refresh Time: 0 CSB clocks |
||||
* [15:8] DRAM Command Time: 0 CSB clocks |
||||
* [07:00] DRAM Precharge Time: 0 CSB clocks |
||||
* TIME_CFG1 |
||||
* [31:26] DRAM tRFC: |
||||
* [25:21] DRAM tWR1: |
||||
* [20:17] DRAM tWRT1: |
||||
* [16:11] DRAM tDRR: |
||||
* [10:05] DRAM tRC: |
||||
* [04:00] DRAM tRAS: |
||||
* TIME_CFG2 |
||||
* [31:28] DRAM tRCD: |
||||
* [27:23] DRAM tFAW: |
||||
* [22:19] DRAM tRTW1: |
||||
* [18:15] DRAM tCCD: |
||||
* [14:10] DRAM tRTP: |
||||
* [09:05] DRAM tRP: |
||||
* [04:00] DRAM tRPA |
||||
*/ |
||||
#define CONFIG_SYS_MDDRC_SYS_CFG 0xEA804A40 |
||||
#define CONFIG_SYS_MDDRC_TIME_CFG0 0x030C3D2E |
||||
#define CONFIG_SYS_MDDRC_TIME_CFG1 0x68EC1168 |
||||
#define CONFIG_SYS_MDDRC_TIME_CFG2 0x34310864 |
||||
|
||||
/*
|
||||
* Alternative 1: small RAM (128 MB) configuration |
||||
*/ |
||||
#define CONFIG_SYS_MDDRC_SYS_CFG_ALT1 0xE8604A40 |
||||
#define CONFIG_SYS_MDDRC_TIME_CFG0_ALT1 0x030C3D2E |
||||
#define CONFIG_SYS_MDDRC_TIME_CFG1_ALT1 0x3CEC1168 |
||||
#define CONFIG_SYS_MDDRC_TIME_CFG2_ALT1 0x33310863 |
||||
|
||||
#define CONFIG_SYS_MDDRC_SYS_CFG_EN 0xF0000000 |
||||
|
||||
#define CONFIG_SYS_DDRCMD_NOP 0x01380000 |
||||
#define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400 |
||||
#define CONFIG_SYS_DDRCMD_EM2 0x01020000 /* EMR2 */ |
||||
#define CONFIG_SYS_DDRCMD_EM3 0x01030000 /* EMR3 */ |
||||
/* EMR with 150 ohm ODT todo: verify */ |
||||
#define CONFIG_SYS_DDRCMD_EN_DLL 0x01010040 |
||||
#define CONFIG_SYS_DDRCMD_RES_DLL 0x01000100 |
||||
#define CONFIG_SYS_DDRCMD_RFSH 0x01080000 |
||||
#define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432 |
||||
/* EMR with 150 ohm ODT todo: verify */ |
||||
#define CONFIG_SYS_DDRCMD_OCD_DEFAULT 0x010107C0 |
||||
/* EMR new command with 150 ohm ODT todo: verify */ |
||||
#define CONFIG_SYS_DDRCMD_OCD_EXIT 0x01010440 |
||||
|
||||
/* DDR Priority Manager Configuration */ |
||||
#define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777 |
||||
#define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000 |
||||
#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001 |
||||
#define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC |
||||
#define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA |
||||
#define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666 |
||||
#define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555 |
||||
#define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444 |
||||
#define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444 |
||||
#define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555 |
||||
#define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558 |
||||
#define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111 |
||||
#define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122 |
||||
#define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa |
||||
#define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa |
||||
#define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666 |
||||
#define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666 |
||||
#define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111 |
||||
#define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111 |
||||
#define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111 |
||||
#define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111 |
||||
#define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111 |
||||
#define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111 |
||||
|
||||
/*
|
||||
* NOR FLASH on the Local Bus |
||||
*/ |
||||
#define CONFIG_SYS_FLASH_CFI /* use Common Flash Interface */ |
||||
#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ |
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
||||
|
||||
#define CONFIG_SYS_FLASH_BASE 0xF0000000 /* start of FLASH-Bank0 */ |
||||
#define CONFIG_SYS_FLASH_SIZE 0x08000000 /* max size of a Bank */ |
||||
/* start of FLASH-Bank1 */ |
||||
#define CONFIG_SYS_FLASH1_BASE (CONFIG_SYS_FLASH_BASE + \ |
||||
CONFIG_SYS_FLASH_SIZE) |
||||
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */ |
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ |
||||
#define CONFIG_SYS_FLASH_BANKS_LIST \ |
||||
{CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH1_BASE} |
||||
|
||||
#define CONFIG_SYS_SRAM_BASE 0x50000000 |
||||
#define CONFIG_SYS_SRAM_SIZE 0x00020000 /* 128 KB */ |
||||
|
||||
/* ALE active low, data size 4 bytes */ |
||||
#define CONFIG_SYS_CS0_CFG 0x05059350 |
||||
/* ALE active low, data size 4 bytes */ |
||||
#define CONFIG_SYS_CS1_CFG 0x05059350 |
||||
|
||||
#define CONFIG_SYS_MRAM_BASE 0x50040000 |
||||
#define CONFIG_SYS_MRAM_SIZE 0x00020000 |
||||
/* ALE active low, data size 4 bytes */ |
||||
#define CONFIG_SYS_CS2_CFG 0x05059110 |
||||
|
||||
/* alt. CS timing for CS0, CS1, CS2 */ |
||||
#define CONFIG_SYS_CS_ALETIMING 0x00000007 |
||||
|
||||
/*
|
||||
* NAND FLASH |
||||
*/ |
||||
#define CONFIG_CMD_NAND /* enable NAND support */ |
||||
#define CONFIG_NAND_MPC5121_NFC |
||||
#define CONFIG_SYS_NAND_BASE 0x40000000 |
||||
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1 |
||||
#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE |
||||
#define CONFIG_SYS_NAND_SELECT_DEVICE /* driver supports mutipl. chips */ |
||||
|
||||
/*
|
||||
* Configuration parameters for MPC5121 NAND driver |
||||
*/ |
||||
#define CONFIG_FSL_NFC_WIDTH 1 |
||||
#define CONFIG_FSL_NFC_WRITE_SIZE 2048 |
||||
#define CONFIG_FSL_NFC_SPARE_SIZE 64 |
||||
#define CONFIG_FSL_NFC_CHIPS CONFIG_SYS_MAX_NAND_DEVICE |
||||
|
||||
/*
|
||||
* Dynamic MTD partition support |
||||
*/ |
||||
#define CONFIG_CMD_MTDPARTS |
||||
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ |
||||
#define CONFIG_FLASH_CFI_MTD |
||||
#define MTDIDS_DEFAULT "nor0=f0000000.flash,nor1=f8000000.flash," \ |
||||
"nand0=MPC5121 NAND" |
||||
|
||||
/*
|
||||
* Flash layout |
||||
*/ |
||||
#define MTDPARTS_DEFAULT "mtdparts=f0000000.flash:512k(u-boot)," \ |
||||
"256k(environment1)," \
|
||||
"256k(environment2)," \
|
||||
"256k(splash-factory)," \
|
||||
"2m(FIT: recovery)," \
|
||||
"4608k(fs-recovery)," \
|
||||
"256k(splash-customer),"\
|
||||
"5m(FIT: kernel+dtb)," \
|
||||
"64m(rootfs squash)ro," \
|
||||
"51m(userfs ubi);" \
|
||||
"f8000000.flash:-(unused);" \
|
||||
"MPC5121 NAND:1024m(extended-userfs)" |
||||
|
||||
/*
|
||||
* Override partitions in device tree using info |
||||
* in "mtdparts" environment variable |
||||
*/ |
||||
#ifdef CONFIG_CMD_MTDPARTS |
||||
#define CONFIG_FDT_FIXUP_PARTITIONS |
||||
#endif |
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* Start of monitor */ |
||||
#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* 512 kB for monitor */ |
||||
#ifdef CONFIG_FSL_DIU_FB |
||||
#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* for malloc */ |
||||
#else |
||||
#define CONFIG_SYS_MALLOC_LEN (512 * 1024) |
||||
#endif |
||||
|
||||
/*
|
||||
* Serial Port |
||||
*/ |
||||
#define CONFIG_CONS_INDEX 1 |
||||
|
||||
/*
|
||||
* Serial console configuration |
||||
*/ |
||||
#define CONFIG_PSC_CONSOLE 6 /* console is on PSC6 */ |
||||
#if CONFIG_PSC_CONSOLE != 6 |
||||
#error CONFIG_PSC_CONSOLE must be 6 |
||||
#endif |
||||
|
||||
#define CONSOLE_FIFO_TX_SIZE FIFOC_PSC6_TX_SIZE |
||||
#define CONSOLE_FIFO_TX_ADDR FIFOC_PSC6_TX_ADDR |
||||
#define CONSOLE_FIFO_RX_SIZE FIFOC_PSC6_RX_SIZE |
||||
#define CONSOLE_FIFO_RX_ADDR FIFOC_PSC6_RX_ADDR |
||||
|
||||
/*
|
||||
* Used PSC UART devices |
||||
*/ |
||||
#define CONFIG_SERIAL_MULTI |
||||
#define CONFIG_SYS_PSC1 |
||||
#define CONFIG_SYS_PSC4 |
||||
#define CONFIG_SYS_PSC6 |
||||
|
||||
/*
|
||||
* Co-processor communication parameters |
||||
*/ |
||||
#define CONFIG_SYS_PDM360NG_COPROC_READ_DELAY 5000 |
||||
#define CONFIG_SYS_PDM360NG_COPROC_BAUDRATE 38400 |
||||
|
||||
/*
|
||||
* I2C |
||||
*/ |
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */ |
||||
#define CONFIG_I2C_MULTI_BUS |
||||
#define CONFIG_I2C_CMD_TREE |
||||
/* I2C speed and slave address */ |
||||
#define CONFIG_SYS_I2C_SPEED 100000 |
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F |
||||
|
||||
/*
|
||||
* EEPROM configuration |
||||
*/ |
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16-bit EEPROM addr */ |
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* ST AT24C01 */ |
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* 10ms of delay */ |
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16-Byte Write Mode */ |
||||
|
||||
/*
|
||||
* MAC addr in EEPROM |
||||
*/ |
||||
#define CONFIG_SYS_I2C_EEPROM_BUS_NUM 0 |
||||
#define CONFIG_SYS_I2C_EEPROM_MAC_OFFSET 0x10 |
||||
/*
|
||||
* Enabled only to delete "ethaddr" before testing |
||||
* "ethaddr" setting from EEPROM |
||||
*/ |
||||
#define CONFIG_ENV_OVERWRITE |
||||
|
||||
/*
|
||||
* Ethernet configuration |
||||
*/ |
||||
#define CONFIG_MPC512x_FEC 1 |
||||
#define CONFIG_NET_MULTI |
||||
#define CONFIG_PHY_ADDR 0x1F |
||||
#define CONFIG_MII 1 /* MII PHY management */ |
||||
#define CONFIG_FEC_AN_TIMEOUT 1 |
||||
#define CONFIG_HAS_ETH0 |
||||
|
||||
/*
|
||||
* Configure on-board RTC |
||||
*/ |
||||
#define CONFIG_RTC_M41T62 /* use M41T00 rtc via i2c */ |
||||
#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ |
||||
|
||||
/*
|
||||
* Environment |
||||
*/ |
||||
#define CONFIG_ENV_IS_IN_FLASH 1 |
||||
/* This has to be a multiple of the Flash sector size */ |
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ |
||||
CONFIG_SYS_MONITOR_LEN) |
||||
#define CONFIG_ENV_SIZE 0x2000 |
||||
#define CONFIG_ENV_SECT_SIZE 0x40000 /* one sector (256K) for env */ |
||||
|
||||
/* Address and size of Redundant Environment Sector */ |
||||
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) |
||||
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
||||
|
||||
#include <config_cmd_default.h> |
||||
|
||||
#define CONFIG_CMD_ASKENV |
||||
#define CONFIG_CMD_DATE |
||||
#define CONFIG_CMD_DHCP |
||||
#define CONFIG_CMD_EEPROM |
||||
#define CONFIG_CMD_I2C |
||||
#define CONFIG_CMD_MII |
||||
#define CONFIG_CMD_PING |
||||
#define CONFIG_CMD_REGINFO |
||||
|
||||
#ifdef CONFIG_VIDEO |
||||
#define CONFIG_CMD_BMP |
||||
#endif |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
||||
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
||||
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ |
||||
|
||||
#ifdef CONFIG_CMD_KGDB |
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
|
||||
/* Print Buffer Size */ |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) |
||||
/* Max number of command args */ |
||||
#define CONFIG_SYS_MAXARGS 16 |
||||
/* Boot Argument Buffer Size */ |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
||||
/* Decrementer freq: 1ms ticks */ |
||||
#define CONFIG_SYS_HZ 1000 |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
/* Initial Memory map for Linux */ |
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) |
||||
|
||||
/* Cache Configuration */ |
||||
#define CONFIG_SYS_DCACHE_SIZE 32768 |
||||
#define CONFIG_SYS_CACHELINE_SIZE 32 |
||||
#ifdef CONFIG_CMD_KGDB |
||||
/* log base 2 of the above value */ |
||||
#define CONFIG_SYS_CACHELINE_SHIFT 5 |
||||
#endif |
||||
|
||||
#define CONFIG_SYS_HID0_INIT 0x000000000 |
||||
#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | HID0_ICE) |
||||
#define CONFIG_SYS_HID2 HID2_HBE |
||||
|
||||
#define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#ifdef CONFIG_CMD_KGDB |
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ |
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
||||
#endif |
||||
|
||||
/*
|
||||
* Environment Configuration |
||||
*/ |
||||
#define CONFIG_TIMESTAMP |
||||
|
||||
#define CONFIG_HOSTNAME pdm360ng |
||||
/* default location for tftp and bootm */ |
||||
#define CONFIG_LOADADDR 400000 |
||||
|
||||
#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ |
||||
|
||||
#define CONFIG_PREBOOT "echo;" \ |
||||
"echo PDM360NG SAMPLE;" \
|
||||
"echo" |
||||
|
||||
#define CONFIG_BOOTCOMMAND "run env_cont" |
||||
|
||||
#define CONFIG_OF_LIBFDT 1 |
||||
#define CONFIG_OF_BOARD_SETUP 1 |
||||
#define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES 1 |
||||
#define CONFIG_FIT |
||||
#define CONFIG_FIT_VERBOSE |
||||
|
||||
#define OF_CPU "PowerPC,5121@0" |
||||
#define OF_SOC_COMPAT "fsl,mpc5121-immr" |
||||
#define OF_TBCLK (bd->bi_busfreq / 4) |
||||
#define OF_STDOUT_PATH "/soc@80000000/serial@11600" |
||||
|
||||
/*
|
||||
* Include common options for all mpc5121 boards |
||||
*/ |
||||
#include "mpc5121-common.h" |
||||
|
||||
#endif /* __CONFIG_H */ |
Loading…
Reference in new issue