The gdsys strider board is based on a Freescale MPC8308 SOC. It boots from NOR-Flash, kernel and rootfs are stored on SD-Card. On board peripherals include: - 1x 10/100 Mbit/s Ethernet (optional) - Lattice ECP3 FPGA connected via eLBC Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc> [trini: Drop setting CONFIG_SYS_GENERIC_BOARD, this is always true now] Signed-off-by: Tom Rini <trini@konsulko.com>master
Dirk Eibach
9 years ago
committed by
Tom Rini
parent
51b96fc67c
commit
a3f9d6c779
@ -0,0 +1,177 @@ |
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/*
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* (C) Copyright 2014 |
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* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <i2c.h> |
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#define ADV7611_I2C_ADDR 0x4c |
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#define ADV7611_RDINFO 0x2051 |
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/*
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* ADV7611 I2C Addresses in u-boot notation |
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*/ |
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enum { |
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CP_I2C_ADDR = 0x22, |
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DPLL_I2C_ADDR = 0x26, |
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KSV_I2C_ADDR = 0x32, |
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HDMI_I2C_ADDR = 0x34, |
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EDID_I2C_ADDR = 0x36, |
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INFOFRAME_I2C_ADDR = 0x3e, |
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CEC_I2C_ADDR = 0x40, |
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IO_I2C_ADDR = ADV7611_I2C_ADDR, |
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}; |
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/*
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* Global Control Registers |
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*/ |
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enum { |
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IO_RD_INFO_MSB = 0xea, |
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IO_RD_INFO_LSB = 0xeb, |
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IO_CEC_ADDR = 0xf4, |
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IO_INFOFRAME_ADDR = 0xf5, |
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IO_DPLL_ADDR = 0xf8, |
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IO_KSV_ADDR = 0xf9, |
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IO_EDID_ADDR = 0xfa, |
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IO_HDMI_ADDR = 0xfb, |
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IO_CP_ADDR = 0xfd, |
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}; |
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int adv7611_i2c[] = CONFIG_SYS_ADV7611_I2C; |
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int adv7611_probe(unsigned int screen) |
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{ |
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int old_bus = i2c_get_bus_num(); |
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unsigned int rd_info; |
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int res = 0; |
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i2c_set_bus_num(adv7611_i2c[screen]); |
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rd_info = (i2c_reg_read(IO_I2C_ADDR, IO_RD_INFO_MSB) << 8) |
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| i2c_reg_read(IO_I2C_ADDR, IO_RD_INFO_LSB); |
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if (rd_info != ADV7611_RDINFO) { |
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res = -1; |
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goto out; |
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} |
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/*
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* set I2C addresses to default values |
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*/ |
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i2c_reg_write(IO_I2C_ADDR, IO_CEC_ADDR, CEC_I2C_ADDR << 1); |
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i2c_reg_write(IO_I2C_ADDR, IO_INFOFRAME_ADDR, INFOFRAME_I2C_ADDR << 1); |
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i2c_reg_write(IO_I2C_ADDR, IO_DPLL_ADDR, DPLL_I2C_ADDR << 1); |
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i2c_reg_write(IO_I2C_ADDR, IO_KSV_ADDR, KSV_I2C_ADDR << 1); |
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i2c_reg_write(IO_I2C_ADDR, IO_EDID_ADDR, EDID_I2C_ADDR << 1); |
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i2c_reg_write(IO_I2C_ADDR, IO_HDMI_ADDR, HDMI_I2C_ADDR << 1); |
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i2c_reg_write(IO_I2C_ADDR, IO_CP_ADDR, CP_I2C_ADDR << 1); |
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/*
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* do magic initialization sequence from |
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* "ADV7611 Register Settings Recommendations Revision 1.5" |
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* with most registers undocumented |
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*/ |
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i2c_reg_write(CP_I2C_ADDR, 0x6c, 0x00); |
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i2c_reg_write(HDMI_I2C_ADDR, 0x9b, 0x03); |
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i2c_reg_write(HDMI_I2C_ADDR, 0x6f, 0x08); |
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i2c_reg_write(HDMI_I2C_ADDR, 0x85, 0x1f); |
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i2c_reg_write(HDMI_I2C_ADDR, 0x87, 0x70); |
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i2c_reg_write(HDMI_I2C_ADDR, 0x57, 0xda); |
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i2c_reg_write(HDMI_I2C_ADDR, 0x58, 0x01); |
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i2c_reg_write(HDMI_I2C_ADDR, 0x03, 0x98); |
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i2c_reg_write(HDMI_I2C_ADDR, 0x4c, 0x44); |
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/*
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* IO_REG_02, default 0xf0 |
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* |
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* INP_COLOR_SPACE (IO, Address 0x02[7:4]) |
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* default: 0b1111 auto |
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* set to : 0b0001 force RGB (range 0 to 255) input |
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* |
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* RGB_OUT (IO, Address 0x02[1]) |
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* default: 0 YPbPr color space output |
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* set to : 1 RGB color space output |
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*/ |
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i2c_reg_write(IO_I2C_ADDR, 0x02, 0x12); |
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/*
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* IO_REG_03, default 0x00 |
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* |
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* OP_FORMAT_SEL (IO, Address 0x03[7:0]) |
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* default: 0x00 8-bit SDR ITU-656 mode |
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* set to : 0x40 24-bit 4:4:4 SDR mode |
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*/ |
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i2c_reg_write(IO_I2C_ADDR, 0x03, 0x40); |
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/*
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* IO_REG_05, default 0x2c |
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* |
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* AVCODE_INSERT_EN (IO, Address 0x05[2]) |
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* default: 1 insert AV codes into data stream |
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* set to : 0 do not insert AV codes into data stream |
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*/ |
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i2c_reg_write(IO_I2C_ADDR, 0x05, 0x28); |
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/*
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* IO_REG_0C, default 0x62 |
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* |
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* POWER_DOWN (IO, Address 0x0C[5]) |
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* default: 1 chip is powered down |
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* set to : 0 chip is operational |
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*/ |
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i2c_reg_write(IO_I2C_ADDR, 0x0c, 0x42); |
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/*
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* IO_REG_15, default 0xbe |
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* |
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* TRI_SYNCS (IO, Address 0x15[3) |
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* TRI_LLC (IO, Address 0x15[2]) |
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* TRI_PIX (IO, Address 0x15[1]) |
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* default: 1 video output pins are tristate |
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* set to : 0 video output pins are active |
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*/ |
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i2c_reg_write(IO_I2C_ADDR, 0x15, 0xb0); |
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/*
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* HDMI_REGISTER_02H, default 0xff |
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* |
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* CLOCK_TERMA_DISABLE (HDMI, Address 0x83[0]) |
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* default: 1 disable termination |
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* set to : 0 enable termination |
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* Future options are: |
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* - use the chips automatic termination control |
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* - set this manually on cable detect |
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* but at the moment this seems a safe default. |
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*/ |
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i2c_reg_write(HDMI_I2C_ADDR, 0x83, 0xfe); |
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/*
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* HDMI_CP_CNTRL_1, default 0x01 |
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* |
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* HDMI_FRUN_EN (CP, Address 0xBA[0]) |
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* default: 1 Enable the free run feature in HDMI mode |
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* set to : 0 Disable the free run feature in HDMI mode |
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*/ |
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i2c_reg_write(CP_I2C_ADDR, 0xba, 0x00); |
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/*
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* INT1_CONFIGURATION, default 0x20 |
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* |
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* INTRQ_DUR_SEL[1:0] (IO, Address 0x40[7:6]) |
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* default: 00 Interrupt signal is active for 4 Xtal periods |
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* set to : 11 Active until cleared |
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* |
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* INTRQ_OP_SEL[1:0] (IO, Address 0x40[1:0]) |
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* default: 00 Open drain |
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* set to : 10 Drives high when active |
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*/ |
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i2c_reg_write(IO_I2C_ADDR, 0x40, 0xc2); |
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out: |
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i2c_set_bus_num(old_bus); |
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return res; |
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} |
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@ -0,0 +1,13 @@ |
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/*
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* (C) Copyright 2014 |
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* Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef _ADV7611_H_ |
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#define _ADV7611_H_ |
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int adv7611_probe(unsigned int screen); |
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#endif |
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@ -0,0 +1,64 @@ |
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/*
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* (C) Copyright 2014 |
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* Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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/* Chrontel CH7301C DVI Transmitter */ |
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#include <common.h> |
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#include <asm/io.h> |
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#include <errno.h> |
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#include <i2c.h> |
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#define CH7301_I2C_ADDR 0x75 |
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enum { |
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CH7301_CM = 0x1c, /* Clock Mode Register */ |
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CH7301_IC = 0x1d, /* Input Clock Register */ |
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CH7301_GPIO = 0x1e, /* GPIO Control Register */ |
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CH7301_IDF = 0x1f, /* Input Data Format Register */ |
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CH7301_CD = 0x20, /* Connection Detect Register */ |
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CH7301_DC = 0x21, /* DAC Control Register */ |
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CH7301_HPD = 0x23, /* Hot Plug Detection Register */ |
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CH7301_TCTL = 0x31, /* DVI Control Input Register */ |
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CH7301_TPCP = 0x33, /* DVI PLL Charge Pump Ctrl Register */ |
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CH7301_TPD = 0x34, /* DVI PLL Divide Register */ |
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CH7301_TPVT = 0x35, /* DVI PLL Supply Control Register */ |
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CH7301_TPF = 0x36, /* DVI PLL Filter Register */ |
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CH7301_TCT = 0x37, /* DVI Clock Test Register */ |
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CH7301_TSTP = 0x48, /* Test Pattern Register */ |
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CH7301_PM = 0x49, /* Power Management register */ |
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CH7301_VID = 0x4a, /* Version ID Register */ |
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CH7301_DID = 0x4b, /* Device ID Register */ |
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CH7301_DSP = 0x56, /* DVI Sync polarity Register */ |
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}; |
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int ch7301_i2c[] = CONFIG_SYS_CH7301_I2C; |
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int ch7301_probe(unsigned screen, bool power) |
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{ |
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u8 value; |
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i2c_set_bus_num(ch7301_i2c[screen]); |
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if (i2c_probe(CH7301_I2C_ADDR)) |
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return -1; |
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value = i2c_reg_read(CH7301_I2C_ADDR, CH7301_DID); |
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if (value != 0x17) |
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return -1; |
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if (power) { |
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i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPCP, 0x08); |
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i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPD, 0x16); |
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i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPF, 0x60); |
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i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x09); |
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i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0xc0); |
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} else { |
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i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x00); |
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i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0x01); |
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} |
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return 0; |
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} |
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@ -0,0 +1,13 @@ |
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/*
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* (C) Copyright 2014 |
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* Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef _CH7301_H_ |
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#define _CH7301_H_ |
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int ch7301_probe(unsigned screen, bool power); |
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#endif |
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@ -0,0 +1,227 @@ |
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/*
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* (C) Copyright 2014 |
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* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <gdsys_fpga.h> |
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enum { |
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UNITTYPE_MAIN_SERVER = 0, |
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UNITTYPE_MAIN_USER = 1, |
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UNITTYPE_VIDEO_SERVER = 2, |
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UNITTYPE_VIDEO_USER = 3, |
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}; |
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enum { |
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UNITTYPEPCB_DVI = 0, |
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UNITTYPEPCB_DP_165 = 1, |
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UNITTYPEPCB_DP_300 = 2, |
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UNITTYPEPCB_HDMI = 3, |
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}; |
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enum { |
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COMPRESSION_NONE = 0, |
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COMPRESSION_TYPE1_DELTA = 1, |
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COMPRESSION_TYPE1_TYPE2_DELTA = 3, |
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}; |
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enum { |
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AUDIO_NONE = 0, |
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AUDIO_TX = 1, |
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AUDIO_RX = 2, |
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AUDIO_RXTX = 3, |
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}; |
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enum { |
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SYSCLK_147456 = 0, |
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}; |
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enum { |
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RAM_DDR2_32 = 0, |
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RAM_DDR3_32 = 1, |
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}; |
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enum { |
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CARRIER_SPEED_1G = 0, |
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CARRIER_SPEED_2_5G = 1, |
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}; |
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bool ioep_fpga_has_osd(unsigned int fpga) |
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{ |
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u16 fpga_features; |
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unsigned feature_osd; |
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FPGA_GET_REG(0, fpga_features, &fpga_features); |
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feature_osd = fpga_features & (1<<11); |
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return feature_osd; |
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} |
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void ioep_fpga_print_info(unsigned int fpga) |
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{ |
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u16 versions; |
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u16 fpga_version; |
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u16 fpga_features; |
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unsigned unit_type; |
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unsigned unit_type_pcb_video; |
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unsigned feature_compression; |
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unsigned feature_osd; |
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unsigned feature_audio; |
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unsigned feature_sysclock; |
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unsigned feature_ramconfig; |
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unsigned feature_carrier_speed; |
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unsigned feature_carriers; |
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unsigned feature_video_channels; |
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FPGA_GET_REG(fpga, versions, &versions); |
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FPGA_GET_REG(fpga, fpga_version, &fpga_version); |
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FPGA_GET_REG(fpga, fpga_features, &fpga_features); |
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unit_type = (versions & 0xf000) >> 12; |
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unit_type_pcb_video = (versions & 0x01c0) >> 6; |
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feature_compression = (fpga_features & 0xe000) >> 13; |
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feature_osd = fpga_features & (1<<11); |
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feature_audio = (fpga_features & 0x0600) >> 9; |
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feature_sysclock = (fpga_features & 0x0180) >> 7; |
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feature_ramconfig = (fpga_features & 0x0060) >> 5; |
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feature_carrier_speed = fpga_features & (1<<4); |
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feature_carriers = (fpga_features & 0x000c) >> 2; |
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feature_video_channels = fpga_features & 0x0003; |
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switch (unit_type) { |
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case UNITTYPE_MAIN_SERVER: |
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case UNITTYPE_MAIN_USER: |
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printf("Mainchannel"); |
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break; |
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case UNITTYPE_VIDEO_SERVER: |
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case UNITTYPE_VIDEO_USER: |
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printf("Videochannel"); |
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break; |
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default: |
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printf("UnitType %d(not supported)", unit_type); |
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break; |
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} |
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switch (unit_type) { |
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case UNITTYPE_MAIN_SERVER: |
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case UNITTYPE_VIDEO_SERVER: |
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printf(" Server"); |
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if (versions & (1<<4)) |
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printf(" UC"); |
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break; |
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case UNITTYPE_MAIN_USER: |
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case UNITTYPE_VIDEO_USER: |
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printf(" User"); |
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break; |
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default: |
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break; |
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} |
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if (versions & (1<<5)) |
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printf(" Fiber"); |
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else |
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printf(" CAT"); |
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switch (unit_type_pcb_video) { |
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case UNITTYPEPCB_DVI: |
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printf(" DVI,"); |
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break; |
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case UNITTYPEPCB_DP_165: |
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printf(" DP 165MPix/s,"); |
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break; |
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case UNITTYPEPCB_DP_300: |
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printf(" DP 300MPix/s,"); |
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break; |
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case UNITTYPEPCB_HDMI: |
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printf(" HDMI,"); |
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break; |
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} |
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printf(" FPGA V %d.%02d\n features:", |
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fpga_version / 100, fpga_version % 100); |
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switch (feature_compression) { |
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case COMPRESSION_NONE: |
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printf(" no compression"); |
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break; |
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case COMPRESSION_TYPE1_DELTA: |
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printf(" type1-deltacompression"); |
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break; |
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case COMPRESSION_TYPE1_TYPE2_DELTA: |
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printf(" type1-deltacompression, type2-inlinecompression"); |
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break; |
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default: |
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printf(" compression %d(not supported)", feature_compression); |
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break; |
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} |
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printf(", %sosd", feature_osd ? "" : "no "); |
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switch (feature_audio) { |
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case AUDIO_NONE: |
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printf(", no audio"); |
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break; |
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case AUDIO_TX: |
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printf(", audio tx"); |
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break; |
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case AUDIO_RX: |
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printf(", audio rx"); |
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break; |
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case AUDIO_RXTX: |
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printf(", audio rx+tx"); |
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break; |
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default: |
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printf(", audio %d(not supported)", feature_audio); |
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break; |
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} |
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puts(",\n "); |
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switch (feature_sysclock) { |
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case SYSCLK_147456: |
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printf("clock 147.456 MHz"); |
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break; |
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default: |
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printf("clock %d(not supported)", feature_sysclock); |
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break; |
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} |
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switch (feature_ramconfig) { |
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case RAM_DDR2_32: |
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printf(", RAM 32 bit DDR2"); |
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break; |
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case RAM_DDR3_32: |
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printf(", RAM 32 bit DDR3"); |
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break; |
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default: |
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printf(", RAM %d(not supported)", feature_ramconfig); |
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break; |
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} |
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printf(", %d carrier(s) %s", feature_carriers, |
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feature_carrier_speed ? "2.5Gbit/s" : "1Gbit/s"); |
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printf(", %d video channel(s)\n", feature_video_channels); |
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} |
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@ -0,0 +1,14 @@ |
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/*
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* (C) Copyright 2014 |
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* Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef _IOEP_FPGA_H_ |
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#define _IOEP_FPGA_H_ |
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void ioep_fpga_print_info(unsigned int fpga); |
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bool ioep_fpga_has_osd(unsigned int fpga); |
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#endif |
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@ -0,0 +1,501 @@ |
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/*
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* (C) Copyright 2014 |
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* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de |
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* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <hwconfig.h> |
||||
#include <i2c.h> |
||||
#include <spi.h> |
||||
#include <libfdt.h> |
||||
#include <fdt_support.h> |
||||
#include <pci.h> |
||||
#include <mpc83xx.h> |
||||
#include <fsl_esdhc.h> |
||||
#include <asm/io.h> |
||||
#include <asm/fsl_serdes.h> |
||||
#include <asm/fsl_mpc83xx_serdes.h> |
||||
|
||||
#include "mpc8308.h" |
||||
|
||||
#include <gdsys_fpga.h> |
||||
|
||||
#include "../common/adv7611.h" |
||||
#include "../common/ch7301.h" |
||||
#include "../common/ioep-fpga.h" |
||||
#include "../common/mclink.h" |
||||
#include "../common/osd.h" |
||||
#include "../common/phy.h" |
||||
|
||||
#include <pca953x.h> |
||||
#include <pca9698.h> |
||||
|
||||
#include <miiphy.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
#define MAX_MUX_CHANNELS 2 |
||||
|
||||
enum { |
||||
MCFPGA_DONE = 1 << 0, |
||||
MCFPGA_INIT_N = 1 << 1, |
||||
MCFPGA_PROGRAM_N = 1 << 2, |
||||
MCFPGA_UPDATE_ENABLE_N = 1 << 3, |
||||
MCFPGA_RESET_N = 1 << 4, |
||||
}; |
||||
|
||||
enum { |
||||
GPIO_MDC = 1 << 14, |
||||
GPIO_MDIO = 1 << 15, |
||||
}; |
||||
|
||||
enum { |
||||
FAN_CONFIG = 0x03, |
||||
FAN_TACHLIM_LSB = 0x48, |
||||
FAN_TACHLIM_MSB = 0x49, |
||||
FAN_PWM_FREQ = 0x4D, |
||||
}; |
||||
|
||||
unsigned int mclink_fpgacount; |
||||
struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR; |
||||
|
||||
struct { |
||||
u8 bus; |
||||
u8 addr; |
||||
} strider_fans[] = CONFIG_STRIDER_FANS; |
||||
|
||||
int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data) |
||||
{ |
||||
int res; |
||||
|
||||
switch (fpga) { |
||||
case 0: |
||||
out_le16(reg, data); |
||||
break; |
||||
default: |
||||
res = mclink_send(fpga - 1, regoff, data); |
||||
if (res < 0) { |
||||
printf("mclink_send reg %02lx data %04x returned %d\n", |
||||
regoff, data, res); |
||||
return res; |
||||
} |
||||
break; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data) |
||||
{ |
||||
int res; |
||||
|
||||
switch (fpga) { |
||||
case 0: |
||||
*data = in_le16(reg); |
||||
break; |
||||
default: |
||||
if (fpga > mclink_fpgacount) |
||||
return -EINVAL; |
||||
res = mclink_receive(fpga - 1, regoff, data); |
||||
if (res < 0) { |
||||
printf("mclink_receive reg %02lx returned %d\n", |
||||
regoff, res); |
||||
return res; |
||||
} |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int checkboard(void) |
||||
{ |
||||
char *s = getenv("serial#"); |
||||
bool hw_type_cat = pca9698_get_value(0x20, 18); |
||||
|
||||
puts("Board: "); |
||||
|
||||
printf("Strider %s", hw_type_cat ? "CAT" : "Fiber"); |
||||
|
||||
if (s != NULL) { |
||||
puts(", serial# "); |
||||
puts(s); |
||||
} |
||||
|
||||
puts("\n"); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static void init_fan_controller(u8 addr) |
||||
{ |
||||
int val; |
||||
|
||||
/* set PWM Frequency to 2.5% resolution */ |
||||
i2c_reg_write(addr, FAN_PWM_FREQ, 20); |
||||
|
||||
/* set Tachometer Limit */ |
||||
i2c_reg_write(addr, FAN_TACHLIM_LSB, 0x10); |
||||
i2c_reg_write(addr, FAN_TACHLIM_MSB, 0x0a); |
||||
|
||||
/* enable Tach input */ |
||||
val = i2c_reg_read(addr, FAN_CONFIG) | 0x04; |
||||
i2c_reg_write(addr, FAN_CONFIG, val); |
||||
} |
||||
|
||||
int last_stage_init(void) |
||||
{ |
||||
int slaves; |
||||
unsigned int k; |
||||
unsigned int mux_ch; |
||||
unsigned char mclink_controllers[] = { 0x3c, 0x3d, 0x3e }; |
||||
bool hw_type_cat = pca9698_get_value(0x20, 18); |
||||
bool ch0_sgmii2_present = false; |
||||
|
||||
/* Turn on Analog Devices ADV7611 */ |
||||
pca9698_direction_output(0x20, 8, 0); |
||||
|
||||
/* Turn on Parade DP501 */ |
||||
pca9698_direction_output(0x20, 9, 1); |
||||
|
||||
ch0_sgmii2_present = !pca9698_get_value(0x20, 37); |
||||
|
||||
/* wait for FPGA done, then reset FPGA */ |
||||
for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) { |
||||
unsigned int ctr = 0; |
||||
|
||||
if (i2c_probe(mclink_controllers[k])) |
||||
continue; |
||||
|
||||
while (!(pca953x_get_val(mclink_controllers[k]) |
||||
& MCFPGA_DONE)) { |
||||
udelay(100000); |
||||
if (ctr++ > 5) { |
||||
printf("no done for mclink_controller %d\n", k); |
||||
break; |
||||
} |
||||
} |
||||
|
||||
pca953x_set_dir(mclink_controllers[k], MCFPGA_RESET_N, 0); |
||||
pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, 0); |
||||
udelay(10); |
||||
pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, |
||||
MCFPGA_RESET_N); |
||||
} |
||||
|
||||
if (hw_type_cat) { |
||||
miiphy_register(bb_miiphy_buses[0].name, bb_miiphy_read, |
||||
bb_miiphy_write); |
||||
for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) { |
||||
if ((mux_ch == 1) && !ch0_sgmii2_present) |
||||
continue; |
||||
|
||||
setup_88e1514(bb_miiphy_buses[0].name, mux_ch); |
||||
} |
||||
} |
||||
|
||||
/* give slave-PLLs and Parade DP501 some time to be up and running */ |
||||
udelay(500000); |
||||
|
||||
mclink_fpgacount = CONFIG_SYS_MCLINK_MAX; |
||||
slaves = mclink_probe(); |
||||
mclink_fpgacount = 0; |
||||
|
||||
ioep_fpga_print_info(0); |
||||
|
||||
if (!adv7611_probe(0)) |
||||
printf(" Advantiv ADV7611 HDMI Receiver\n"); |
||||
|
||||
#ifdef CONFIG_STRIDER_CON |
||||
if (ioep_fpga_has_osd(0)) |
||||
osd_probe(0); |
||||
#endif |
||||
|
||||
#ifdef CONFIG_STRIDER_CPU |
||||
ch7301_probe(0, false); |
||||
#endif |
||||
|
||||
if (slaves <= 0) |
||||
return 0; |
||||
|
||||
mclink_fpgacount = slaves; |
||||
|
||||
for (k = 1; k <= slaves; ++k) { |
||||
ioep_fpga_print_info(k); |
||||
#ifdef CONFIG_STRIDER_CON |
||||
if (ioep_fpga_has_osd(k)) |
||||
osd_probe(k); |
||||
#endif |
||||
#ifdef CONFIG_STRIDER_CPU |
||||
FPGA_SET_REG(k, extended_control, 0); /* enable video in*/ |
||||
if (!adv7611_probe(k)) |
||||
printf(" Advantiv ADV7611 HDMI Receiver\n"); |
||||
ch7301_probe(k, false); |
||||
#endif |
||||
if (hw_type_cat) { |
||||
miiphy_register(bb_miiphy_buses[k].name, |
||||
bb_miiphy_read, bb_miiphy_write); |
||||
setup_88e1514(bb_miiphy_buses[k].name, 0); |
||||
} |
||||
} |
||||
|
||||
for (k = 0; k < ARRAY_SIZE(strider_fans); ++k) { |
||||
i2c_set_bus_num(strider_fans[k].bus); |
||||
init_fan_controller(strider_fans[k].addr); |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/*
|
||||
* provide access to fpga gpios (for I2C bitbang) |
||||
* (these may look all too simple but make iocon.h much more readable) |
||||
*/ |
||||
void fpga_gpio_set(unsigned int bus, int pin) |
||||
{ |
||||
FPGA_SET_REG(bus, gpio.set, pin); |
||||
} |
||||
|
||||
void fpga_gpio_clear(unsigned int bus, int pin) |
||||
{ |
||||
FPGA_SET_REG(bus, gpio.clear, pin); |
||||
} |
||||
|
||||
int fpga_gpio_get(unsigned int bus, int pin) |
||||
{ |
||||
u16 val; |
||||
|
||||
FPGA_GET_REG(bus, gpio.read, &val); |
||||
|
||||
return val & pin; |
||||
} |
||||
|
||||
void mpc8308_init(void) |
||||
{ |
||||
pca9698_direction_output(0x20, 26, 1); |
||||
} |
||||
|
||||
void mpc8308_set_fpga_reset(unsigned state) |
||||
{ |
||||
pca9698_set_value(0x20, 26, state ? 0 : 1); |
||||
} |
||||
|
||||
void mpc8308_setup_hw(void) |
||||
{ |
||||
immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; |
||||
|
||||
/*
|
||||
* set "startup-finished"-gpios |
||||
*/ |
||||
setbits_be32(&immr->gpio[0].dir, (1 << (31-11)) | (1 << (31-12))); |
||||
setbits_be32(&immr->gpio[0].dat, 1 << (31-12)); |
||||
} |
||||
|
||||
int mpc8308_get_fpga_done(unsigned fpga) |
||||
{ |
||||
return pca9698_get_value(0x20, 20); |
||||
} |
||||
|
||||
#ifdef CONFIG_FSL_ESDHC |
||||
int board_mmc_init(bd_t *bd) |
||||
{ |
||||
immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; |
||||
sysconf83xx_t *sysconf = &immr->sysconf; |
||||
|
||||
/* Enable cache snooping in eSDHC system configuration register */ |
||||
out_be32(&sysconf->sdhccr, 0x02000000); |
||||
|
||||
return fsl_esdhc_mmc_init(bd); |
||||
} |
||||
#endif |
||||
|
||||
static struct pci_region pcie_regions_0[] = { |
||||
{ |
||||
.bus_start = CONFIG_SYS_PCIE1_MEM_BASE, |
||||
.phys_start = CONFIG_SYS_PCIE1_MEM_PHYS, |
||||
.size = CONFIG_SYS_PCIE1_MEM_SIZE, |
||||
.flags = PCI_REGION_MEM, |
||||
}, |
||||
{ |
||||
.bus_start = CONFIG_SYS_PCIE1_IO_BASE, |
||||
.phys_start = CONFIG_SYS_PCIE1_IO_PHYS, |
||||
.size = CONFIG_SYS_PCIE1_IO_SIZE, |
||||
.flags = PCI_REGION_IO, |
||||
}, |
||||
}; |
||||
|
||||
void pci_init_board(void) |
||||
{ |
||||
immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; |
||||
sysconf83xx_t *sysconf = &immr->sysconf; |
||||
law83xx_t *pcie_law = sysconf->pcielaw; |
||||
struct pci_region *pcie_reg[] = { pcie_regions_0 }; |
||||
|
||||
fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX, |
||||
FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); |
||||
|
||||
/* Deassert the resets in the control register */ |
||||
out_be32(&sysconf->pecr1, 0xE0008000); |
||||
udelay(2000); |
||||
|
||||
/* Configure PCI Express Local Access Windows */ |
||||
out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR); |
||||
out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB); |
||||
|
||||
mpc83xx_pcie_init(1, pcie_reg); |
||||
} |
||||
|
||||
ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) |
||||
{ |
||||
info->portwidth = FLASH_CFI_16BIT; |
||||
info->chipwidth = FLASH_CFI_BY16; |
||||
info->interface = FLASH_CFI_X16; |
||||
return 1; |
||||
} |
||||
|
||||
#if defined(CONFIG_OF_BOARD_SETUP) |
||||
int ft_board_setup(void *blob, bd_t *bd) |
||||
{ |
||||
ft_cpu_setup(blob, bd); |
||||
fdt_fixup_dr_usb(blob, bd); |
||||
fdt_fixup_esdhc(blob, bd); |
||||
|
||||
return 0; |
||||
} |
||||
#endif |
||||
|
||||
/*
|
||||
* FPGA MII bitbang implementation |
||||
*/ |
||||
|
||||
struct fpga_mii { |
||||
unsigned fpga; |
||||
int mdio; |
||||
} fpga_mii[] = { |
||||
{ 0, 1}, |
||||
{ 1, 1}, |
||||
{ 2, 1}, |
||||
{ 3, 1}, |
||||
}; |
||||
|
||||
static int mii_dummy_init(struct bb_miiphy_bus *bus) |
||||
{ |
||||
return 0; |
||||
} |
||||
|
||||
static int mii_mdio_active(struct bb_miiphy_bus *bus) |
||||
{ |
||||
struct fpga_mii *fpga_mii = bus->priv; |
||||
|
||||
if (fpga_mii->mdio) |
||||
FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); |
||||
else |
||||
FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int mii_mdio_tristate(struct bb_miiphy_bus *bus) |
||||
{ |
||||
struct fpga_mii *fpga_mii = bus->priv; |
||||
|
||||
FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int mii_set_mdio(struct bb_miiphy_bus *bus, int v) |
||||
{ |
||||
struct fpga_mii *fpga_mii = bus->priv; |
||||
|
||||
if (v) |
||||
FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); |
||||
else |
||||
FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO); |
||||
|
||||
fpga_mii->mdio = v; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int mii_get_mdio(struct bb_miiphy_bus *bus, int *v) |
||||
{ |
||||
u16 gpio; |
||||
struct fpga_mii *fpga_mii = bus->priv; |
||||
|
||||
FPGA_GET_REG(fpga_mii->fpga, gpio.read, &gpio); |
||||
|
||||
*v = ((gpio & GPIO_MDIO) != 0); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int mii_set_mdc(struct bb_miiphy_bus *bus, int v) |
||||
{ |
||||
struct fpga_mii *fpga_mii = bus->priv; |
||||
|
||||
if (v) |
||||
FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDC); |
||||
else |
||||
FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDC); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int mii_delay(struct bb_miiphy_bus *bus) |
||||
{ |
||||
udelay(1); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
struct bb_miiphy_bus bb_miiphy_buses[] = { |
||||
{ |
||||
.name = "board0", |
||||
.init = mii_dummy_init, |
||||
.mdio_active = mii_mdio_active, |
||||
.mdio_tristate = mii_mdio_tristate, |
||||
.set_mdio = mii_set_mdio, |
||||
.get_mdio = mii_get_mdio, |
||||
.set_mdc = mii_set_mdc, |
||||
.delay = mii_delay, |
||||
.priv = &fpga_mii[0], |
||||
}, |
||||
{ |
||||
.name = "board1", |
||||
.init = mii_dummy_init, |
||||
.mdio_active = mii_mdio_active, |
||||
.mdio_tristate = mii_mdio_tristate, |
||||
.set_mdio = mii_set_mdio, |
||||
.get_mdio = mii_get_mdio, |
||||
.set_mdc = mii_set_mdc, |
||||
.delay = mii_delay, |
||||
.priv = &fpga_mii[1], |
||||
}, |
||||
{ |
||||
.name = "board2", |
||||
.init = mii_dummy_init, |
||||
.mdio_active = mii_mdio_active, |
||||
.mdio_tristate = mii_mdio_tristate, |
||||
.set_mdio = mii_set_mdio, |
||||
.get_mdio = mii_get_mdio, |
||||
.set_mdc = mii_set_mdc, |
||||
.delay = mii_delay, |
||||
.priv = &fpga_mii[2], |
||||
}, |
||||
{ |
||||
.name = "board3", |
||||
.init = mii_dummy_init, |
||||
.mdio_active = mii_mdio_active, |
||||
.mdio_tristate = mii_mdio_tristate, |
||||
.set_mdio = mii_set_mdio, |
||||
.get_mdio = mii_get_mdio, |
||||
.set_mdc = mii_set_mdc, |
||||
.delay = mii_delay, |
||||
.priv = &fpga_mii[3], |
||||
}, |
||||
}; |
||||
|
||||
int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) / |
||||
sizeof(bb_miiphy_buses[0]); |
||||
@ -0,0 +1,7 @@ |
||||
CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CON" |
||||
CONFIG_PPC=y |
||||
CONFIG_MPC83xx=y |
||||
CONFIG_TARGET_STRIDER=y |
||||
CONFIG_AUTOBOOT_KEYED=y |
||||
CONFIG_AUTOBOOT_STOP_STR=" " |
||||
# CONFIG_CMD_SETEXPR is not set |
||||
@ -0,0 +1,7 @@ |
||||
CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CPU" |
||||
CONFIG_PPC=y |
||||
CONFIG_MPC83xx=y |
||||
CONFIG_TARGET_STRIDER=y |
||||
CONFIG_AUTOBOOT_KEYED=y |
||||
CONFIG_AUTOBOOT_STOP_STR=" " |
||||
# CONFIG_CMD_SETEXPR is not set |
||||
@ -0,0 +1,651 @@ |
||||
/*
|
||||
* (C) Copyright 2014 |
||||
* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de |
||||
* |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
*/ |
||||
#define CONFIG_E300 1 /* E300 family */ |
||||
#define CONFIG_MPC83xx 1 /* MPC83xx family */ |
||||
#define CONFIG_MPC830x 1 /* MPC830x family */ |
||||
#define CONFIG_MPC8308 1 /* MPC8308 CPU specific */ |
||||
#define CONFIG_STRIDER 1 /* STRIDER board specific */ |
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0xFE000000 |
||||
|
||||
#ifdef CONFIG_STRIDER_CPU |
||||
#define CONFIG_IDENT_STRING " strider cpu 0.01" |
||||
#else |
||||
#define CONFIG_IDENT_STRING " strider con 0.01" |
||||
#endif |
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F |
||||
#define CONFIG_BOARD_EARLY_INIT_R |
||||
#define CONFIG_LAST_STAGE_INIT |
||||
|
||||
/* new uImage format support */ |
||||
#define CONFIG_FIT 1 |
||||
#define CONFIG_FIT_VERBOSE 1 |
||||
|
||||
#define CONFIG_MMC |
||||
#define CONFIG_FSL_ESDHC |
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR |
||||
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
||||
|
||||
#define CONFIG_CMD_MMC |
||||
#define CONFIG_GENERIC_MMC |
||||
#define CONFIG_DOS_PARTITION |
||||
#define CONFIG_CMD_EXT2 |
||||
|
||||
#define CONFIG_CMD_MEMTEST |
||||
#define CONFIG_SYS_ALT_MEMTEST |
||||
|
||||
#define CONFIG_CMD_FPGAD |
||||
#define CONFIG_CMD_IOLOOP |
||||
|
||||
/*
|
||||
* System Clock Setup |
||||
*/ |
||||
#define CONFIG_83XX_CLKIN 33333333 /* in Hz */ |
||||
#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN |
||||
|
||||
/*
|
||||
* Hardware Reset Configuration Word |
||||
* if CLKIN is 66.66MHz, then |
||||
* CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz |
||||
* We choose the A type silicon as default, so the core is 400Mhz. |
||||
*/ |
||||
#define CONFIG_SYS_HRCW_LOW (\ |
||||
HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
|
||||
HRCWL_DDR_TO_SCB_CLK_2X1 |\
|
||||
HRCWL_SVCOD_DIV_2 |\
|
||||
HRCWL_CSB_TO_CLKIN_4X1 |\
|
||||
HRCWL_CORE_TO_CSB_3X1) |
||||
/*
|
||||
* There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits |
||||
* in 8308's HRCWH according to the manual, but original Freescale's |
||||
* code has them and I've expirienced some problems using the board |
||||
* with BDI3000 attached when I've tried to set these bits to zero |
||||
* (UART doesn't work after the 'reset run' command). |
||||
*/ |
||||
#define CONFIG_SYS_HRCW_HIGH (\ |
||||
HRCWH_PCI_HOST |\
|
||||
HRCWH_PCI1_ARBITER_ENABLE |\
|
||||
HRCWH_CORE_ENABLE |\
|
||||
HRCWH_FROM_0XFFF00100 |\
|
||||
HRCWH_BOOTSEQ_DISABLE |\
|
||||
HRCWH_SW_WATCHDOG_DISABLE |\
|
||||
HRCWH_ROM_LOC_LOCAL_16BIT |\
|
||||
HRCWH_RL_EXT_LEGACY |\
|
||||
HRCWH_TSEC1M_IN_MII |\
|
||||
HRCWH_TSEC2M_IN_RGMII |\
|
||||
HRCWH_BIG_ENDIAN) |
||||
|
||||
/*
|
||||
* System IO Config |
||||
*/ |
||||
#define CONFIG_SYS_SICRH (\ |
||||
SICRH_ESDHC_A_SD |\
|
||||
SICRH_ESDHC_B_SD |\
|
||||
SICRH_ESDHC_C_SD |\
|
||||
SICRH_GPIO_A_GPIO |\
|
||||
SICRH_GPIO_B_GPIO |\
|
||||
SICRH_IEEE1588_A_GPIO |\
|
||||
SICRH_USB |\
|
||||
SICRH_GTM_GPIO |\
|
||||
SICRH_IEEE1588_B_GPIO |\
|
||||
SICRH_ETSEC2_GPIO |\
|
||||
SICRH_GPIOSEL_1 |\
|
||||
SICRH_TMROBI_V3P3 |\
|
||||
SICRH_TSOBI1_V2P5 |\
|
||||
SICRH_TSOBI2_V2P5) /* 0x0037f103 */ |
||||
#define CONFIG_SYS_SICRL (\ |
||||
SICRL_SPI_PF0 |\
|
||||
SICRL_UART_PF0 |\
|
||||
SICRL_IRQ_PF0 |\
|
||||
SICRL_I2C2_PF0 |\
|
||||
SICRL_ETSEC1_TX_CLK) /* 0x00000000 */ |
||||
|
||||
/*
|
||||
* IMMR new address |
||||
*/ |
||||
#define CONFIG_SYS_IMMR 0xE0000000 |
||||
|
||||
/*
|
||||
* SERDES |
||||
*/ |
||||
#define CONFIG_FSL_SERDES |
||||
#define CONFIG_FSL_SERDES1 0xe3000 |
||||
|
||||
/*
|
||||
* Arbiter Setup |
||||
*/ |
||||
#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ |
||||
#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ |
||||
#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ |
||||
|
||||
/*
|
||||
* DDR Setup |
||||
*/ |
||||
#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ |
||||
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE |
||||
#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE |
||||
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 |
||||
#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ |
||||
| DDRCDR_PZ_LOZ \
|
||||
| DDRCDR_NZ_LOZ \
|
||||
| DDRCDR_ODT \
|
||||
| DDRCDR_Q_DRN) |
||||
/* 0x7b880001 */ |
||||
/*
|
||||
* Manually set up DDR parameters |
||||
* consist of one chip NT5TU64M16HG from NANYA |
||||
*/ |
||||
|
||||
#define CONFIG_SYS_DDR_SIZE 128 /* MB */ |
||||
|
||||
#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 |
||||
#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ |
||||
| CSCONFIG_ODT_RD_NEVER \
|
||||
| CSCONFIG_ODT_WR_ONLY_CURRENT \
|
||||
| CSCONFIG_BANK_BIT_3 \
|
||||
| CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) |
||||
/* 0x80010102 */ |
||||
#define CONFIG_SYS_DDR_TIMING_3 0 |
||||
#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ |
||||
| (0 << TIMING_CFG0_WRT_SHIFT) \
|
||||
| (0 << TIMING_CFG0_RRT_SHIFT) \
|
||||
| (0 << TIMING_CFG0_WWT_SHIFT) \
|
||||
| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
|
||||
| (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
|
||||
| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
|
||||
| (2 << TIMING_CFG0_MRS_CYC_SHIFT)) |
||||
/* 0x00260802 */ |
||||
#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ |
||||
| (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
|
||||
| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
|
||||
| (7 << TIMING_CFG1_CASLAT_SHIFT) \
|
||||
| (9 << TIMING_CFG1_REFREC_SHIFT) \
|
||||
| (2 << TIMING_CFG1_WRREC_SHIFT) \
|
||||
| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
|
||||
| (2 << TIMING_CFG1_WRTORD_SHIFT)) |
||||
/* 0x26279222 */ |
||||
#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ |
||||
| (4 << TIMING_CFG2_CPO_SHIFT) \
|
||||
| (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
|
||||
| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
|
||||
| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
|
||||
| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
|
||||
| (5 << TIMING_CFG2_FOUR_ACT_SHIFT)) |
||||
/* 0x021848c5 */ |
||||
#define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \ |
||||
| (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) |
||||
/* 0x08240100 */ |
||||
#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ |
||||
| SDRAM_CFG_SDRAM_TYPE_DDR2 \
|
||||
| SDRAM_CFG_DBW_16) |
||||
/* 0x43100000 */ |
||||
|
||||
#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ |
||||
#define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \ |
||||
| (0x0242 << SDRAM_MODE_SD_SHIFT)) |
||||
/* ODT 150ohm CL=4, AL=0 on SDRAM */ |
||||
#define CONFIG_SYS_DDR_MODE2 0x00000000 |
||||
|
||||
/*
|
||||
* Memory test |
||||
*/ |
||||
#define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */ |
||||
#define CONFIG_SYS_MEMTEST_END 0x07f00000 |
||||
|
||||
/*
|
||||
* The reserved memory |
||||
*/ |
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ |
||||
#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ |
||||
|
||||
/*
|
||||
* Initial RAM Base Address Setup |
||||
*/ |
||||
#define CONFIG_SYS_INIT_RAM_LOCK 1 |
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ |
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ |
||||
#define CONFIG_SYS_GBL_DATA_OFFSET \ |
||||
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
||||
|
||||
/*
|
||||
* Local Bus Configuration & Clock Setup |
||||
*/ |
||||
#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP |
||||
#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 |
||||
#define CONFIG_SYS_LBC_LBCR 0x00040000 |
||||
|
||||
/*
|
||||
* FLASH on the Local Bus |
||||
*/ |
||||
#if 1 |
||||
#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ |
||||
#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ |
||||
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT |
||||
#define CONFIG_FLASH_CFI_LEGACY |
||||
#define CONFIG_SYS_FLASH_LEGACY_512Kx16 |
||||
#else |
||||
#define CONFIG_SYS_NO_FLASH |
||||
#endif |
||||
|
||||
#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ |
||||
#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */ |
||||
#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ |
||||
|
||||
/* Window base at flash base */ |
||||
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE |
||||
#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) |
||||
|
||||
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ |
||||
| BR_PS_16 /* 16 bit port */ \
|
||||
| BR_MS_GPCM /* MSEL = GPCM */ \
|
||||
| BR_V) /* valid */ |
||||
#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ |
||||
| OR_UPM_XAM \
|
||||
| OR_GPCM_CSNT \
|
||||
| OR_GPCM_ACS_DIV2 \
|
||||
| OR_GPCM_XACS \
|
||||
| OR_GPCM_SCY_15 \
|
||||
| OR_GPCM_TRLX_SET \
|
||||
| OR_GPCM_EHTR_SET) |
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
||||
#define CONFIG_SYS_MAX_FLASH_SECT 135 |
||||
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ |
||||
|
||||
/*
|
||||
* FPGA |
||||
*/ |
||||
#define CONFIG_SYS_FPGA0_BASE 0xE0600000 |
||||
#define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */ |
||||
|
||||
/* Window base at FPGA base */ |
||||
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA0_BASE |
||||
#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_1MB) |
||||
|
||||
#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FPGA0_BASE \ |
||||
| BR_PS_16 /* 16 bit port */ \
|
||||
| BR_MS_GPCM /* MSEL = GPCM */ \
|
||||
| BR_V) /* valid */ |
||||
#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \ |
||||
| OR_UPM_XAM \
|
||||
| OR_GPCM_CSNT \
|
||||
| OR_GPCM_ACS_DIV2 \
|
||||
| OR_GPCM_XACS \
|
||||
| OR_GPCM_SCY_15 \
|
||||
| OR_GPCM_TRLX_SET \
|
||||
| OR_GPCM_EHTR_SET) |
||||
|
||||
#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE |
||||
#define CONFIG_SYS_FPGA_DONE(k) 0x0010 |
||||
|
||||
#define CONFIG_SYS_FPGA_COUNT 1 |
||||
|
||||
#define CONFIG_SYS_MCLINK_MAX 3 |
||||
|
||||
#define CONFIG_SYS_FPGA_PTR \ |
||||
{ (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL } |
||||
|
||||
#define CONFIG_SYS_FPGA_NO_RFL_HI |
||||
|
||||
/*
|
||||
* Serial Port |
||||
*/ |
||||
#define CONFIG_CONS_INDEX 2 |
||||
#define CONFIG_SYS_NS16550 |
||||
#define CONFIG_SYS_NS16550_SERIAL |
||||
#define CONFIG_SYS_NS16550_REG_SIZE 1 |
||||
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) |
||||
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE \ |
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} |
||||
|
||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) |
||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) |
||||
|
||||
/* Use the HUSH parser */ |
||||
#define CONFIG_SYS_HUSH_PARSER |
||||
|
||||
/* Pass open firmware flat tree */ |
||||
#define CONFIG_OF_LIBFDT 1 |
||||
#define CONFIG_OF_BOARD_SETUP 1 |
||||
#define CONFIG_OF_STDOUT_VIA_ALIAS 1 |
||||
|
||||
/* I2C */ |
||||
#define CONFIG_SYS_I2C |
||||
#define CONFIG_SYS_I2C_FSL |
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000 |
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F |
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 |
||||
|
||||
#define CONFIG_PCA953X /* NXP PCA9554 */ |
||||
#define CONFIG_PCA9698 /* NXP PCA9698 */ |
||||
|
||||
#define CONFIG_SYS_I2C_IHS |
||||
#define CONFIG_SYS_I2C_IHS_CH0 |
||||
#define CONFIG_SYS_I2C_IHS_SPEED_0 50000 |
||||
#define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F |
||||
#define CONFIG_SYS_I2C_IHS_CH1 |
||||
#define CONFIG_SYS_I2C_IHS_SPEED_1 50000 |
||||
#define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F |
||||
#define CONFIG_SYS_I2C_IHS_CH2 |
||||
#define CONFIG_SYS_I2C_IHS_SPEED_2 50000 |
||||
#define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F |
||||
#define CONFIG_SYS_I2C_IHS_CH3 |
||||
#define CONFIG_SYS_I2C_IHS_SPEED_3 50000 |
||||
#define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F |
||||
|
||||
/*
|
||||
* Software (bit-bang) I2C driver configuration |
||||
*/ |
||||
#define CONFIG_SYS_I2C_SOFT |
||||
#define CONFIG_SOFT_I2C_READ_REPEATED_START |
||||
#define CONFIG_SYS_I2C_SOFT_SPEED 50000 |
||||
#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F |
||||
#define I2C_SOFT_DECLARATIONS2 |
||||
#define CONFIG_SYS_I2C_SOFT_SPEED_2 50000 |
||||
#define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F |
||||
#define I2C_SOFT_DECLARATIONS3 |
||||
#define CONFIG_SYS_I2C_SOFT_SPEED_3 50000 |
||||
#define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F |
||||
#define I2C_SOFT_DECLARATIONS4 |
||||
#define CONFIG_SYS_I2C_SOFT_SPEED_4 50000 |
||||
#define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F |
||||
#ifdef CONFIG_STRIDER_CON |
||||
#define I2C_SOFT_DECLARATIONS5 |
||||
#define CONFIG_SYS_I2C_SOFT_SPEED_5 50000 |
||||
#define CONFIG_SYS_I2C_SOFT_SLAVE_5 0x7F |
||||
#define I2C_SOFT_DECLARATIONS6 |
||||
#define CONFIG_SYS_I2C_SOFT_SPEED_6 50000 |
||||
#define CONFIG_SYS_I2C_SOFT_SLAVE_6 0x7F |
||||
#define I2C_SOFT_DECLARATIONS7 |
||||
#define CONFIG_SYS_I2C_SOFT_SPEED_7 50000 |
||||
#define CONFIG_SYS_I2C_SOFT_SLAVE_7 0x7F |
||||
#define I2C_SOFT_DECLARATIONS8 |
||||
#define CONFIG_SYS_I2C_SOFT_SPEED_8 50000 |
||||
#define CONFIG_SYS_I2C_SOFT_SLAVE_8 0x7F |
||||
#endif |
||||
|
||||
#ifdef CONFIG_STRIDER_CON |
||||
#define CONFIG_SYS_ICS8N3QV01_I2C {5, 6, 7, 8} |
||||
#define CONFIG_SYS_CH7301_I2C {5, 6, 7, 8} |
||||
#define CONFIG_SYS_ADV7611_I2C {5, 6, 7, 8} |
||||
#define CONFIG_SYS_DP501_I2C {1, 2, 3, 4} |
||||
#define CONFIG_STRIDER_FANS { {10, 0x4c}, {11, 0x4c}, \ |
||||
{12, 0x4c} } |
||||
#else |
||||
#define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4} |
||||
#define CONFIG_SYS_ADV7611_I2C {1, 2, 3, 4} |
||||
#define CONFIG_SYS_DP501_I2C {1, 2, 3, 4} |
||||
#define CONFIG_STRIDER_FANS { {2, 0x18}, {3, 0x18}, \ |
||||
{4, 0x18} } |
||||
#endif |
||||
|
||||
#ifndef __ASSEMBLY__ |
||||
void fpga_gpio_set(unsigned int bus, int pin); |
||||
void fpga_gpio_clear(unsigned int bus, int pin); |
||||
int fpga_gpio_get(unsigned int bus, int pin); |
||||
#endif |
||||
|
||||
#ifdef CONFIG_STRIDER_CON |
||||
#define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0200 : 0x0040) |
||||
#define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0100 : 0x0020) |
||||
#define I2C_FPGA_IDX ((I2C_ADAP_HWNR > 3) ? \ |
||||
(I2C_ADAP_HWNR - 4) : I2C_ADAP_HWNR) |
||||
#else |
||||
#define I2C_SDA_GPIO 0x0040 |
||||
#define I2C_SCL_GPIO 0x0020 |
||||
#define I2C_FPGA_IDX I2C_ADAP_HWNR |
||||
#endif |
||||
#define I2C_ACTIVE { } |
||||
#define I2C_TRISTATE { } |
||||
#define I2C_READ \ |
||||
(fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0) |
||||
#define I2C_SDA(bit) \ |
||||
do { \
|
||||
if (bit) \
|
||||
fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \
|
||||
else \
|
||||
fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \
|
||||
} while (0) |
||||
#define I2C_SCL(bit) \ |
||||
do { \
|
||||
if (bit) \
|
||||
fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \
|
||||
else \
|
||||
fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \
|
||||
} while (0) |
||||
#define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */ |
||||
|
||||
/*
|
||||
* Software (bit-bang) MII driver configuration |
||||
*/ |
||||
#define CONFIG_BITBANGMII /* bit-bang MII PHY management */ |
||||
#define CONFIG_BITBANGMII_MULTI |
||||
|
||||
/*
|
||||
* OSD Setup |
||||
*/ |
||||
#define CONFIG_SYS_OSD_SCREENS 1 |
||||
#define CONFIG_SYS_DP501_DIFFERENTIAL |
||||
#define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */ |
||||
|
||||
/*
|
||||
* General PCI |
||||
* Addresses are mapped 1-1. |
||||
*/ |
||||
#define CONFIG_SYS_PCIE1_BASE 0xA0000000 |
||||
#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 |
||||
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 |
||||
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 |
||||
#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 |
||||
#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 |
||||
#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 |
||||
#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 |
||||
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 |
||||
|
||||
/* enable PCIE clock */ |
||||
#define CONFIG_SYS_SCCR_PCIEXP1CM 1 |
||||
|
||||
#define CONFIG_PCI |
||||
#define CONFIG_PCI_INDIRECT_BRIDGE |
||||
#define CONFIG_PCIE |
||||
|
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */ |
||||
|
||||
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ |
||||
#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1 |
||||
|
||||
/*
|
||||
* TSEC |
||||
*/ |
||||
#define CONFIG_TSEC_ENET /* TSEC ethernet support */ |
||||
#define CONFIG_SYS_TSEC1_OFFSET 0x24000 |
||||
#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) |
||||
|
||||
/*
|
||||
* TSEC ethernet configuration |
||||
*/ |
||||
#define CONFIG_MII 1 /* MII PHY management */ |
||||
#define CONFIG_TSEC1 |
||||
#define CONFIG_TSEC1_NAME "eTSEC0" |
||||
#define TSEC1_PHY_ADDR 1 |
||||
#define TSEC1_PHYIDX 0 |
||||
#define TSEC1_FLAGS 0 |
||||
|
||||
/* Options are: eTSEC[0-1] */ |
||||
#define CONFIG_ETHPRIME "eTSEC0" |
||||
|
||||
/*
|
||||
* Environment |
||||
*/ |
||||
#if 1 |
||||
#define CONFIG_ENV_IS_IN_FLASH 1 |
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ |
||||
CONFIG_SYS_MONITOR_LEN) |
||||
#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ |
||||
#define CONFIG_ENV_SIZE 0x2000 |
||||
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) |
||||
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE |
||||
#else |
||||
#define CONFIG_ENV_IS_NOWHERE |
||||
#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ |
||||
#endif |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
||||
|
||||
/*
|
||||
* Command line configuration. |
||||
*/ |
||||
#define CONFIG_CMD_I2C |
||||
#define CONFIG_CMD_MII |
||||
#define CONFIG_CMD_PCI |
||||
#define CONFIG_CMD_PING |
||||
|
||||
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
||||
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
||||
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
||||
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ |
||||
|
||||
#undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */ |
||||
|
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
|
||||
#define CONFIG_SYS_CONSOLE_INFO_QUIET |
||||
|
||||
/* Print Buffer Size */ |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) |
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 256 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
/*
|
||||
* Core HID Setup |
||||
*/ |
||||
#define CONFIG_SYS_HID0_INIT 0x000000000 |
||||
#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ |
||||
HID0_ENABLE_INSTRUCTION_CACHE | \
|
||||
HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) |
||||
#define CONFIG_SYS_HID2 HID2_HBE |
||||
|
||||
/*
|
||||
* MMU Setup |
||||
*/ |
||||
|
||||
/* DDR: cache cacheable */ |
||||
#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ |
||||
BATL_MEMCOHERENCE) |
||||
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \ |
||||
BATU_VS | BATU_VP) |
||||
#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L |
||||
#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U |
||||
|
||||
/* IMMRBAR, PCI IO and FPGA: cache-inhibit and guarded */ |
||||
#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ |
||||
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
||||
#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \ |
||||
BATU_VP) |
||||
#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L |
||||
#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U |
||||
|
||||
/* FLASH: icache cacheable, but dcache-inhibit and guarded */ |
||||
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ |
||||
BATL_MEMCOHERENCE) |
||||
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \ |
||||
BATU_VS | BATU_VP) |
||||
#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ |
||||
BATL_CACHEINHIBIT | \
|
||||
BATL_GUARDEDSTORAGE) |
||||
#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U |
||||
|
||||
/* Stack in dcache: cacheable, no memory coherence */ |
||||
#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) |
||||
#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ |
||||
BATU_VS | BATU_VP) |
||||
#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L |
||||
#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U |
||||
|
||||
/*
|
||||
* Environment Configuration |
||||
*/ |
||||
|
||||
#define CONFIG_ENV_OVERWRITE |
||||
|
||||
#if defined(CONFIG_TSEC_ENET) |
||||
#define CONFIG_HAS_ETH0 |
||||
#endif |
||||
|
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ |
||||
|
||||
#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ |
||||
|
||||
#define CONFIG_HOSTNAME hrcon |
||||
#define CONFIG_ROOTPATH "/opt/nfsroot" |
||||
#define CONFIG_BOOTFILE "uImage" |
||||
|
||||
#define CONFIG_PREBOOT /* enable preboot variable */ |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"netdev=eth0\0" \
|
||||
"consoledev=ttyS1\0" \
|
||||
"u-boot=u-boot.bin\0" \
|
||||
"kernel_addr=1000000\0" \
|
||||
"fdt_addr=C00000\0" \
|
||||
"fdtfile=hrcon.dtb\0" \
|
||||
"load=tftp ${loadaddr} ${u-boot}\0" \
|
||||
"update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
|
||||
" +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
|
||||
" +${filesize};cp.b ${fileaddr} " \
|
||||
__stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
|
||||
"upd=run load update\0" \
|
||||
|
||||
#define CONFIG_NFSBOOTCOMMAND \ |
||||
"setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=$serverip:$rootpath " \
|
||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp ${kernel_addr} $bootfile;" \
|
||||
"tftp ${fdt_addr} $fdtfile;" \
|
||||
"bootm ${kernel_addr} - ${fdt_addr}" |
||||
|
||||
#define CONFIG_MMCBOOTCOMMAND \ |
||||
"setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"ext2load mmc 0:2 ${kernel_addr} $bootfile;" \
|
||||
"ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \
|
||||
"bootm ${kernel_addr} - ${fdt_addr}" |
||||
|
||||
#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND |
||||
|
||||
|
||||
#endif /* __CONFIG_H */ |
||||
Loading…
Reference in new issue