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@ -44,7 +44,7 @@ static void exynos_dp_enable_video_input(unsigned int enable) |
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reg = readl(&dp_regs->video_ctl1); |
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reg &= ~VIDEO_EN_MASK; |
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/* enable video input*/ |
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/* enable video input */ |
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if (enable) |
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reg |= VIDEO_EN_MASK; |
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@ -55,13 +55,13 @@ static void exynos_dp_enable_video_input(unsigned int enable) |
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void exynos_dp_enable_video_bist(unsigned int enable) |
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{ |
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/*enable video bist*/ |
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/* enable video bist */ |
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unsigned int reg; |
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reg = readl(&dp_regs->video_ctl4); |
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reg &= ~VIDEO_BIST_MASK; |
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/*enable video bist*/ |
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/* enable video bist */ |
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if (enable) |
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reg |= VIDEO_BIST_MASK; |
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@ -112,7 +112,7 @@ static void exynos_dp_init_analog_param(void) |
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/*
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* Set AUX TX terminal resistor to 102 ohm |
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* Set AUX channel amplitude control |
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*/ |
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*/ |
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reg = PD_RING_OSC | AUX_TERMINAL_CTRL_52_OHM | TX_CUR1_2X | TX_CUR_4_MA; |
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writel(reg, &dp_regs->pll_filter_ctl1); |
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@ -146,7 +146,7 @@ static void exynos_dp_init_interrupt(void) |
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*/ |
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writel(INT_POL, &dp_regs->int_ctl); |
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/* Clear pending regisers */ |
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/* Clear pending registers */ |
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writel(0xff, &dp_regs->common_int_sta1); |
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writel(0xff, &dp_regs->common_int_sta2); |
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writel(0xff, &dp_regs->common_int_sta3); |
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@ -165,7 +165,7 @@ void exynos_dp_reset(void) |
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{ |
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unsigned int reg_func_1; |
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/*dp tx sw reset*/ |
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/* dp tx sw reset */ |
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writel(RESET_DP_TX, &dp_regs->tx_sw_reset); |
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exynos_dp_enable_video_input(DP_DISABLE); |
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@ -287,7 +287,7 @@ int exynos_dp_init_analog_func(void) |
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unsigned int retry_cnt = 10; |
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unsigned int reg; |
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/*Power On All Analog block */ |
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/* Power On All Analog block */ |
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exynos_dp_set_analog_power_down(POWER_ALL, DP_DISABLE); |
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reg = PLL_LOCK_CHG; |
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@ -297,14 +297,14 @@ int exynos_dp_init_analog_func(void) |
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reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL); |
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writel(reg, &dp_regs->debug_ctl); |
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/*Assert DP PLL Reset*/ |
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/* Assert DP PLL Reset */ |
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reg = readl(&dp_regs->pll_ctl); |
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reg |= DP_PLL_RESET; |
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writel(reg, &dp_regs->pll_ctl); |
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mdelay(1); |
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/*Deassert DP PLL Reset*/ |
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/* Deassert DP PLL Reset */ |
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reg = readl(&dp_regs->pll_ctl); |
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reg &= ~(DP_PLL_RESET); |
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writel(reg, &dp_regs->pll_ctl); |
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@ -336,7 +336,7 @@ void exynos_dp_init_hpd(void) |
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{ |
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unsigned int reg; |
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/* Clear interrupts releated to Hot Plug Dectect */ |
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/* Clear interrupts related to Hot Plug Detect */ |
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reg = HOTPLUG_CHG | HPD_LOST | PLUG; |
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writel(reg, &dp_regs->common_int_sta4); |
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@ -366,7 +366,7 @@ void exynos_dp_init_aux(void) |
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{ |
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unsigned int reg; |
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/* Clear inerrupts related to AUX channel */ |
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/* Clear interrupts related to AUX channel */ |
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reg = RPLY_RECEIV | AUX_ERR; |
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writel(reg, &dp_regs->int_sta); |
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@ -377,7 +377,7 @@ void exynos_dp_init_aux(void) |
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AUX_HW_RETRY_INTERVAL_600_MICROSECONDS; |
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writel(reg, &dp_regs->aux_hw_retry_ctl); |
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/* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */ |
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/* Receive AUX Channel DEFER commands equal to DEFER_COUNT*64 */ |
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reg = DEFER_CTRL_EN | DEFER_COUNT(1); |
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writel(reg, &dp_regs->aux_ch_defer_ctl); |
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@ -1040,7 +1040,7 @@ void exynos_dp_config_video_slave_mode(struct edp_video_info *video_info) |
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reg |= (video_info->h_sync_polarity << H_S_POLARITY_CFG_SHIFT); |
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writel(reg, &dp_regs->video_ctl10); |
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/*Set video mode to slave mode */ |
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/* Set video mode to slave mode */ |
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reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE; |
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writel(reg, &dp_regs->soc_general_ctl); |
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} |
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