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@ -16,16 +16,16 @@ struct ventana_board_info { |
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u8 mfgdate[4]; /* 0x20: MFG date (read only) */ |
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u8 res2[7]; /* 0x24 */ |
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/* sdram config */ |
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u8 sdram_size; /* 0x2B: enum (512,1024,2048) MB */ |
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u8 sdram_speed; /* 0x2C: enum (100,133,166,200,267,333,400) MHz */ |
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u8 sdram_width; /* 0x2D: enum (32,64) bit */ |
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u8 sdram_size; /* 0x2B: (16 << n) MB */ |
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u8 sdram_speed; /* 0x2C: (33.333 * n) MHz */ |
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u8 sdram_width; /* 0x2D: (8 << n) bit */ |
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/* cpu config */ |
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u8 cpu_speed; /* 0x2E: enum (800,1000,1200) MHz */ |
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u8 cpu_type; /* 0x2F: enum (imx6q,imx6d,imx6dl,imx6s) */ |
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u8 cpu_speed; /* 0x2E: (33.333 * n) MHz */ |
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u8 cpu_type; /* 0x2F: 7=imx6q, 8=imx6dl */ |
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u8 model[16]; /* 0x30: model string */ |
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/* FLASH config */ |
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u8 nand_flash_size; /* 0x40: enum (4,8,16,32,64,128) MB */ |
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u8 spi_flash_size; /* 0x41: enum (4,8,16,32,64,128) MB */ |
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u8 nand_flash_size; /* 0x40: (8 << (n-1)) MB */ |
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u8 spi_flash_size; /* 0x41: (4 << (n-1)) MB */ |
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/* Config1: SoC Peripherals */ |
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u8 config[8]; /* 0x42: loading options */ |
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