Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>master
parent
f28e1bd9da
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a605aacd83
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(BOARD).a
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COBJS = $(BOARD).o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) |
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$(AR) $(ARFLAGS) $@ $(OBJS)
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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@ -0,0 +1,25 @@ |
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#
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# (C) Copyright 2000-2003
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
|
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
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#
|
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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TEXT_BASE = 0xffe00000
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/*
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* (C) Copyright 2004 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <command.h> |
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#include <malloc.h> |
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#include <asm/immap.h> |
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/* Prototypes */ |
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int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); |
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int checkboard (void) { |
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ulong val; |
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uchar val8; |
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puts ("Board: "); |
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puts("Freescale M5249EVB"); |
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val8 = ((uchar)~((uchar)mbar2_readLong(MCFSIM_GPIO1_READ) >> 4)) & 0xf; |
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printf(" (Switch=%1X)\n", val8); |
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/*
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* Set LED on |
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*/ |
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val = mbar2_readLong(MCFSIM_GPIO1_OUT) & ~CFG_GPIO1_LED; |
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mbar2_writeLong(MCFSIM_GPIO1_OUT, val); /* Set LED on */ |
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return 0; |
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}; |
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long int initdram (int board_type) { |
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unsigned long junk = 0xa5a59696; |
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/*
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* Note: |
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* RC = ([(RefreshTime/#rows) / (1/BusClk)] / 16) - 1 |
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*/ |
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#ifdef CFG_FAST_CLK |
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/*
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* Busclk=70MHz, RefreshTime=64ms, #rows=4096 (4K) |
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* SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=39 |
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*/ |
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mbar_writeShort(MCFSIM_DCR, 0x8239); |
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#elif CFG_PLL_BYPASS |
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/*
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* Busclk=5.6448MHz, RefreshTime=64ms, #rows=8192 (8K) |
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* SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=02 |
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*/ |
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mbar_writeShort(MCFSIM_DCR, 0x8202); |
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#else |
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/*
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* Busclk=36MHz, RefreshTime=64ms, #rows=4096 (4K) |
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* SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=22 (562 bus clock cycles) |
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*/ |
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mbar_writeShort(MCFSIM_DCR, 0x8222); |
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#endif |
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/*
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* SDRAM starts at 0x0000_0000, CASL=10, CBM=010, PS=10 (16bit port), |
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* PM=1 (continuous page mode) |
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*/ |
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/* RE=0 (keep auto-refresh disabled while setting up registers) */ |
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mbar_writeLong(MCFSIM_DACR0, 0x00003324); |
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/* BAM=007c (bits 22,21 are bank selects; 256kB blocks) */ |
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mbar_writeLong(MCFSIM_DMR0, 0x01fc0001); |
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/** Precharge sequence **/ |
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mbar_writeLong(MCFSIM_DACR0, 0x0000332c); /* Set DACR0[IP] (bit 3) */ |
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*((volatile unsigned long *) 0x00) = junk; /* write to a memory location to init. precharge */ |
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udelay(0x10); /* Allow several Precharge cycles */ |
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/** Refresh Sequence **/ |
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mbar_writeLong(MCFSIM_DACR0, 0x0000b324); /* Enable the refresh bit, DACR0[RE] (bit 15) */ |
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udelay(0x7d0); /* Allow gobs of refresh cycles */ |
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/** Mode Register initialization **/ |
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mbar_writeLong(MCFSIM_DACR0, 0x0000b364); /* Enable DACR0[IMRS] (bit 6); RE remains enabled */ |
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*((volatile unsigned long *) 0x800) = junk; /* Access RAM to initialize the mode register */ |
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return CFG_SDRAM_SIZE * 1024 * 1024; |
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}; |
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int testdram (void) { |
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/* TODO: XXX XXX XXX */ |
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printf ("DRAM test not implemented!\n"); |
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return (0); |
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} |
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@ -0,0 +1,146 @@ |
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/* |
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* (C) Copyright 2000 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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OUTPUT_ARCH(m68k) |
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SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); |
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/* Do we need any of these for elf? |
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__DYNAMIC = 0; */ |
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SECTIONS |
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{ |
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/* Read-only sections, merged into text segment: */ |
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. = + SIZEOF_HEADERS; |
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.interp : { *(.interp) } |
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.hash : { *(.hash) } |
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.dynsym : { *(.dynsym) } |
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.dynstr : { *(.dynstr) } |
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.rel.text : { *(.rel.text) } |
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.rela.text : { *(.rela.text) } |
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.rel.data : { *(.rel.data) } |
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.rela.data : { *(.rela.data) } |
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.rel.rodata : { *(.rel.rodata) } |
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.rela.rodata : { *(.rela.rodata) } |
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.rel.got : { *(.rel.got) } |
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.rela.got : { *(.rela.got) } |
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.rel.ctors : { *(.rel.ctors) } |
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.rela.ctors : { *(.rela.ctors) } |
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.rel.dtors : { *(.rel.dtors) } |
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.rela.dtors : { *(.rela.dtors) } |
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.rel.bss : { *(.rel.bss) } |
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.rela.bss : { *(.rela.bss) } |
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.rel.plt : { *(.rel.plt) } |
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.rela.plt : { *(.rela.plt) } |
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.init : { *(.init) } |
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.plt : { *(.plt) } |
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.text : |
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{ |
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/* WARNING - the following is hand-optimized to fit within */ |
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/* the sector layout of our flash chips! XXX FIXME XXX */ |
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cpu/mcf52x2/start.o (.text) |
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lib_m68k/traps.o (.text) |
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cpu/mcf52x2/interrupts.o (.text) |
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common/dlmalloc.o (.text) |
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lib_generic/zlib.o (.text) |
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. = DEFINED(env_offset) ? env_offset : .; |
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common/environment.o (.text) |
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*(.text) |
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*(.fixup) |
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*(.got1) |
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} |
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_etext = .; |
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PROVIDE (etext = .); |
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.rodata : |
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{ |
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*(.rodata) |
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*(.rodata1) |
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*(.rodata.str1.4) |
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*(.eh_frame) |
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} |
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.fini : { *(.fini) } =0 |
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.ctors : { *(.ctors) } |
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.dtors : { *(.dtors) } |
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/* Read-write section, merged into data segment: */ |
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. = (. + 0x00FF) & 0xFFFFFF00; |
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_erotext = .; |
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PROVIDE (erotext = .); |
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.reloc : |
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{ |
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__got_start = .; |
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*(.got) |
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__got_end = .; |
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_GOT2_TABLE_ = .; |
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*(.got2) |
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_FIXUP_TABLE_ = .; |
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*(.fixup) |
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} |
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__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; |
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__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
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.data : |
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{ |
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*(.data) |
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*(.data1) |
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*(.sdata) |
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*(.sdata2) |
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*(.dynamic) |
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CONSTRUCTORS |
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} |
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_edata = .; |
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PROVIDE (edata = .); |
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. = .; |
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__u_boot_cmd_start = .; |
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.u_boot_cmd : { *(.u_boot_cmd) } |
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__u_boot_cmd_end = .; |
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. = .; |
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__start___ex_table = .; |
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__ex_table : { *(__ex_table) } |
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__stop___ex_table = .; |
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. = ALIGN(256); |
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__init_begin = .; |
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.text.init : { *(.text.init) } |
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.data.init : { *(.data.init) } |
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. = ALIGN(256); |
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__init_end = .; |
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__bss_start = .; |
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.bss : |
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{ |
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_sbss = .; |
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*(.sbss) *(.scommon) |
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*(.dynbss) |
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*(.bss) |
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*(COMMON) |
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. = ALIGN(4); |
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_ebss = .; |
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} |
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_end = . ; |
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PROVIDE (end = .); |
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} |
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/*
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* Configuation settings for the esd TASREG board. |
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* |
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* (C) Copyright 2004 |
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* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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/*
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* board/config.h - configuration options, board specific |
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*/ |
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#ifndef _M5249EVB_H |
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#define _M5249EVB_H |
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/*
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* High Level Configuration Options |
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* (easy to change) |
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*/ |
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#define CONFIG_MCF52x2 /* define processor family */ |
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#define CONFIG_M5249 /* define processor type */ |
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#define CONFIG_MCFTMR |
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#define CONFIG_MCFUART |
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#define CFG_UART_PORT (0) |
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#define CONFIG_BAUDRATE 19200 |
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#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } |
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#undef CONFIG_WATCHDOG |
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#undef CONFIG_MONITOR_IS_IN_RAM /* no pre-loader required!!! ;-) */ |
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/*
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* BOOTP options |
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*/ |
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#undef CONFIG_BOOTP_BOOTFILESIZE |
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#undef CONFIG_BOOTP_BOOTPATH |
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#undef CONFIG_BOOTP_GATEWAY |
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#undef CONFIG_BOOTP_HOSTNAME |
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/*
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* Command line configuration. |
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*/ |
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#include <config_cmd_default.h> |
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#undef CONFIG_CMD_NET |
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#define CFG_PROMPT "=> " |
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#define CFG_LONGHELP /* undef to save memory */ |
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#if defined(CONFIG_CMD_KGDB) |
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
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#else |
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
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#endif |
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
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#define CFG_MAXARGS 16 /* max number of command args */ |
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
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#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ |
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#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup */ |
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#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ |
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#define CONFIG_LOOPW 1 /* enable loopw command */ |
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#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ |
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#define CFG_LOAD_ADDR 0x200000 /* default load address */ |
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#define CFG_MEMTEST_START 0x400 |
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#define CFG_MEMTEST_END 0x380000 |
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#define CFG_HZ 1000 |
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/*
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* Clock configuration: enable only one of the following options |
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*/ |
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#undef CFG_PLL_BYPASS /* bypass PLL for test purpose */ |
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#define CFG_FAST_CLK 1 /* MCF5249 can run at 140MHz */ |
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#define CFG_CLK 132025600 /* MCF5249 can run at 140MHz */ |
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/*
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* Low Level Configuration Settings |
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* (address mappings, register initial values, etc.) |
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* You should know what you are doing if you make changes here. |
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*/ |
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#define CFG_MBAR 0x10000000 /* Register Base Addrs */ |
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#define CFG_MBAR2 0x80000000 |
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in DPRAM) |
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*/ |
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#define CFG_INIT_RAM_ADDR 0x20000000 |
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#define CFG_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */ |
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#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ |
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
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#define CFG_ENV_IS_IN_FLASH 1 |
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#define CFG_ENV_OFFSET 0x4000 /* Address of Environment Sector*/ |
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#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ |
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#define CFG_ENV_SECT_SIZE 0x2000 /* see README - env sector total size */ |
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|
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration |
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* (Set up by the startup code) |
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* Please note that CFG_SDRAM_BASE _must_ start at 0 |
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*/ |
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#define CFG_SDRAM_BASE 0x00000000 |
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#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */ |
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#define CFG_FLASH_BASE (CFG_CSAR0 << 16) |
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#if 0 /* test-only */
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#define CONFIG_PRAM 512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */ |
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#endif |
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#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) |
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#define CFG_MONITOR_LEN 0x20000 |
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#define CFG_MALLOC_LEN (1 * 1024*1024) /* Reserve 1 MB for malloc() */ |
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#define CFG_BOOTPARAMS_LEN 64*1024 |
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|
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/*
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* For booting Linux, the board info and command line data |
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* have to be in the first 8 MB of memory, since this is |
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* the maximum mapped by the Linux kernel during initialization ?? |
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*/ |
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#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20)) |
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|
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/*-----------------------------------------------------------------------
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* FLASH organization |
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*/ |
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#define CFG_FLASH_CFI |
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#ifdef CFG_FLASH_CFI |
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|
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# define CFG_FLASH_CFI_DRIVER 1 |
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# define CFG_FLASH_SIZE 0x1000000 /* Max size that the board might have */ |
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# define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT |
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# define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
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# define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ |
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# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ |
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# define CFG_FLASH_CHECKSUM |
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# define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } |
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#endif |
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|
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/*-----------------------------------------------------------------------
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* Cache Configuration |
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*/ |
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#define CFG_CACHELINE_SIZE 16 |
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|
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/*-----------------------------------------------------------------------
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* Memory bank definitions |
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*/ |
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|
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/* CS0 - AMD Flash, address 0xffc00000 */ |
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#define CFG_CSAR0 0xffe0 |
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#define CFG_CSCR0 0x1980 /* WS=0110, AA=1, PS=10 */ |
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/** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/ |
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#define CFG_CSMR0 0x003f0021 /* 4MB, AA=0, WP=0, C/I=1, V=1 */ |
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|
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/* CS1 - FPGA, address 0xe0000000 */ |
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#define CFG_CSAR1 0xe000 |
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#define CFG_CSCR1 0x0d80 /* WS=0011, AA=1, PS=10 */ |
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#define CFG_CSMR1 0x00010001 /* 128kB, AA=0, WP=0, C/I=0, V=1*/ |
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|
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/*-----------------------------------------------------------------------
|
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* Port configuration |
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*/ |
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#define CFG_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ |
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#define CFG_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54*/ |
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#define CFG_GPIO_EN 0x00000008 /* Set gpio output enable */ |
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#define CFG_GPIO1_EN 0x00c70000 /* Set gpio output enable */ |
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#define CFG_GPIO_OUT 0x00000008 /* Set outputs to default state */ |
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#define CFG_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ |
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#define CFG_GPIO1_LED 0x00400000 /* user led */ |
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|
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#endif /* M5249 */ |
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Loading…
Reference in new issue