* Patch by Pierre Aubert, 20 Nov 2002 Add driver for Epson SED13806 graphic controller. Add support for BMP logos in cfb_console driver.master
wdenk
22 years ago
parent
ea909b7604
commit
a6c7ad2f65
@ -0,0 +1,353 @@ |
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/*
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* (C) Copyright 2002 |
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* Stäubli Faverges - <www.staubli.com> |
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* Pierre AUBERT p.aubert@staubli.com |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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/* Video support for the ECCX daughter board */ |
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#include <common.h> |
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#include <config.h> |
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#ifdef CONFIG_VIDEO_SED13806 |
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#include <sed13806.h> |
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/* Screen configurations: the initialization of the SD13806 depends on
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screen and on display mode. We handle only 8bpp and 16 bpp modes */ |
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/* ECCX board is supplied with a NEC NL6448BC20 screen */ |
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#ifdef CONFIG_NEC_NL6448BC20 |
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#define DISPLAY_WIDTH 640 |
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#define DISPLAY_HEIGHT 480 |
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#ifdef CONFIG_VIDEO_SED13806_8BPP |
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static const S1D_REGS init_regs [] =
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{ |
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{0x0001,0x00}, // Miscellaneous Register
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{0x01FC,0x00}, // Display Mode Register
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{0x0004,0x1b}, // General IO Pins Configuration Register 0
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{0x0005,0x00}, // General IO Pins Configuration Register 1
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{0x0008,0xe5}, // General IO Pins Control Register 0
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{0x0009,0x1f}, // General IO Pins Control Register 1
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{0x0010,0x02}, // Memory Clock Configuration Register
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{0x0014,0x10}, // LCD Pixel Clock Configuration Register
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{0x0018,0x02}, // CRT/TV Pixel Clock Configuration Register
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{0x001C,0x02}, // MediaPlug Clock Configuration Register
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{0x001E,0x01}, // CPU To Memory Wait State Select Register
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{0x0021,0x04}, // DRAM Refresh Rate Register
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{0x002A,0x00}, // DRAM Timings Control Register 0
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{0x002B,0x01}, // DRAM Timings Control Register 1
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{0x0020,0x80}, // Memory Configuration Register
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{0x0030,0x25}, // Panel Type Register
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{0x0031,0x00}, // MOD Rate Register
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{0x0032,0x4F}, // LCD Horizontal Display Width Register
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{0x0034,0x13}, // LCD Horizontal Non-Display Period Register
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{0x0035,0x01}, // TFT FPLINE Start Position Register
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{0x0036,0x0B}, // TFT FPLINE Pulse Width Register
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{0x0038,0xDF}, // LCD Vertical Display Height Register 0
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{0x0039,0x01}, // LCD Vertical Display Height Register 1
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{0x003A,0x2C}, // LCD Vertical Non-Display Period Register
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{0x003B,0x00}, // TFT FPFRAME Start Position Register
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{0x003C,0x01}, // TFT FPFRAME Pulse Width Register
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{0x0040,0x03}, // LCD Display Mode Register
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{0x0041,0x02}, // LCD Miscellaneous Register
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{0x0042,0x00}, // LCD Display Start Address Register 0
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{0x0043,0x00}, // LCD Display Start Address Register 1
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{0x0044,0x00}, // LCD Display Start Address Register 2
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{0x0046,0x40}, // LCD Memory Address Offset Register 0
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{0x0047,0x01}, // LCD Memory Address Offset Register 1
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{0x0048,0x00}, // LCD Pixel Panning Register
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{0x004A,0x00}, // LCD Display FIFO High Threshold Control Register
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{0x004B,0x00}, // LCD Display FIFO Low Threshold Control Register
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{0x0050,0x4F}, // CRT/TV Horizontal Display Width Register
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{0x0052,0x13}, // CRT/TV Horizontal Non-Display Period Register
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{0x0053,0x01}, // CRT/TV HRTC Start Position Register
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{0x0054,0x0B}, // CRT/TV HRTC Pulse Width Register
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{0x0056,0xDF}, // CRT/TV Vertical Display Height Register 0
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{0x0057,0x01}, // CRT/TV Vertical Display Height Register 1
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{0x0058,0x2B}, // CRT/TV Vertical Non-Display Period Register
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{0x0059,0x09}, // CRT/TV VRTC Start Position Register
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{0x005A,0x01}, // CRT/TV VRTC Pulse Width Register
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{0x005B,0x00}, // TV Output Control Register
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{0x0060,0x03}, // CRT/TV Display Mode Register
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{0x0062,0x00}, // CRT/TV Display Start Address Register 0
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{0x0063,0x00}, // CRT/TV Display Start Address Register 1
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{0x0064,0x00}, // CRT/TV Display Start Address Register 2
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{0x0066,0x40}, // CRT/TV Memory Address Offset Register 0
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{0x0067,0x01}, // CRT/TV Memory Address Offset Register 1
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{0x0068,0x00}, // CRT/TV Pixel Panning Register
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{0x006A,0x00}, // CRT/TV Display FIFO High Threshold Control Register
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{0x006B,0x00}, // CRT/TV Display FIFO Low Threshold Control Register
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{0x0070,0x00}, // LCD Ink/Cursor Control Register
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{0x0071,0x00}, // LCD Ink/Cursor Start Address Register
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{0x0072,0x00}, // LCD Cursor X Position Register 0
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{0x0073,0x00}, // LCD Cursor X Position Register 1
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{0x0074,0x00}, // LCD Cursor Y Position Register 0
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{0x0075,0x00}, // LCD Cursor Y Position Register 1
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{0x0076,0x00}, // LCD Ink/Cursor Blue Color 0 Register
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{0x0077,0x00}, // LCD Ink/Cursor Green Color 0 Register
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{0x0078,0x00}, // LCD Ink/Cursor Red Color 0 Register
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{0x007A,0x1F}, // LCD Ink/Cursor Blue Color 1 Register
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{0x007B,0x3F}, // LCD Ink/Cursor Green Color 1 Register
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{0x007C,0x1F}, // LCD Ink/Cursor Red Color 1 Register
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{0x007E,0x00}, // LCD Ink/Cursor FIFO Threshold Register
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{0x0080,0x00}, // CRT/TV Ink/Cursor Control Register
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{0x0081,0x00}, // CRT/TV Ink/Cursor Start Address Register
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{0x0082,0x00}, // CRT/TV Cursor X Position Register 0
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{0x0083,0x00}, // CRT/TV Cursor X Position Register 1
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{0x0084,0x00}, // CRT/TV Cursor Y Position Register 0
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{0x0085,0x00}, // CRT/TV Cursor Y Position Register 1
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{0x0086,0x00}, // CRT/TV Ink/Cursor Blue Color 0 Register
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{0x0087,0x00}, // CRT/TV Ink/Cursor Green Color 0 Register
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{0x0088,0x00}, // CRT/TV Ink/Cursor Red Color 0 Register
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{0x008A,0x1F}, // CRT/TV Ink/Cursor Blue Color 1 Register
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{0x008B,0x3F}, // CRT/TV Ink/Cursor Green Color 1 Register
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{0x008C,0x1F}, // CRT/TV Ink/Cursor Red Color 1 Register
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{0x008E,0x00}, // CRT/TV Ink/Cursor FIFO Threshold Register
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{0x0100,0x00}, // BitBlt Control Register 0
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{0x0101,0x00}, // BitBlt Control Register 1
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{0x0102,0x00}, // BitBlt ROP Code/Color Expansion Register
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{0x0103,0x00}, // BitBlt Operation Register
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{0x0104,0x00}, // BitBlt Source Start Address Register 0
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{0x0105,0x00}, // BitBlt Source Start Address Register 1
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{0x0106,0x00}, // BitBlt Source Start Address Register 2
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{0x0108,0x00}, // BitBlt Destination Start Address Register 0
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{0x0109,0x00}, // BitBlt Destination Start Address Register 1
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{0x010A,0x00}, // BitBlt Destination Start Address Register 2
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{0x010C,0x00}, // BitBlt Memory Address Offset Register 0
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{0x010D,0x00}, // BitBlt Memory Address Offset Register 1
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{0x0110,0x00}, // BitBlt Width Register 0
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{0x0111,0x00}, // BitBlt Width Register 1
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{0x0112,0x00}, // BitBlt Height Register 0
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{0x0113,0x00}, // BitBlt Height Register 1
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{0x0114,0x00}, // BitBlt Background Color Register 0
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{0x0115,0x00}, // BitBlt Background Color Register 1
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{0x0118,0x00}, // BitBlt Foreground Color Register 0
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{0x0119,0x00}, // BitBlt Foreground Color Register 1
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{0x01E0,0x00}, // Look-Up Table Mode Register
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{0x01E2,0x00}, // Look-Up Table Address Register
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{0x01E4,0x00}, // Look-Up Table Data Register
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{0x01F0,0x10}, // Power Save Configuration Register
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{0x01F1,0x00}, // Power Save Status Register
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{0x01F4,0x00}, // CPU-to-Memory Access Watchdog Timer Register
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{0x01FC,0x01}, // Display Mode Register
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{0, 0} |
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}; |
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#endif /* CONFIG_VIDEO_SED13806_8BPP */ |
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#ifdef CONFIG_VIDEO_SED13806_16BPP |
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static const S1D_REGS init_regs [] =
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{ |
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{0x0001,0x00}, // Miscellaneous Register
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{0x01FC,0x00}, // Display Mode Register
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{0x0004,0x1b}, // General IO Pins Configuration Register 0
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{0x0005,0x00}, // General IO Pins Configuration Register 1
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{0x0008,0xe5}, // General IO Pins Control Register 0
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{0x0009,0x1f}, // General IO Pins Control Register 1
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{0x0010,0x02}, // Memory Clock Configuration Register
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{0x0014,0x10}, // LCD Pixel Clock Configuration Register
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{0x0018,0x02}, // CRT/TV Pixel Clock Configuration Register
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{0x001C,0x02}, // MediaPlug Clock Configuration Register
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{0x001E,0x01}, // CPU To Memory Wait State Select Register
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{0x0021,0x04}, // DRAM Refresh Rate Register
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{0x002A,0x00}, // DRAM Timings Control Register 0
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{0x002B,0x01}, // DRAM Timings Control Register 1
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{0x0020,0x80}, // Memory Configuration Register
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{0x0030,0x25}, // Panel Type Register
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{0x0031,0x00}, // MOD Rate Register
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{0x0032,0x4F}, // LCD Horizontal Display Width Register
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{0x0034,0x13}, // LCD Horizontal Non-Display Period Register
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{0x0035,0x01}, // TFT FPLINE Start Position Register
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{0x0036,0x0B}, // TFT FPLINE Pulse Width Register
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{0x0038,0xDF}, // LCD Vertical Display Height Register 0
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{0x0039,0x01}, // LCD Vertical Display Height Register 1
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{0x003A,0x2C}, // LCD Vertical Non-Display Period Register
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{0x003B,0x00}, // TFT FPFRAME Start Position Register
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{0x003C,0x01}, // TFT FPFRAME Pulse Width Register
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{0x0040,0x05}, // LCD Display Mode Register
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{0x0041,0x02}, // LCD Miscellaneous Register
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{0x0042,0x00}, // LCD Display Start Address Register 0
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{0x0043,0x00}, // LCD Display Start Address Register 1
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{0x0044,0x00}, // LCD Display Start Address Register 2
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{0x0046,0x80}, // LCD Memory Address Offset Register 0
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{0x0047,0x02}, // LCD Memory Address Offset Register 1
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{0x0048,0x00}, // LCD Pixel Panning Register
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{0x004A,0x00}, // LCD Display FIFO High Threshold Control Register
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{0x004B,0x00}, // LCD Display FIFO Low Threshold Control Register
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{0x0050,0x4F}, // CRT/TV Horizontal Display Width Register
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{0x0052,0x13}, // CRT/TV Horizontal Non-Display Period Register
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{0x0053,0x01}, // CRT/TV HRTC Start Position Register
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{0x0054,0x0B}, // CRT/TV HRTC Pulse Width Register
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{0x0056,0xDF}, // CRT/TV Vertical Display Height Register 0
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{0x0057,0x01}, // CRT/TV Vertical Display Height Register 1
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{0x0058,0x2B}, // CRT/TV Vertical Non-Display Period Register
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{0x0059,0x09}, // CRT/TV VRTC Start Position Register
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{0x005A,0x01}, // CRT/TV VRTC Pulse Width Register
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{0x005B,0x00}, // TV Output Control Register
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{0x0060,0x05}, // CRT/TV Display Mode Register
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{0x0062,0x00}, // CRT/TV Display Start Address Register 0
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{0x0063,0x00}, // CRT/TV Display Start Address Register 1
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{0x0064,0x00}, // CRT/TV Display Start Address Register 2
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{0x0066,0x80}, // CRT/TV Memory Address Offset Register 0
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{0x0067,0x02}, // CRT/TV Memory Address Offset Register 1
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{0x0068,0x00}, // CRT/TV Pixel Panning Register
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{0x006A,0x00}, // CRT/TV Display FIFO High Threshold Control Register
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{0x006B,0x00}, // CRT/TV Display FIFO Low Threshold Control Register
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{0x0070,0x00}, // LCD Ink/Cursor Control Register
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{0x0071,0x00}, // LCD Ink/Cursor Start Address Register
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{0x0072,0x00}, // LCD Cursor X Position Register 0
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{0x0073,0x00}, // LCD Cursor X Position Register 1
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{0x0074,0x00}, // LCD Cursor Y Position Register 0
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{0x0075,0x00}, // LCD Cursor Y Position Register 1
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{0x0076,0x00}, // LCD Ink/Cursor Blue Color 0 Register
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{0x0077,0x00}, // LCD Ink/Cursor Green Color 0 Register
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{0x0078,0x00}, // LCD Ink/Cursor Red Color 0 Register
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{0x007A,0x1F}, // LCD Ink/Cursor Blue Color 1 Register
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{0x007B,0x3F}, // LCD Ink/Cursor Green Color 1 Register
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{0x007C,0x1F}, // LCD Ink/Cursor Red Color 1 Register
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{0x007E,0x00}, // LCD Ink/Cursor FIFO Threshold Register
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{0x0080,0x00}, // CRT/TV Ink/Cursor Control Register
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{0x0081,0x00}, // CRT/TV Ink/Cursor Start Address Register
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{0x0082,0x00}, // CRT/TV Cursor X Position Register 0
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{0x0083,0x00}, // CRT/TV Cursor X Position Register 1
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{0x0084,0x00}, // CRT/TV Cursor Y Position Register 0
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{0x0085,0x00}, // CRT/TV Cursor Y Position Register 1
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{0x0086,0x00}, // CRT/TV Ink/Cursor Blue Color 0 Register
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{0x0087,0x00}, // CRT/TV Ink/Cursor Green Color 0 Register
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{0x0088,0x00}, // CRT/TV Ink/Cursor Red Color 0 Register
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{0x008A,0x1F}, // CRT/TV Ink/Cursor Blue Color 1 Register
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{0x008B,0x3F}, // CRT/TV Ink/Cursor Green Color 1 Register
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{0x008C,0x1F}, // CRT/TV Ink/Cursor Red Color 1 Register
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{0x008E,0x00}, // CRT/TV Ink/Cursor FIFO Threshold Register
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{0x0100,0x00}, // BitBlt Control Register 0
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{0x0101,0x00}, // BitBlt Control Register 1
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{0x0102,0x00}, // BitBlt ROP Code/Color Expansion Register
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{0x0103,0x00}, // BitBlt Operation Register
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{0x0104,0x00}, // BitBlt Source Start Address Register 0
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{0x0105,0x00}, // BitBlt Source Start Address Register 1
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{0x0106,0x00}, // BitBlt Source Start Address Register 2
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{0x0108,0x00}, // BitBlt Destination Start Address Register 0
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{0x0109,0x00}, // BitBlt Destination Start Address Register 1
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{0x010A,0x00}, // BitBlt Destination Start Address Register 2
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{0x010C,0x00}, // BitBlt Memory Address Offset Register 0
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{0x010D,0x00}, // BitBlt Memory Address Offset Register 1
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{0x0110,0x00}, // BitBlt Width Register 0
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{0x0111,0x00}, // BitBlt Width Register 1
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{0x0112,0x00}, // BitBlt Height Register 0
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{0x0113,0x00}, // BitBlt Height Register 1
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{0x0114,0x00}, // BitBlt Background Color Register 0
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{0x0115,0x00}, // BitBlt Background Color Register 1
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{0x0118,0x00}, // BitBlt Foreground Color Register 0
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{0x0119,0x00}, // BitBlt Foreground Color Register 1
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{0x01E0,0x01}, // Look-Up Table Mode Register
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{0x01E2,0x00}, // Look-Up Table Address Register
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{0x01E4,0x00}, // Look-Up Table Data Register
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{0x01F0,0x10}, // Power Save Configuration Register
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{0x01F1,0x00}, // Power Save Status Register
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{0x01F4,0x00}, // CPU-to-Memory Access Watchdog Timer Register
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{0x01FC,0x01}, // Display Mode Register
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{0, 0} |
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}; |
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#endif /* CONFIG_VIDEO_SED13806_16BPP */ |
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#endif /* CONFIG_NEC_NL6448BC20 */ |
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#ifdef CONFIG_CONSOLE_EXTRA_INFO |
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/*-----------------------------------------------------------------------------
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* video_get_info_str -- setup a board string: type, speed, etc. |
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* line_number= location to place info string beside logo |
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* info= buffer for info string |
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*----------------------------------------------------------------------------- |
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*/ |
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void video_get_info_str (int line_number, char *info) |
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{ |
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if (line_number == 1) { |
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strcpy (info, " RPXClassic board"); |
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} |
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else { |
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info [0] = '\0'; |
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} |
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} |
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#endif |
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/*-----------------------------------------------------------------------------
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* board_video_init -- init de l'EPSON, config du CS |
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*----------------------------------------------------------------------------- |
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*/ |
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unsigned int board_video_init (void) |
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{ |
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volatile immap_t *immap = (immap_t *)CFG_IMMR; |
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volatile memctl8xx_t *memctl = &immap->im_memctl; |
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/* Program ECCX registers */ |
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*(ECCX_CSR12) |= ECCX_860; |
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*(ECCX_CSR8) |= ECCX_BE | ECCX_CS2; |
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*(ECCX_CSR8) |= ECCX_ENEPSON; |
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memctl->memc_or2 = SED13806_OR; |
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memctl->memc_br2 = SED13806_REG_ADDR | SED13806_ACCES; |
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return (SED13806_REG_ADDR); |
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} |
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/*-----------------------------------------------------------------------------
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* board_validate_screen --
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*----------------------------------------------------------------------------- |
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*/ |
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void board_validate_screen (unsigned int base) |
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{ |
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/* Activate the panel bias power */ |
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*(volatile unsigned char *)(base + REG_GPIO_CTRL) = 0x80; |
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} |
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/*-----------------------------------------------------------------------------
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* board_get_regs --
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*----------------------------------------------------------------------------- |
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*/ |
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const S1D_REGS *board_get_regs (void) |
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{ |
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return (init_regs); |
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} |
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/*-----------------------------------------------------------------------------
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* board_get_width --
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*----------------------------------------------------------------------------- |
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*/ |
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int board_get_width (void) |
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{ |
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return (DISPLAY_WIDTH); |
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} |
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/*-----------------------------------------------------------------------------
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* board_get_height --
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*----------------------------------------------------------------------------- |
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*/ |
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int board_get_height (void) |
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{ |
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return (DISPLAY_HEIGHT); |
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} |
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#endif /* CONFIG_VIDEO_SED13806 */ |
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@ -0,0 +1,306 @@ |
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/*
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* (C) Copyright 2002 |
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* Stäubli Faverges - <www.staubli.com> |
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* Pierre AUBERT p.aubert@staubli.com |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
/* Video support for Epson SED13806 chipset */ |
||||
|
||||
#include <common.h> |
||||
|
||||
#ifdef CONFIG_VIDEO_SED13806 |
||||
|
||||
#include <video_fb.h> |
||||
#include <sed13806.h> |
||||
|
||||
#define readByte(ptrReg) \ |
||||
*(volatile unsigned char *)(sed13806.isaBase + ptrReg) |
||||
|
||||
#define writeByte(ptrReg,value) \ |
||||
*(volatile unsigned char *)(sed13806.isaBase + ptrReg) = value |
||||
|
||||
#define writeWord(ptrReg,value) \ |
||||
(*(volatile unsigned short *)(sed13806.isaBase + ptrReg) = ((value >> 8 ) & 0xff) | ((value << 8) & 0xff00)) |
||||
|
||||
|
||||
GraphicDevice sed13806; |
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* EpsonSetRegs --
|
||||
*----------------------------------------------------------------------------- |
||||
*/ |
||||
static void EpsonSetRegs (void) |
||||
{ |
||||
/* the content of the chipset register depends on the board (clocks, ...)*/ |
||||
const S1D_REGS *preg = board_get_regs (); |
||||
while (preg -> Index) { |
||||
writeByte (preg -> Index, preg -> Value); |
||||
preg ++; |
||||
} |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* video_hw_init --
|
||||
*----------------------------------------------------------------------------- |
||||
*/ |
||||
void *video_hw_init (void) |
||||
{ |
||||
unsigned int *vm, i; |
||||
|
||||
memset (&sed13806, 0, sizeof (GraphicDevice)); |
||||
|
||||
/* Initialization of the access to the graphic chipset
|
||||
Retreive base address of the chipset |
||||
(see board/RPXClassic/eccx.c) */ |
||||
if ((sed13806.isaBase = board_video_init ()) == 0) { |
||||
return (NULL); |
||||
} |
||||
|
||||
sed13806.frameAdrs = sed13806.isaBase + FRAME_BUFFER_OFFSET; |
||||
sed13806.winSizeX = board_get_width (); |
||||
sed13806.winSizeY = board_get_height (); |
||||
|
||||
#if defined(CONFIG_VIDEO_SED13806_8BPP) |
||||
sed13806.gdfIndex = GDF__8BIT_INDEX; |
||||
sed13806.gdfBytesPP = 1; |
||||
|
||||
#elif defined(CONFIG_VIDEO_SED13806_16BPP) |
||||
sed13806.gdfIndex = GDF_16BIT_565RGB; |
||||
sed13806.gdfBytesPP = 2; |
||||
|
||||
#else |
||||
#error Unsupported SED13806 BPP |
||||
#endif |
||||
|
||||
sed13806.memSize = sed13806.winSizeX * sed13806.winSizeY * sed13806.gdfBytesPP; |
||||
|
||||
/* Load SED registers */ |
||||
EpsonSetRegs (); |
||||
|
||||
/* (see board/RPXClassic/RPXClassic.c) */ |
||||
board_validate_screen (sed13806.isaBase); |
||||
|
||||
/* Clear video memory */ |
||||
i = sed13806.memSize/4; |
||||
vm = (unsigned int *)sed13806.frameAdrs; |
||||
while(i--) |
||||
*vm++ = 0; |
||||
|
||||
|
||||
return (&sed13806); |
||||
} |
||||
/*-----------------------------------------------------------------------------
|
||||
* Epson_wait_idle -- Wait for hardware to become idle |
||||
*----------------------------------------------------------------------------- |
||||
*/ |
||||
static void Epson_wait_idle (void) |
||||
{ |
||||
while (readByte (BLT_CTRL0) & 0x80); |
||||
|
||||
/* Read a word in the BitBLT memory area to shutdown the BitBLT engine */ |
||||
*(volatile unsigned short *)(sed13806.isaBase + BLT_REG); |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* video_hw_bitblt --
|
||||
*----------------------------------------------------------------------------- |
||||
*/ |
||||
void video_hw_bitblt ( |
||||
unsigned int bpp, /* bytes per pixel */ |
||||
unsigned int src_x, /* source pos x */ |
||||
unsigned int src_y, /* source pos y */ |
||||
unsigned int dst_x, /* dest pos x */ |
||||
unsigned int dst_y, /* dest pos y */ |
||||
unsigned int dim_x, /* frame width */ |
||||
unsigned int dim_y /* frame height */ |
||||
) |
||||
{ |
||||
register GraphicDevice *pGD = (GraphicDevice *)&sed13806; |
||||
unsigned long srcAddr, dstAddr; |
||||
unsigned int stride = bpp * pGD -> winSizeX; |
||||
|
||||
srcAddr = (src_y * stride) + (src_x * bpp); |
||||
dstAddr = (dst_y * stride) + (dst_x * bpp); |
||||
|
||||
Epson_wait_idle (); |
||||
|
||||
writeByte(BLT_ROP,0x0C); // source
|
||||
writeByte(BLT_OP,0x02);// move blit in positive direction with ROP
|
||||
writeWord(BLT_MEM_OFF0, stride / 2); |
||||
if (pGD -> gdfIndex == GDF__8BIT_INDEX) { |
||||
writeByte(BLT_CTRL1,0x00); |
||||
} |
||||
else { |
||||
writeByte(BLT_CTRL1,0x01); |
||||
} |
||||
|
||||
writeWord(BLT_WIDTH0,(dim_x - 1)); |
||||
writeWord(BLT_HEIGHT0,(dim_y - 1)); |
||||
|
||||
/* set up blit registers */ |
||||
writeByte(BLT_SRC_ADDR0,srcAddr); |
||||
writeByte(BLT_SRC_ADDR1,srcAddr>>8);
|
||||
writeByte(BLT_SRC_ADDR2,srcAddr>>16);
|
||||
|
||||
writeByte(BLT_DST_ADDR0,dstAddr); |
||||
writeByte(BLT_DST_ADDR1,dstAddr>>8);
|
||||
writeByte(BLT_DST_ADDR2,dstAddr>>16);
|
||||
|
||||
/* Engage the blt engine */ |
||||
/* rectangular region for src and dst */ |
||||
writeByte(BLT_CTRL0,0x80); |
||||
|
||||
/* wait untill current blits finished */ |
||||
Epson_wait_idle (); |
||||
} |
||||
/*-----------------------------------------------------------------------------
|
||||
* video_hw_rectfill --
|
||||
*----------------------------------------------------------------------------- |
||||
*/ |
||||
void video_hw_rectfill ( |
||||
unsigned int bpp, /* bytes per pixel */ |
||||
unsigned int dst_x, /* dest pos x */ |
||||
unsigned int dst_y, /* dest pos y */ |
||||
unsigned int dim_x, /* frame width */ |
||||
unsigned int dim_y, /* frame height */ |
||||
unsigned int color /* fill color */ |
||||
) |
||||
{ |
||||
register GraphicDevice *pGD = (GraphicDevice *)&sed13806; |
||||
unsigned long dstAddr; |
||||
unsigned int stride = bpp * pGD -> winSizeX; |
||||
|
||||
dstAddr = (dst_y * stride) + (dst_x * bpp); |
||||
|
||||
Epson_wait_idle (); |
||||
|
||||
/* set up blit registers */ |
||||
writeByte(BLT_DST_ADDR0,dstAddr); |
||||
writeByte(BLT_DST_ADDR1,dstAddr>>8);
|
||||
writeByte(BLT_DST_ADDR2,dstAddr>>16);
|
||||
|
||||
writeWord(BLT_WIDTH0,(dim_x - 1)); |
||||
writeWord(BLT_HEIGHT0,(dim_y - 1)); |
||||
writeWord(BLT_FGCOLOR0,color); |
||||
|
||||
writeByte(BLT_OP,0x0C); /* solid fill */ |
||||
writeWord(BLT_MEM_OFF0,stride / 2); |
||||
|
||||
if (pGD -> gdfIndex == GDF__8BIT_INDEX) { |
||||
writeByte(BLT_CTRL1,0x00); |
||||
} |
||||
else { |
||||
writeByte(BLT_CTRL1,0x01); |
||||
} |
||||
|
||||
/* Engage the blt engine */ |
||||
/* rectangular region for src and dst */ |
||||
writeByte(BLT_CTRL0,0x80); |
||||
|
||||
/* wait untill current blits finished */ |
||||
Epson_wait_idle (); |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* video_set_lut --
|
||||
*----------------------------------------------------------------------------- |
||||
*/ |
||||
void video_set_lut ( |
||||
unsigned int index, /* color number */ |
||||
unsigned char r, /* red */ |
||||
unsigned char g, /* green */ |
||||
unsigned char b /* blue */ |
||||
) |
||||
{ |
||||
writeByte(REG_LUT_ADDR, index ); |
||||
writeByte(REG_LUT_DATA, r); |
||||
writeByte(REG_LUT_DATA, g); |
||||
writeByte(REG_LUT_DATA, b); |
||||
} |
||||
#ifdef CONFIG_VIDEO_HW_CURSOR |
||||
/*-----------------------------------------------------------------------------
|
||||
* video_set_hw_cursor --
|
||||
*----------------------------------------------------------------------------- |
||||
*/ |
||||
void video_set_hw_cursor (int x, int y) |
||||
{ |
||||
writeByte (LCD_CURSOR_XL, (x & 0xff)); |
||||
writeByte (LCD_CURSOR_XM, (x >> 8)); |
||||
writeByte (LCD_CURSOR_YL, (y & 0xff)); |
||||
writeByte (LCD_CURSOR_YM, (y >> 8)); |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* video_init_hw_cursor --
|
||||
*----------------------------------------------------------------------------- |
||||
*/ |
||||
void video_init_hw_cursor (int font_width, int font_height) |
||||
{ |
||||
volatile unsigned char *ptr; |
||||
unsigned char pattern; |
||||
int i; |
||||
|
||||
|
||||
/* Init cursor content
|
||||
Cursor size is 64x64 pixels |
||||
Start of the cursor memory depends on panel type (dual panel ...) */ |
||||
if ((i = readByte (LCD_CURSOR_START)) == 0) { |
||||
ptr = (unsigned char *)(sed13806.frameAdrs + DEFAULT_VIDEO_MEMORY_SIZE - HWCURSORSIZE); |
||||
} |
||||
else { |
||||
ptr = (unsigned char *)(sed13806.frameAdrs + DEFAULT_VIDEO_MEMORY_SIZE - (i * 8192)); |
||||
} |
||||
|
||||
/* Fill the first line and the first empty line after cursor */ |
||||
for (i = 0, pattern = 0; i < 64; i++) { |
||||
if (i < font_width) { |
||||
/* Invert background */ |
||||
pattern |= 0x3; |
||||
|
||||
} |
||||
else { |
||||
/* Background */ |
||||
pattern |= 0x2; |
||||
} |
||||
if ((i & 3) == 3) { |
||||
*ptr = pattern; |
||||
*(ptr + font_height * 16) = 0xaa; |
||||
ptr ++; |
||||
pattern = 0; |
||||
} |
||||
pattern <<= 2; |
||||
} |
||||
|
||||
/* Duplicate this line */ |
||||
for (i = 1; i < font_height; i++) { |
||||
memcpy ((void *)ptr, (void *)(ptr - 16), 16); |
||||
ptr += 16; |
||||
} |
||||
|
||||
for (; i < 64; i++) { |
||||
memcpy ((void *)(ptr + 16), (void *)ptr, 16); |
||||
ptr += 16; |
||||
} |
||||
|
||||
/* Select cursor mode */ |
||||
writeByte (LCD_CURSOR_CNTL, 1); |
||||
} |
||||
#endif |
||||
#endif |
||||
@ -0,0 +1,98 @@ |
||||
/*
|
||||
* (C) Copyright 2002 |
||||
* Stäubli Faverges - <www.staubli.com> |
||||
* Pierre AUBERT p.aubert@staubli.com |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
/* Video support for Epson SED13806 chipset */ |
||||
|
||||
|
||||
#ifndef _SED13806_H_ |
||||
#define _SED13806_H_ |
||||
|
||||
|
||||
/* General definitions */ |
||||
#define FRAME_BUFFER_OFFSET 0x200000 /* Frame buffer offset */ |
||||
#define TOTAL_SPACE_SIZE 0x400000 |
||||
|
||||
#define DEFAULT_VIDEO_MEMORY_SIZE 0x140000 /* Video Memory Size */ |
||||
|
||||
#define HWCURSORSIZE 1024 /* Size of memory reserved |
||||
for HW cursor*/
|
||||
|
||||
/* Offset of chipset registers */ |
||||
#define BLT_CTRL0 (0x0100) |
||||
#define BLT_CTRL1 (0x0101) |
||||
#define BLT_ROP (0x0102) |
||||
#define BLT_OP (0x0103) |
||||
#define BLT_SRC_ADDR0 (0x0104) |
||||
#define BLT_SRC_ADDR1 (0x0105) |
||||
#define BLT_SRC_ADDR2 (0x0106) |
||||
#define BLT_DST_ADDR0 (0x0108) |
||||
#define BLT_DST_ADDR1 (0x0109) |
||||
#define BLT_DST_ADDR2 (0x010A) |
||||
#define BLT_MEM_OFF0 (0x010C) |
||||
#define BLT_MEM_OFF1 (0x010D) |
||||
#define BLT_WIDTH0 (0x0110) |
||||
#define BLT_WIDTH1 (0x0111) |
||||
#define BLT_HEIGHT0 (0x0112) |
||||
#define BLT_HEIGHT1 (0x0113) |
||||
#define BLT_BGCOLOR0 (0x0114) |
||||
#define BLT_BGCOLOR1 (0x0115) |
||||
#define BLT_FGCOLOR0 (0x0118) |
||||
#define BLT_FGCOLOR1 (0x0119) |
||||
|
||||
#define BLT_REG (0x100000) |
||||
|
||||
/* Lookup table registers */ |
||||
#define REG_LUT_ADDR 0x1e2 |
||||
#define REG_LUT_DATA 0x1e4 |
||||
|
||||
/* Cursor/Ink registers */ |
||||
#define LCD_CURSOR_CNTL (0x0070) |
||||
#define LCD_CURSOR_START (0x0071) |
||||
#define LCD_CURSOR_XL (0x0072) |
||||
#define LCD_CURSOR_XM (0x0073) |
||||
#define LCD_CURSOR_YL (0x0074) |
||||
#define LCD_CURSOR_YM (0x0075) |
||||
#define LCD_CURSOR_COL0_B (0x0076) |
||||
#define LCD_CURSOR_COL0_G (0x0077) |
||||
#define LCD_CURSOR_COL0_R (0x0078) |
||||
#define LCD_CURSOR_COL1_B (0x007A) |
||||
#define LCD_CURSOR_COL1_G (0x007B) |
||||
#define LCD_CURSOR_COL1_R (0x007C) |
||||
#define LCD_CURSOR_FIFO (0x007E) |
||||
|
||||
typedef struct |
||||
{ |
||||
unsigned short Index; |
||||
unsigned char Value; |
||||
} S1D_REGS; |
||||
|
||||
|
||||
|
||||
/* Board specific functions */ |
||||
unsigned int board_video_init (void); |
||||
void board_validate_screen (unsigned int base); |
||||
const S1D_REGS *board_get_regs (void); |
||||
int board_get_width (void); |
||||
int board_get_height (void); |
||||
|
||||
#endif /* _SED13806_H_ */ |
||||
Loading…
Reference in new issue