arm: socfpga: reset: Replace ad-hoc reset functions

Replace all those ad-hoc reset functions, which were all copies
of the same invocation of clrbits_le32() anyway, with one single
unified function, socfpga_per_reset(), with necessary parameters.

Signed-off-by: Marek Vasut <marex@denx.de>

arch/arm/mach-socfpga/include/mach/reset_manager.h

@@ -14,13 +14,6 @@ void socfpga_bridges_reset(int enable);
 
 void socfpga_per_reset(u32 reset, int set);
 
-void socfpga_emac_reset(int enable);
-void socfpga_watchdog_reset(void);
-void socfpga_spim_enable(void);
-void socfpga_uart0_enable(void);
-void socfpga_sdram_enable(void);
-void socfpga_osc1timer_enable(void);
-
 struct socfpga_reset_manager {
 	u32	status;
 	u32	ctrl;

arch/arm/mach-socfpga/misc.c

@@ -54,8 +54,10 @@ int cpu_eth_init(bd_t *bis)
 {
 #if CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS
 	const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB;
+	const u32 reset = SOCFPGA_RESET(EMAC0);
 #elif CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS
 	const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB;
+	const u32 reset = SOCFPGA_RESET(EMAC1);
 #else
 #error "Incorrect CONFIG_EMAC_BASE value!"
 #endif
@@ -66,7 +68,8 @@ int cpu_eth_init(bd_t *bis)
 	 * Putting the EMAC controller to reset when configuring the PHY
 	 * interface select at System Manager
 	 */
-	socfpga_emac_reset(1);
+	socfpga_per_reset(SOCFPGA_RESET(EMAC0), 1);
+	socfpga_per_reset(SOCFPGA_RESET(EMAC1), 1);
 
 	/* Clearing emac0 PHY interface select to 0 */
 	clrbits_le32(&sysmgr_regs->emacgrp_ctrl,
@@ -77,7 +80,7 @@ int cpu_eth_init(bd_t *bis)
 		     SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << physhift);
 
 	/* Release the EMAC controller from reset */
-	socfpga_emac_reset(0);
+	socfpga_per_reset(reset, 0);
 
 	/* initialize and register the emac */
 	return designware_initialize(CONFIG_EMAC_BASE,
@@ -164,8 +167,10 @@ int arch_cpu_init(void)
 	 * If the HW watchdog is NOT enabled, make sure it is not running,
 	 * for example because it was enabled in the preloader. This might
 	 * trigger a watchdog-triggered reboot of Linux kernel later.
+	 * Toggle watchdog reset, so watchdog in not running state.
 	 */
-	socfpga_watchdog_reset();
+	socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
+	socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
 #endif
 
 	return 0;
@@ -215,7 +220,8 @@ int arch_early_init_r(void)
 
 #ifdef CONFIG_DESIGNWARE_SPI
 	/* Get Designware SPI controller out of reset */
-	socfpga_spim_enable();
+	socfpga_per_reset(SOCFPGA_RESET(SPIM0), 0);
+	socfpga_per_reset(SOCFPGA_RESET(SPIM1), 0);
 #endif
 
 	return 0;

arch/arm/mach-socfpga/reset_manager.c

@@ -39,16 +39,6 @@ void socfpga_per_reset(u32 reset, int set)
 		clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
 }
 
-/* Toggle reset signal to watchdog (WDT is disabled after this operation!) */
-void socfpga_watchdog_reset(void)
-{
-	/* assert reset for watchdog */
-	socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
-
-	/* deassert watchdog from reset (watchdog in not running state) */
-	socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
-}
-
 /*
  * Write the reset manager register to cause reset
  */
@@ -109,43 +99,3 @@ void socfpga_bridges_reset(int enable)
 	}
 }
 #endif
-
-/* Change the reset state for EMAC 0 and EMAC 1 */
-void socfpga_emac_reset(int enable)
-{
-	if (enable) {
-		socfpga_per_reset(SOCFPGA_RESET(EMAC0), 1);
-		socfpga_per_reset(SOCFPGA_RESET(EMAC1), 1);
-	} else {
-#if (CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS)
-		socfpga_per_reset(SOCFPGA_RESET(EMAC0), 0);
-#elif (CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS)
-		socfpga_per_reset(SOCFPGA_RESET(EMAC1), 0);
-#endif
-	}
-}
-
-/* SPI Master enable (its held in reset by the preloader) */
-void socfpga_spim_enable(void)
-{
-	socfpga_per_reset(SOCFPGA_RESET(SPIM0), 0);
-	socfpga_per_reset(SOCFPGA_RESET(SPIM1), 0);
-}
-
-/* Bring UART0 out of reset. */
-void socfpga_uart0_enable(void)
-{
-	socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
-}
-
-/* Bring SDRAM controller out of reset. */
-void socfpga_sdram_enable(void)
-{
-	socfpga_per_reset(SOCFPGA_RESET(SDR), 0);
-}
-
-/* Bring OSC1 timer out of reset. */
-void socfpga_osc1timer_enable(void)
-{
-	socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
-}

arch/arm/mach-socfpga/spl.c

@@ -175,9 +175,9 @@ void spl_board_init(void)
 	/* freeze all IO banks */
 	sys_mgr_frzctrl_freeze_req();
 
-	socfpga_sdram_enable();
-	socfpga_uart0_enable();
-	socfpga_osc1timer_enable();
+	socfpga_per_reset(SOCFPGA_RESET(SDR), 0);
+	socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
+	socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
 
 	timer_init();