With the introducing of generic board and ARM-based cores, current deep sleep framework doesn't work anymore. This patch will convert the current framework to adapt this change. Basically it does: 1. Converts all the Freescale's DDR driver to support deep sleep. 2. Added basic framework support for ARM-based and PPC-based cores separately. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>master
Tang Yuantian
10 years ago
committed by
York Sun
parent
da5ce448c7
commit
a7787b7850
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/*
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* Copyright 2014 Freescale Semiconductor, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/io.h> |
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#if !defined(CONFIG_ARMV7_NONSEC) || !defined(CONFIG_ARMV7_VIRT) |
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#error " Deep sleep needs non-secure mode support. " |
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#else |
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#include <asm/secure.h> |
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#endif |
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#include <asm/armv7.h> |
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#include <asm/cache.h> |
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#if defined(CONFIG_LS102XA) |
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#include <asm/arch/immap_ls102xa.h> |
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#endif |
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#include "sleep.h" |
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DECLARE_GLOBAL_DATA_PTR; |
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void __weak board_mem_sleep_setup(void) |
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{ |
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} |
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void __weak board_sleep_prepare(void) |
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{ |
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} |
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bool is_warm_boot(void) |
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{ |
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struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; |
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if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR) |
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return 1; |
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return 0; |
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} |
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void fsl_dp_disable_console(void) |
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{ |
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gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE; |
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} |
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/*
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* When wakeup from deep sleep, the first 128 bytes space |
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* will be used to do DDR training which corrupts the data |
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* in there. This function will restore them. |
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*/ |
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static void dp_ddr_restore(void) |
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{ |
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u64 *src, *dst; |
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int i; |
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struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR; |
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/* get the address of ddr date from SPARECR3 */ |
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src = (u64 *)in_le32(&scfg->sparecr[2]); |
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dst = (u64 *)CONFIG_SYS_SDRAM_BASE; |
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for (i = 0; i < DDR_BUFF_LEN / 8; i++) |
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*dst++ = *src++; |
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flush_dcache_all(); |
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} |
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static void dp_resume_prepare(void) |
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{ |
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dp_ddr_restore(); |
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board_sleep_prepare(); |
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armv7_init_nonsec(); |
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cleanup_before_linux(); |
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} |
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int fsl_dp_resume(void) |
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{ |
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u32 start_addr; |
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void (*kernel_resume)(void); |
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struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR; |
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if (!is_warm_boot()) |
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return 0; |
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dp_resume_prepare(); |
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/* Get the entry address and jump to kernel */ |
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start_addr = in_le32(&scfg->sparecr[1]); |
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debug("Entry address is 0x%08x\n", start_addr); |
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kernel_resume = (void (*)(void))start_addr; |
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secure_ram_addr(_do_nonsec_entry)(kernel_resume, 0, 0, 0); |
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return 0; |
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} |
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@ -0,0 +1,88 @@ |
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/*
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* Copyright 2014 Freescale Semiconductor, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/immap_85xx.h> |
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#include "sleep.h" |
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DECLARE_GLOBAL_DATA_PTR; |
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void __weak board_mem_sleep_setup(void) |
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{ |
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} |
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void __weak board_sleep_prepare(void) |
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{ |
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} |
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bool is_warm_boot(void) |
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{ |
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struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; |
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if (in_be32(&gur->scrtsr[0]) & DCFG_CCSR_CRSTSR_WDRFR) |
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return 1; |
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return 0; |
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} |
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void fsl_dp_disable_console(void) |
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{ |
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gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE; |
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} |
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/*
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* When wakeup from deep sleep, the first 128 bytes space |
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* will be used to do DDR training which corrupts the data |
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* in there. This function will restore them. |
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*/ |
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static void dp_ddr_restore(void) |
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{ |
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volatile u64 *src, *dst; |
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int i; |
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struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_MPC85xx_SCFG; |
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/* get the address of ddr date from SPARECR3 */ |
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src = (u64 *)in_be32(&scfg->sparecr[2]); |
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dst = (u64 *)CONFIG_SYS_SDRAM_BASE; |
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for (i = 0; i < DDR_BUFF_LEN / 8; i++) |
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*dst++ = *src++; |
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flush_dcache(); |
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} |
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static void dp_resume_prepare(void) |
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{ |
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dp_ddr_restore(); |
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board_sleep_prepare(); |
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l2cache_init(); |
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#if defined(CONFIG_RAMBOOT_PBL) |
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disable_cpc_sram(); |
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#endif |
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enable_cpc(); |
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} |
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int fsl_dp_resume(void) |
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{ |
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u32 start_addr; |
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void (*kernel_resume)(void); |
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struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_MPC85xx_SCFG; |
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if (!is_warm_boot()) |
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return 0; |
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dp_resume_prepare(); |
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/* Get the entry address and jump to kernel */ |
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start_addr = in_be32(&scfg->sparecr[1]); |
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debug("Entry address is 0x%08x\n", start_addr); |
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kernel_resume = (void (*)(void))start_addr; |
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kernel_resume(); |
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return 0; |
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} |
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@ -0,0 +1,21 @@ |
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/*
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* Copyright 2014 Freescale Semiconductor, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef __SLEEP_H |
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#define __SLEEP_H |
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#define DCFG_CCSR_CRSTSR_WDRFR (1 << 3) |
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#define DDR_BUFF_LEN 128 |
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/* determine if it is a wakeup from deep sleep */ |
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bool is_warm_boot(void); |
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/* disable console output */ |
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void fsl_dp_disable_console(void); |
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/* clean up everything and jump to kernel */ |
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int fsl_dp_resume(void); |
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#endif |
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