OMAP Voltage controller is used to generically talk to PMICs on OMAP3,4,5 over I2C_SR. Instead of replicating code in multiple SoC code, introduce a common voltage controller logic which can be re-used from elsewhere. With this change, we replace setup_sri2c with omap_vc_init which has the same functionality, and replace the voltage scale replication in do_scale_vcore and do_scale_tps62361 with omap_vc_bypass_send_value. omap_vc_bypass_send_value can also now be used with any configuration of PMIC. NOTE: Voltage controller controlling I2C_SR is a write-only data path, so no register read operation can be implemented. Reported-by: Isabelle Gros <i-gros@ti.com> Reported-by: Jerome Angeloni <j-angeloni@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>master
Nishanth Menon
12 years ago
committed by
Albert ARIBAUD
parent
bbbc1ae921
commit
a78274b205
@ -0,0 +1,138 @@ |
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/*
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* Voltage Controller implementation for OMAP |
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* |
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* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
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* Nishanth Menon |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License version 2 as |
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* published by the Free Software Foundation. |
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* |
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any |
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* kind, whether express or implied; without even the implied warranty |
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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*/ |
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#include <common.h> |
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#include <asm/omap_common.h> |
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#include <asm/arch/sys_proto.h> |
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/*
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* Define Master code if there are multiple masters on the I2C_SR bus. |
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* Normally not required |
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*/ |
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#ifndef CONFIG_OMAP_VC_I2C_HS_MCODE |
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#define CONFIG_OMAP_VC_I2C_HS_MCODE 0x0 |
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#endif |
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/* Register defines and masks for VC IP Block */ |
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/* PRM_VC_CFG_I2C_MODE */ |
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#define PRM_VC_CFG_I2C_MODE_DFILTEREN_BIT (0x1 << 6) |
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#define PRM_VC_CFG_I2C_MODE_SRMODEEN_BIT (0x1 << 4) |
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#define PRM_VC_CFG_I2C_MODE_HSMODEEN_BIT (0x1 << 3) |
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#define PRM_VC_CFG_I2C_MODE_HSMCODE_SHIFT 0x0 |
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#define PRM_VC_CFG_I2C_MODE_HSMCODE_MASK 0x3 |
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/* PRM_VC_CFG_I2C_CLK */ |
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#define PRM_VC_CFG_I2C_CLK_HSCLL_SHIFT 24 |
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#define PRM_VC_CFG_I2C_CLK_HSCLL_MASK 0xFF |
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#define PRM_VC_CFG_I2C_CLK_HSCLH_SHIFT 16 |
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#define PRM_VC_CFG_I2C_CLK_HSCLH_MASK 0xFF |
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#define PRM_VC_CFG_I2C_CLK_SCLH_SHIFT 0 |
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#define PRM_VC_CFG_I2C_CLK_SCLH_MASK 0xFF |
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#define PRM_VC_CFG_I2C_CLK_SCLL_SHIFT 8 |
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#define PRM_VC_CFG_I2C_CLK_SCLL_MASK (0xFF << 8) |
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/* PRM_VC_VAL_BYPASS */ |
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#define PRM_VC_VAL_BYPASS_VALID_BIT (0x1 << 24) |
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#define PRM_VC_VAL_BYPASS_SLAVEADDR_SHIFT 0 |
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#define PRM_VC_VAL_BYPASS_SLAVEADDR_MASK 0x7F |
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#define PRM_VC_VAL_BYPASS_REGADDR_SHIFT 8 |
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#define PRM_VC_VAL_BYPASS_REGADDR_MASK 0xFF |
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#define PRM_VC_VAL_BYPASS_DATA_SHIFT 16 |
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#define PRM_VC_VAL_BYPASS_DATA_MASK 0xFF |
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/**
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* omap_vc_init() - Initialization for Voltage controller |
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* @speed_khz: I2C buspeed in KHz |
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*/ |
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void omap_vc_init(u16 speed_khz) |
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{ |
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u32 val; |
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u32 sys_clk_khz, cycles_hi, cycles_low; |
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sys_clk_khz = get_sys_clk_freq() / 1000; |
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if (speed_khz > 400) { |
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puts("higher speed requested - throttle to 400Khz\n"); |
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speed_khz = 400; |
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} |
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/*
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* Setup the dedicated I2C controller for Voltage Control |
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* I2C clk - high period 40% low period 60% |
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*/ |
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speed_khz /= 10; |
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cycles_hi = sys_clk_khz * 4 / speed_khz; |
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cycles_low = sys_clk_khz * 6 / speed_khz; |
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/* values to be set in register - less by 5 & 7 respectively */ |
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cycles_hi -= 5; |
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cycles_low -= 7; |
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val = (cycles_hi << PRM_VC_CFG_I2C_CLK_SCLH_SHIFT) | |
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(cycles_low << PRM_VC_CFG_I2C_CLK_SCLL_SHIFT); |
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writel(val, &prcm->prm_vc_cfg_i2c_clk); |
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val = CONFIG_OMAP_VC_I2C_HS_MCODE << |
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PRM_VC_CFG_I2C_MODE_HSMCODE_SHIFT; |
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/* No HS mode for now */ |
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val &= ~PRM_VC_CFG_I2C_MODE_HSMODEEN_BIT; |
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writel(val, &prcm->prm_vc_cfg_i2c_mode); |
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} |
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/**
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* omap_vc_bypass_send_value() - Send a data using VC Bypass command |
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* @sa: 7 bit I2C slave address of the PMIC |
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* @reg_addr: I2C register address(8 bit) address in PMIC |
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* @reg_data: what 8 bit data to write |
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*/ |
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int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data) |
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{ |
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/*
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* Unfortunately we need to loop here instead of a defined time |
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* use arbitary large value |
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*/ |
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u32 timeout = 0xFFFF; |
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u32 reg_val; |
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sa &= PRM_VC_VAL_BYPASS_SLAVEADDR_MASK; |
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reg_addr &= PRM_VC_VAL_BYPASS_REGADDR_MASK; |
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reg_data &= PRM_VC_VAL_BYPASS_DATA_MASK; |
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/* program VC to send data */ |
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reg_val = sa << PRM_VC_VAL_BYPASS_SLAVEADDR_SHIFT | |
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reg_addr << PRM_VC_VAL_BYPASS_REGADDR_SHIFT | |
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reg_data << PRM_VC_VAL_BYPASS_DATA_SHIFT; |
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writel(reg_val, &prcm->prm_vc_val_bypass); |
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/* Signal VC to send data */ |
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writel(reg_val | PRM_VC_VAL_BYPASS_VALID_BIT, &prcm->prm_vc_val_bypass); |
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/* Wait on VC to complete transmission */ |
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do { |
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reg_val = readl(&prcm->prm_vc_val_bypass) & |
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PRM_VC_VAL_BYPASS_VALID_BIT; |
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if (!reg_val) |
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break; |
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sdelay(100); |
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} while (--timeout); |
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/* Optional: cleanup PRM_IRQSTATUS_Ax */ |
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/* In case we can do something about it in future.. */ |
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if (!timeout) |
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return -1; |
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/* All good.. */ |
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return 0; |
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} |
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