Initial support for the DS4510, a CPU supervisor with integrated EEPROM, SRAM, and 4 programmable non-volatile GPIO pins. The CONFIG_DS4510 define enables support for the device while the CONFIG_CMD_DS4510 define enables the ds4510 command. The additional CONFIG_DS4510_INFO, CONFIG_DS4510_MEM, and CONFIG_DS4510_RST defines add additional sub-commands to the ds4510 command when defined. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>master
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/*
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* Copyright 2008 Extreme Engineering Solutions, Inc. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License |
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* Version 2 as published by the Free Software Foundation. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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|
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/*
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* Driver for DS4510, a CPU supervisor with integrated EEPROM, SRAM, |
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* and 4 programmable non-volatile GPIO pins. |
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*/ |
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#include <common.h> |
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#include <i2c.h> |
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#include <command.h> |
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#include <ds4510.h> |
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/* Default to an address that hopefully won't corrupt other i2c devices */ |
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#ifndef CONFIG_SYS_I2C_DS4510_ADDR |
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#define CONFIG_SYS_I2C_DS4510_ADDR (~0) |
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#endif |
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enum { |
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DS4510_CMD_INFO, |
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DS4510_CMD_DEVICE, |
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DS4510_CMD_NV, |
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DS4510_CMD_RSTDELAY, |
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DS4510_CMD_OUTPUT, |
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DS4510_CMD_INPUT, |
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DS4510_CMD_PULLUP, |
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DS4510_CMD_EEPROM, |
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DS4510_CMD_SEEPROM, |
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DS4510_CMD_SRAM, |
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}; |
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/*
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* Write to DS4510, taking page boundaries into account |
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*/ |
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int ds4510_mem_write(uint8_t chip, int offset, uint8_t *buf, int count) |
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{ |
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int wrlen; |
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int i = 0; |
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do { |
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wrlen = DS4510_EEPROM_PAGE_SIZE - |
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DS4510_EEPROM_PAGE_OFFSET(offset); |
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if (count < wrlen) |
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wrlen = count; |
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if (i2c_write(chip, offset, 1, &buf[i], wrlen)) |
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return -1; |
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/*
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* This delay isn't needed for SRAM writes but shouldn't delay |
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* things too much, so do it unconditionally for simplicity |
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*/ |
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udelay(DS4510_EEPROM_PAGE_WRITE_DELAY_MS * 1000); |
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count -= wrlen; |
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offset += wrlen; |
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i += wrlen; |
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} while (count > 0); |
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return 0; |
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} |
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/*
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* General read from DS4510 |
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*/ |
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int ds4510_mem_read(uint8_t chip, int offset, uint8_t *buf, int count) |
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{ |
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return i2c_read(chip, offset, 1, buf, count); |
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} |
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/*
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* Write SEE bit in config register. |
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* nv = 0 - Writes to SEEPROM registers behave like EEPROM |
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* nv = 1 - Writes to SEEPROM registers behave like SRAM |
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*/ |
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int ds4510_see_write(uint8_t chip, uint8_t nv) |
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{ |
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uint8_t data; |
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if (i2c_read(chip, DS4510_CFG, 1, &data, 1)) |
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return -1; |
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if (nv) /* Treat SEEPROM bits as EEPROM */ |
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data &= ~DS4510_CFG_SEE; |
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else /* Treat SEEPROM bits as SRAM */ |
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data |= DS4510_CFG_SEE; |
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return ds4510_mem_write(chip, DS4510_CFG, &data, 1); |
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} |
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/*
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* Write de-assertion of reset signal delay |
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*/ |
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int ds4510_rstdelay_write(uint8_t chip, uint8_t delay) |
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{ |
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uint8_t data; |
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if (i2c_read(chip, DS4510_RSTDELAY, 1, &data, 1)) |
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return -1; |
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data &= ~DS4510_RSTDELAY_MASK; |
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data |= delay & DS4510_RSTDELAY_MASK; |
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return ds4510_mem_write(chip, DS4510_RSTDELAY, &data, 1); |
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} |
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/*
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* Write pullup characteristics of IO pins |
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*/ |
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int ds4510_pullup_write(uint8_t chip, uint8_t val) |
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{ |
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val &= DS4510_IO_MASK; |
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return ds4510_mem_write(chip, DS4510_PULLUP, (uint8_t *)&val, 1); |
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} |
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/*
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* Read pullup characteristics of IO pins |
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*/ |
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int ds4510_pullup_read(uint8_t chip) |
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{ |
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uint8_t val; |
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if (i2c_read(chip, DS4510_PULLUP, 1, &val, 1)) |
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return -1; |
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return val & DS4510_IO_MASK; |
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} |
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/*
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* Write drive level of IO pins |
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*/ |
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int ds4510_gpio_write(uint8_t chip, uint8_t val) |
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{ |
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uint8_t data; |
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int i; |
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for (i = 0; i < DS4510_NUM_IO; i++) { |
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if (i2c_read(chip, DS4510_IO0 - i, 1, &data, 1)) |
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return -1; |
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if (val & (0x1 << i)) |
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data |= 0x1; |
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else |
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data &= ~0x1; |
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if (ds4510_mem_write(chip, DS4510_IO0 - i, &data, 1)) |
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return -1; |
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} |
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return 0; |
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} |
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/*
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* Read drive level of IO pins |
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*/ |
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int ds4510_gpio_read(uint8_t chip) |
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{ |
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uint8_t data; |
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int val = 0; |
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int i; |
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for (i = 0; i < DS4510_NUM_IO; i++) { |
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if (i2c_read(chip, DS4510_IO0 - i, 1, &data, 1)) |
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return -1; |
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if (data & 1) |
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val |= (1 << i); |
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} |
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return val; |
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} |
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/*
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* Read physical level of IO pins |
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*/ |
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int ds4510_gpio_read_val(uint8_t chip) |
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{ |
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uint8_t val; |
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if (i2c_read(chip, DS4510_IO_STATUS, 1, &val, 1)) |
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return -1; |
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return val & DS4510_IO_MASK; |
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} |
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#ifdef CONFIG_CMD_DS4510 |
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#ifdef CONFIG_CMD_DS4510_INFO |
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/*
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* Display DS4510 information |
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*/ |
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static int ds4510_info(uint8_t chip) |
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{ |
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int i; |
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int tmp; |
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uint8_t data; |
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printf("DS4510 @ 0x%x:\n\n", chip); |
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if (i2c_read(chip, DS4510_RSTDELAY, 1, &data, 1)) |
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return -1; |
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printf("rstdelay = 0x%x\n\n", data & DS4510_RSTDELAY_MASK); |
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if (i2c_read(chip, DS4510_CFG, 1, &data, 1)) |
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return -1; |
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printf("config = 0x%x\n", data); |
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printf(" /ready = %d\n", data & DS4510_CFG_READY ? 1 : 0); |
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printf(" trip pt = %d\n", data & DS4510_CFG_TRIP_POINT ? 1 : 0); |
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printf(" rst sts = %d\n", data & DS4510_CFG_RESET ? 1 : 0); |
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printf(" /see = %d\n", data & DS4510_CFG_SEE ? 1 : 0); |
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printf(" swrst = %d\n\n", data & DS4510_CFG_SWRST ? 1 : 0); |
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printf("gpio pins: 3210\n"); |
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printf("---------------\n"); |
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printf("pullup "); |
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tmp = ds4510_pullup_read(chip); |
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if (tmp == -1) |
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return tmp; |
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for (i = DS4510_NUM_IO - 1; i >= 0; i--) |
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printf("%d", (tmp & (1 << i)) ? 1 : 0); |
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printf("\n"); |
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printf("driven "); |
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tmp = ds4510_gpio_read(chip); |
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if (tmp == -1) |
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return -1; |
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for (i = DS4510_NUM_IO - 1; i >= 0; i--) |
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printf("%d", (tmp & (1 << i)) ? 1 : 0); |
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printf("\n"); |
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printf("read "); |
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tmp = ds4510_gpio_read_val(chip); |
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if (tmp == -1) |
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return -1; |
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for (i = DS4510_NUM_IO - 1; i >= 0; i--) |
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printf("%d", (tmp & (1 << i)) ? 1 : 0); |
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printf("\n"); |
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return 0; |
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} |
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#endif /* CONFIG_CMD_DS4510_INFO */ |
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cmd_tbl_t cmd_ds4510[] = { |
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U_BOOT_CMD_MKENT(device, 3, 0, (void *)DS4510_CMD_DEVICE, "", ""), |
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U_BOOT_CMD_MKENT(nv, 3, 0, (void *)DS4510_CMD_NV, "", ""), |
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U_BOOT_CMD_MKENT(output, 4, 0, (void *)DS4510_CMD_OUTPUT, "", ""), |
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U_BOOT_CMD_MKENT(input, 3, 0, (void *)DS4510_CMD_INPUT, "", ""), |
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U_BOOT_CMD_MKENT(pullup, 4, 0, (void *)DS4510_CMD_PULLUP, "", ""), |
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#ifdef CONFIG_CMD_DS4510_INFO |
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U_BOOT_CMD_MKENT(info, 2, 0, (void *)DS4510_CMD_INFO, "", ""), |
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#endif |
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#ifdef CONFIG_CMD_DS4510_RST |
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U_BOOT_CMD_MKENT(rstdelay, 3, 0, (void *)DS4510_CMD_RSTDELAY, "", ""), |
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#endif |
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#ifdef CONFIG_CMD_DS4510_MEM |
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U_BOOT_CMD_MKENT(eeprom, 6, 0, (void *)DS4510_CMD_EEPROM, "", ""), |
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U_BOOT_CMD_MKENT(seeprom, 6, 0, (void *)DS4510_CMD_SEEPROM, "", ""), |
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U_BOOT_CMD_MKENT(sram, 6, 0, (void *)DS4510_CMD_SRAM, "", ""), |
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#endif |
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}; |
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int do_ds4510(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) |
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{ |
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static uint8_t chip = CONFIG_SYS_I2C_DS4510_ADDR; |
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cmd_tbl_t *c; |
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ulong ul_arg2 = 0; |
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ulong ul_arg3 = 0; |
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int tmp; |
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#ifdef CONFIG_CMD_DS4510_MEM |
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ulong addr; |
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ulong off; |
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ulong cnt; |
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int end; |
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int (*rw_func)(uint8_t, int, uint8_t *, int); |
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#endif |
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c = find_cmd_tbl(argv[1], cmd_ds4510, ARRAY_SIZE(cmd_ds4510)); |
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/* All commands but "device" require 'maxargs' arguments */ |
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if (!c || !((argc == (c->maxargs)) || |
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(((int)c->cmd == DS4510_CMD_DEVICE) && |
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(argc == (c->maxargs - 1))))) { |
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printf("Usage:\n%s\n", cmdtp->usage); |
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return 1; |
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} |
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/* arg2 used as chip addr and pin number */ |
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if (argc > 2) |
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ul_arg2 = simple_strtoul(argv[2], NULL, 16); |
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/* arg3 used as output/pullup value */ |
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if (argc > 3) |
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ul_arg3 = simple_strtoul(argv[3], NULL, 16); |
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switch ((int)c->cmd) { |
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case DS4510_CMD_DEVICE: |
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if (argc == 3) |
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chip = ul_arg2; |
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printf("Current device address: 0x%x\n", chip); |
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return 0; |
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case DS4510_CMD_NV: |
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return ds4510_see_write(chip, ul_arg2); |
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case DS4510_CMD_OUTPUT: |
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tmp = ds4510_gpio_read(chip); |
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if (tmp == -1) |
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return -1; |
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if (ul_arg3) |
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tmp |= (1 << ul_arg2); |
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else |
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tmp &= ~(1 << ul_arg2); |
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return ds4510_gpio_write(chip, tmp); |
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case DS4510_CMD_INPUT: |
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tmp = ds4510_gpio_read_val(chip); |
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if (tmp == -1) |
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return -1; |
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return (tmp & (1 << ul_arg2)) != 0; |
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case DS4510_CMD_PULLUP: |
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tmp = ds4510_pullup_read(chip); |
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if (tmp == -1) |
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return -1; |
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if (ul_arg3) |
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tmp |= (1 << ul_arg2); |
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else |
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tmp &= ~(1 << ul_arg2); |
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return ds4510_pullup_write(chip, tmp); |
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#ifdef CONFIG_CMD_DS4510_INFO |
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case DS4510_CMD_INFO: |
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return ds4510_info(chip); |
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#endif |
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#ifdef CONFIG_CMD_DS4510_RST |
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case DS4510_CMD_RSTDELAY: |
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return ds4510_rstdelay_write(chip, ul_arg2); |
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#endif |
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#ifdef CONFIG_CMD_DS4510_MEM |
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case DS4510_CMD_EEPROM: |
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end = DS4510_EEPROM + DS4510_EEPROM_SIZE; |
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off = DS4510_EEPROM; |
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break; |
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case DS4510_CMD_SEEPROM: |
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end = DS4510_SEEPROM + DS4510_SEEPROM_SIZE; |
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off = DS4510_SEEPROM; |
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break; |
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case DS4510_CMD_SRAM: |
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end = DS4510_SRAM + DS4510_SRAM_SIZE; |
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off = DS4510_SRAM; |
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break; |
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#endif |
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default: |
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/* We should never get here... */ |
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return 1; |
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} |
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#ifdef CONFIG_CMD_DS4510_MEM |
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/* Only eeprom, seeprom, and sram commands should make it here */ |
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if (strcmp(argv[2], "read") == 0) { |
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rw_func = ds4510_mem_read; |
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} else if (strcmp(argv[2], "write") == 0) { |
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rw_func = ds4510_mem_write; |
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} else { |
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printf("Usage:\n%s\n", cmdtp->usage); |
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return 1; |
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} |
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addr = simple_strtoul(argv[3], NULL, 16); |
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off += simple_strtoul(argv[4], NULL, 16); |
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cnt = simple_strtoul(argv[5], NULL, 16); |
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if ((off + cnt) > end) { |
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printf("ERROR: invalid len\n"); |
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return -1; |
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} |
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return rw_func(chip, off, (uint8_t *)addr, cnt); |
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#endif |
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} |
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U_BOOT_CMD( |
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ds4510, 6, 1, do_ds4510, |
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"ds4510 - ds4510 eeprom/seeprom/sram/gpio access\n", |
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"device [dev]\n" |
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" - show or set current device address\n" |
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#ifdef CONFIG_CMD_DS4510_INFO |
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"ds4510 info\n" |
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" - display ds4510 info\n" |
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#endif |
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"ds4510 output pin 0|1\n" |
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" - set pin low or high-Z\n" |
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"ds4510 input pin\n" |
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" - read value of pin\n" |
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"ds4510 pullup pin 0|1\n" |
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" - disable/enable pullup on specified pin\n" |
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"ds4510 nv 0|1\n" |
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" - make gpio and seeprom writes volatile/non-volatile\n" |
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#ifdef CONFIG_CMD_DS4510_RST |
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"ds4510 rstdelay 0-3\n" |
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" - set reset output delay\n" |
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#endif |
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#ifdef CONFIG_CMD_DS4510_MEM |
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"ds4510 eeprom read addr off cnt\n" |
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"ds4510 eeprom write addr off cnt\n" |
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" - read/write 'cnt' bytes at EEPROM offset 'off'\n" |
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"ds4510 seeprom read addr off cnt\n" |
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"ds4510 seeprom write addr off cnt\n" |
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" - read/write 'cnt' bytes at SRAM-shadowed EEPROM offset 'off'\n" |
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"ds4510 sram read addr off cnt\n" |
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"ds4510 sram write addr off cnt\n" |
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" - read/write 'cnt' bytes at SRAM offset 'off'\n" |
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#endif |
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); |
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#endif /* CONFIG_CMD_DS4510 */ |
@ -0,0 +1,75 @@ |
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/*
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* Copyright 2008 Extreme Engineering Solutions, Inc. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License |
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* Version 2 as published by the Free Software Foundation. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#ifndef __DS4510_H_ |
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#define __DS4510_H_ |
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/* General defines */ |
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#define DS4510_NUM_IO 0x04 |
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#define DS4510_IO_MASK ((1 << DS4510_NUM_IO) - 1) |
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#define DS4510_EEPROM_PAGE_WRITE_DELAY_MS 20 |
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/* EEPROM from 0x00 - 0x39 */ |
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#define DS4510_EEPROM 0x00 |
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#define DS4510_EEPROM_SIZE 0x40 |
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#define DS4510_EEPROM_PAGE_SIZE 0x08 |
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#define DS4510_EEPROM_PAGE_OFFSET(x) ((x) & (DS4510_EEPROM_PAGE_SIZE - 1)) |
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/* SEEPROM from 0xf0 - 0xf7 */ |
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#define DS4510_SEEPROM 0xf0 |
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#define DS4510_SEEPROM_SIZE 0x08 |
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/* Registers overlapping SEEPROM from 0xf0 - 0xf7 */ |
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#define DS4510_PULLUP 0xF0 |
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#define DS4510_PULLUP_DIS 0x00 |
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#define DS4510_PULLUP_EN 0x01 |
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#define DS4510_RSTDELAY 0xF1 |
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#define DS4510_RSTDELAY_MASK 0x03 |
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#define DS4510_RSTDELAY_125 0x00 |
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#define DS4510_RSTDELAY_250 0x01 |
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#define DS4510_RSTDELAY_500 0x02 |
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#define DS4510_RSTDELAY_1000 0x03 |
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#define DS4510_IO3 0xF4 |
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#define DS4510_IO2 0xF5 |
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#define DS4510_IO1 0xF6 |
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#define DS4510_IO0 0xF7 |
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/* Status configuration registers from 0xf8 - 0xf9*/ |
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#define DS4510_IO_STATUS 0xF8 |
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#define DS4510_CFG 0xF9 |
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#define DS4510_CFG_READY 0x80 |
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#define DS4510_CFG_TRIP_POINT 0x40 |
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#define DS4510_CFG_RESET 0x20 |
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#define DS4510_CFG_SEE 0x10 |
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#define DS4510_CFG_SWRST 0x08 |
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/* SRAM from 0xfa - 0xff */ |
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#define DS4510_SRAM 0xfa |
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#define DS4510_SRAM_SIZE 0x06 |
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int ds4510_mem_write(uint8_t chip, int offset, uint8_t *buf, int count); |
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int ds4510_mem_read(uint8_t chip, int offset, uint8_t *buf, int count); |
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int ds4510_see_write(uint8_t chip, uint8_t nv); |
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int ds4510_rstdelay_write(uint8_t chip, uint8_t delay); |
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int ds4510_pullup_write(uint8_t chip, uint8_t val); |
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int ds4510_pullup_read(uint8_t chip); |
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int ds4510_gpio_write(uint8_t chip, uint8_t val); |
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int ds4510_gpio_read(uint8_t chip); |
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int ds4510_gpio_read_val(uint8_t chip); |
||||
|
||||
#endif /* __DS4510_H_ */ |
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Reference in new issue