- creating SoC subdir for Atmel AT91RM9200 cpu/arm920t/at91rm9200 - moving code out of cpu/at91rm9200 into cpu/arm920t/at91rm9200master
wdenk
20 years ago
parent
20787e23b8
commit
a85f9f21aa
@ -1,27 +0,0 @@ |
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#
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# (C) Copyright 2002
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# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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# Marius Groeger <mgroeger@sysgo.de>
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \
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-mshort-load-bytes -msoft-float
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PLATFORM_CPPFLAGS += -mapcs-32 -march=armv4 -mtune=arm7tdmi
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@ -1,200 +0,0 @@ |
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/*
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* (C) Copyright 2002 |
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
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* Marius Groeger <mgroeger@sysgo.de> |
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* |
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* (C) Copyright 2002 |
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
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* Alex Zuepke <azu@sysgo.de> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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/*
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* CPU specific code |
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*/ |
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#include <common.h> |
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#include <command.h> |
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#include <asm/io.h> |
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#include <asm/arch/hardware.h> |
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#if !defined(CONFIG_DBGU) && !defined(CONFIG_USART0) && !defined(CONFIG_USART1) |
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#error must define one of CONFIG_DBGU or CONFIG_USART0 or CONFIG_USART1 |
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#endif |
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/* read co-processor 15, register #1 (control register) */ |
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static unsigned long read_p15_c1(void) |
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{ |
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unsigned long value; |
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__asm__ __volatile__( |
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"mrc p15, 0, %0, c1, c0, 0 @ read control reg\n" |
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: "=r" (value) |
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: |
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: "memory"); |
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/*printf("p15/c1 is = %08lx\n", value); */ |
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return value; |
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} |
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/* write to co-processor 15, register #1 (control register) */ |
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static void write_p15_c1(unsigned long value) |
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{ |
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/*printf("write %08lx to p15/c1\n", value); */ |
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__asm__ __volatile__( |
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"mcr p15, 0, %0, c1, c0, 0 @ write it back\n" |
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: "=r" (value) |
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: |
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: "memory"); |
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read_p15_c1(); |
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} |
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static void cp_delay(void) |
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{ |
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volatile int i; |
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/* copro seems to need some delay between reading and writing */ |
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for (i=0; i<100; i++); |
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} |
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/* See also ARM Ref. Man. */ |
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#define C1_MMU (1<<0) /* mmu off/on */ |
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#define C1_ALIGN (1<<1) /* alignment faults off/on */ |
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#define C1_IDC (1<<2) /* icache and/or dcache off/on */ |
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#define C1_WRITE_BUFFER (1<<3) /* write buffer off/on */ |
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#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */ |
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#define C1_SYS_PROT (1<<8) /* system protection */ |
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#define C1_ROM_PROT (1<<9) /* ROM protection */ |
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#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */ |
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int cpu_init(void) |
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{ |
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/*
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* setup up stacks if necessary |
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*/ |
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#ifdef CONFIG_USE_IRQ |
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DECLARE_GLOBAL_DATA_PTR; |
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IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4; |
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FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ; |
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#endif |
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return 0; |
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} |
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int cleanup_before_linux(void) |
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{ |
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/*
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* this function is called just before we call linux |
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* it prepares the processor for linux |
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* |
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* we turn off caches etc ... |
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* and we set the CPU-speed to 73 MHz - see start.S for details |
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*/ |
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disable_interrupts(); |
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return 0; |
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} |
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int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) |
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{ |
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#ifdef CFG_SOFT_RESET |
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disable_interrupts(); |
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reset_cpu(0); |
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#else |
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#ifdef CONFIG_DBGU |
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AT91PS_USART us = (AT91PS_USART) AT91C_BASE_DBGU; |
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#endif |
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#ifdef CONFIG_USART0 |
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AT91PS_USART us = AT91C_BASE_US0; |
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#endif |
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#ifdef CONFIG_USART1 |
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AT91PS_USART us = AT91C_BASE_US1; |
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#endif |
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AT91PS_PIO pio = AT91C_BASE_PIOA; |
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/*shutdown the console to avoid strange chars during reset */ |
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us->US_CR = (AT91C_US_RSTRX | AT91C_US_RSTTX); |
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#ifdef CONFIG_AT91RM9200DK |
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/* Clear PA19 to trigger the hard reset */ |
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pio->PIO_CODR = 0x00080000; |
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pio->PIO_OER = 0x00080000; |
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pio->PIO_PER = 0x00080000; |
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#endif |
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#ifdef CONFIG_CMC_PU2 |
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/* this is the way Linux does it */ |
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#define AT91C_ST_RSTEN (0x1 << 16) |
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#define AT91C_ST_EXTEN (0x1 << 17) |
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#define AT91C_ST_WDRST (0x1 << 0) |
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/* watchdog mode register */ |
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#define ST_WDMR *((unsigned long *)0xfffffd08) |
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/* system clock control register */ |
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#define ST_CR *((unsigned long *)0xfffffd00) |
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ST_WDMR = AT91C_ST_RSTEN | AT91C_ST_EXTEN | 1 ; |
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ST_CR = AT91C_ST_WDRST; |
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/* Never reached */ |
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#endif |
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#endif |
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return 0; |
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} |
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void icache_enable(void) |
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{ |
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ulong reg; |
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reg = read_p15_c1(); |
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cp_delay(); |
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write_p15_c1(reg | C1_IDC); |
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} |
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void icache_disable(void) |
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{ |
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ulong reg; |
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reg = read_p15_c1(); |
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cp_delay(); |
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write_p15_c1(reg & ~C1_IDC); |
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} |
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int icache_status(void) |
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{ |
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return (read_p15_c1() & C1_IDC) != 0; |
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return 0; |
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} |
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void dcache_enable(void) |
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{ |
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ulong reg; |
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reg = read_p15_c1(); |
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cp_delay(); |
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write_p15_c1(reg | C1_IDC); |
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} |
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void dcache_disable(void) |
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{ |
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ulong reg; |
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reg = read_p15_c1(); |
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cp_delay(); |
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write_p15_c1(reg & ~C1_IDC); |
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} |
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int dcache_status(void) |
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{ |
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return (read_p15_c1() & C1_IDC) != 0; |
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return 0; |
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} |
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@ -1,391 +0,0 @@ |
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/* |
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* armboot - Startup Code for ARM720 CPU-core |
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* |
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* Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
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* Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include "config.h" |
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#include "version.h" |
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/* |
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************************************************************************* |
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* |
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* Jump vector table as in table 3.1 in [1] |
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* |
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************************************************************************* |
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*/ |
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.globl _start
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_start: b reset |
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ldr pc, _undefined_instruction |
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ldr pc, _software_interrupt |
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ldr pc, _prefetch_abort |
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ldr pc, _data_abort |
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ldr pc, _not_used |
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ldr pc, _irq |
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ldr pc, _fiq |
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_undefined_instruction: .word undefined_instruction |
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_software_interrupt: .word software_interrupt |
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_prefetch_abort: .word prefetch_abort |
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_data_abort: .word data_abort |
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_not_used: .word not_used |
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_irq: .word irq |
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_fiq: .word fiq |
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.balignl 16,0xdeadbeef |
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/* |
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************************************************************************* |
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* |
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* Startup Code (reset vector) |
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* |
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* do important init only if we don't start from memory! |
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* relocate armboot to ram |
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* setup stack |
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* jump to second stage |
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* |
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************************************************************************* |
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*/ |
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_TEXT_BASE: |
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.word TEXT_BASE
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.globl _armboot_start
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_armboot_start: |
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.word _start
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/* |
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* These are defined in the board-specific linker script. |
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*/ |
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.globl _bss_start
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_bss_start: |
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.word __bss_start
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.globl _bss_end
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_bss_end: |
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.word _end
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#ifdef CONFIG_USE_IRQ |
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/* IRQ stack memory (calculated at run-time) */ |
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.globl IRQ_STACK_START
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IRQ_STACK_START: |
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.word 0x0badc0de
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/* IRQ stack memory (calculated at run-time) */ |
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.globl FIQ_STACK_START
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FIQ_STACK_START: |
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.word 0x0badc0de
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#endif |
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/* |
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* the actual reset code |
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*/ |
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reset: |
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/* |
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* set the cpu to SVC32 mode |
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*/ |
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mrs r0,cpsr |
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bic r0,r0,#0x1f |
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orr r0,r0,#0xd3 /* was 13 */ |
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msr cpsr,r0 |
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT |
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/* scratch stack */ |
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/**** ldr r1, =0x00204000 ****/ |
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/* Insure word alignment */ |
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/**** bic r1, r1, #3 ****/ |
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/* Init stack SYS */ |
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/**** mov sp, r1 ****/ |
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/* |
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* This does a lot more than just set up the memory, which |
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* is why it's called lowlevel_init |
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*/ |
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bl lowlevel_init /* in lowlevel.S */ |
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/* |
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* Read/modify/write CP15 control register |
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* disable MMU, enable I-Cache, select Asychronous Clocking Mode |
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*/ |
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mrc p15, 0, r0, c1, c0, 0 @ read cp15 control register (cp15 r1) in r0
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bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
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bic r0, r0, #0x0000008f @ clear bits 7, 3:0 (B--- WCAM)
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orr r0, r0, #0x00000002 @ set bit 2 (A) Align
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orr r0, r0, #0x00000004 @ set bit 3 (C) D-Cache
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orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
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orr r0, r0, #0xC0000000 @ set bits 31:30 (iA, nF)
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mcr p15, 0, r0, c1, c0, 0 @ write r0 in cp15 control register (cp15 r1)
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#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ |
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/* |
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* relocate exeception table |
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*/ |
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ldr r0, =_start |
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ldr r1, =0x0 |
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mov r2, #16 |
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copyex: |
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subs r2, r2, #1 |
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ldr r3, [r0], #4 |
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str r3, [r1], #4 |
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bne copyex |
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/* |
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* we do sys-critical inits only at reboot, |
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* not when booting from ram! |
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*/ |
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT |
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bl cpu_init_crit |
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#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ |
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#ifndef CONFIG_SKIP_RELOCATE_UBOOT |
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relocate: /* relocate U-Boot to RAM */ |
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adr r0, _start /* r0 <- current position of code */ |
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ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ |
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cmp r0, r1 /* don't reloc during debug */ |
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beq stack_setup |
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ldr r2, _armboot_start |
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ldr r3, _bss_start |
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sub r2, r3, r2 /* r2 <- size of armboot */ |
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add r2, r0, r2 /* r2 <- source end address */ |
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copy_loop: |
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ldmia r0!, {r3-r10} /* copy from source address [r0] */ |
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stmia r1!, {r3-r10} /* copy to target address [r1] */ |
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cmp r0, r2 /* until source end addreee [r2] */ |
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ble copy_loop |
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#endif /* CONFIG_SKIP_RELOCATE_UBOOT */ |
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/* Set up the stack */ |
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stack_setup: |
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ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ |
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sub r0, r0, #CFG_MALLOC_LEN /* malloc area */ |
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sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ |
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#ifdef CONFIG_USE_IRQ |
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sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) |
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#endif |
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sub sp, r0, #12 /* leave 3 words for abort-stack */ |
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clear_bss: |
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ldr r0, _bss_start /* find start of bss segment */ |
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ldr r1, _bss_end /* stop here */ |
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mov r2, #0x00000000 /* clear */ |
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clbss_l:str r2, [r0] /* clear loop... */ |
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add r0, r0, #4 |
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cmp r0, r1 |
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ble clbss_l |
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ldr pc,_start_armboot |
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_start_armboot: .word start_armboot |
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/* |
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************************************************************************* |
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* |
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* CPU_init_critical registers |
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* |
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************************************************************************* |
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*/ |
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cpu_init_crit: |
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/* do nothing for now */ |
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mov pc, lr |
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/* |
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************************************************************************* |
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* |
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* Interrupt handling |
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* |
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************************************************************************* |
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*/ |
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@
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@ IRQ stack frame.
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@
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#define S_FRAME_SIZE 72 |
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#define S_OLD_R0 68 |
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#define S_PSR 64 |
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#define S_PC 60 |
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#define S_LR 56 |
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#define S_SP 52 |
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#define S_IP 48 |
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#define S_FP 44 |
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#define S_R10 40 |
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#define S_R9 36 |
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#define S_R8 32 |
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#define S_R7 28 |
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#define S_R6 24 |
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#define S_R5 20 |
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#define S_R4 16 |
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#define S_R3 12 |
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#define S_R2 8 |
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#define S_R1 4 |
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#define S_R0 0 |
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#define MODE_SVC 0x13 |
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#define I_BIT 0x80 |
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/* |
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* use bad_save_user_regs for abort/prefetch/undef/swi ... |
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* use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling |
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*/ |
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.macro bad_save_user_regs
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sub sp, sp, #S_FRAME_SIZE |
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stmia sp, {r0 - r12} @ Calling r0-r12
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add r8, sp, #S_PC |
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ldr r2, _armboot_start |
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sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) |
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sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
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ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0
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add r0, sp, #S_FRAME_SIZE @ restore sp_SVC |
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add r5, sp, #S_SP |
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mov r1, lr |
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stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r
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mov r0, sp |
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.endm |
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.macro irq_save_user_regs
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sub sp, sp, #S_FRAME_SIZE |
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stmia sp, {r0 - r12} @ Calling r0-r12
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add r8, sp, #S_PC |
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stmdb r8, {sp, lr}^ @ Calling SP, LR
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str lr, [r8, #0] @ Save calling PC
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mrs r6, spsr |
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str r6, [r8, #4] @ Save CPSR
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str r0, [r8, #8] @ Save OLD_R0
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mov r0, sp |
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.endm |
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.macro irq_restore_user_regs
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ldmia sp, {r0 - lr}^ @ Calling r0 - lr
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mov r0, r0 |
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ldr lr, [sp, #S_PC] @ Get PC |
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add sp, sp, #S_FRAME_SIZE |
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subs pc, lr, #4 @ return & move spsr_svc into cpsr
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.endm |
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.macro get_bad_stack
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ldr r13, _armboot_start @ setup our mode stack
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sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) |
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sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
|
||||
|
||||
str lr, [r13] @ save caller lr / spsr
|
||||
mrs lr, spsr |
||||
str lr, [r13, #4] |
||||
|
||||
mov r13, #MODE_SVC @ prepare SVC-Mode |
||||
msr spsr_c, r13 |
||||
mov lr, pc |
||||
movs pc, lr |
||||
.endm |
||||
|
||||
.macro get_irq_stack @ setup IRQ stack
|
||||
ldr sp, IRQ_STACK_START |
||||
.endm |
||||
|
||||
.macro get_fiq_stack @ setup FIQ stack
|
||||
ldr sp, FIQ_STACK_START |
||||
.endm |
||||
|
||||
/* |
||||
* exception handlers |
||||
*/ |
||||
.align 5
|
||||
undefined_instruction: |
||||
get_bad_stack |
||||
bad_save_user_regs |
||||
bl do_undefined_instruction |
||||
|
||||
.align 5
|
||||
software_interrupt: |
||||
get_bad_stack |
||||
bad_save_user_regs |
||||
bl do_software_interrupt |
||||
|
||||
.align 5
|
||||
prefetch_abort: |
||||
get_bad_stack |
||||
bad_save_user_regs |
||||
bl do_prefetch_abort |
||||
|
||||
.align 5
|
||||
data_abort: |
||||
get_bad_stack |
||||
bad_save_user_regs |
||||
bl do_data_abort |
||||
|
||||
.align 5
|
||||
not_used: |
||||
get_bad_stack |
||||
bad_save_user_regs |
||||
bl do_not_used |
||||
|
||||
#ifdef CONFIG_USE_IRQ |
||||
|
||||
.align 5
|
||||
irq: |
||||
get_irq_stack |
||||
irq_save_user_regs |
||||
bl do_irq |
||||
irq_restore_user_regs |
||||
|
||||
.align 5
|
||||
fiq: |
||||
get_fiq_stack |
||||
/* someone ought to write a more effiction fiq_save_user_regs */ |
||||
irq_save_user_regs |
||||
bl do_fiq |
||||
irq_restore_user_regs |
||||
|
||||
#else |
||||
|
||||
.align 5
|
||||
irq: |
||||
get_bad_stack |
||||
bad_save_user_regs |
||||
bl do_irq |
||||
|
||||
.align 5
|
||||
fiq: |
||||
get_bad_stack |
||||
bad_save_user_regs |
||||
bl do_fiq |
||||
|
||||
#endif |
||||
|
||||
.align 5
|
||||
.globl reset_cpu
|
||||
reset_cpu: |
||||
mov pc, r0 |
||||
Loading…
Reference in new issue