Signed-off-by: Peter Howard <phoward@gme.net.au> [trini: Add config file, update for ..._ether_addr() -> ..._ethaddr() rename] Signed-off-by: Tom Rini <trini@konsulko.com>master
Peter Howard
10 years ago
committed by
Tom Rini
parent
a8eeaf2f7a
commit
a868e44333
@ -0,0 +1,28 @@ |
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Summary |
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======= |
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This README assumes you have read README.da850. It contains some additional |
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information specific to building the omapl138-lcdk. The AIS file as generated |
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by the build is, currently, not useable due to differences in the flash |
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available on this board, as compared to the da850evm boards. |
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|
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Flash Differences |
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================= |
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Refer to the discussion in [1] for more detail - basically the da850evm uses |
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SPI flash whereas the lcdk uses NAND flash to store the bootloader, and |
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the support isn't there in the SPL code. |
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|
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It should be possible to add the support in the SPL code should someone be |
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sufficiently motivated. |
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|
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Using the built image |
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===================== |
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The output image to use is u-boot.bin. This needs to be converted to an |
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AIS file as described in [1] and then flashed using the utitilty linked to |
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there and also described in README.da850. You _may_ be able to write using |
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u-boot itself, but the commands in README.da850 won't work as they write to |
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SPI rather than NAND. |
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|
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Links |
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===== |
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[1] |
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http://e2e.ti.com/support/dsp/omap_applications_processors/f/42/t/386829 |
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@ -0,0 +1,383 @@ |
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/*
|
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* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
|
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* |
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* Based on da850evm.c. Original Copyrights follow: |
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* |
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* Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com> |
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* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation; either version 2 of the License, or |
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* (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
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*/ |
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|
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#include <common.h> |
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#include <i2c.h> |
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#include <net.h> |
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#include <netdev.h> |
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#include <spi.h> |
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#include <spi_flash.h> |
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#include <asm/arch/hardware.h> |
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#include <asm/ti-common/davinci_nand.h> |
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#include <asm/io.h> |
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#include <asm/errno.h> |
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#include <asm/arch/davinci_misc.h> |
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#ifdef CONFIG_DAVINCI_MMC |
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#include <mmc.h> |
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#include <asm/arch/sdmmc_defs.h> |
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#endif |
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|
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DECLARE_GLOBAL_DATA_PTR; |
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#define pinmux(x) (&davinci_syscfg_regs->pinmux[x]) |
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#ifdef CONFIG_DAVINCI_MMC |
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/* MMC0 pin muxer settings */ |
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const struct pinmux_config mmc0_pins[] = { |
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/* GP0[11] is required for SD to work on Rev 3 EVMs */ |
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{ pinmux(0), 8, 4 }, /* GP0[11] */ |
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{ pinmux(10), 2, 0 }, /* MMCSD0_CLK */ |
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{ pinmux(10), 2, 1 }, /* MMCSD0_CMD */ |
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{ pinmux(10), 2, 2 }, /* MMCSD0_DAT_0 */ |
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{ pinmux(10), 2, 3 }, /* MMCSD0_DAT_1 */ |
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{ pinmux(10), 2, 4 }, /* MMCSD0_DAT_2 */ |
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{ pinmux(10), 2, 5 }, /* MMCSD0_DAT_3 */ |
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/* LCDK supports only 4-bit mode, remaining pins are not configured */ |
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}; |
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#endif |
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|
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/* UART pin muxer settings */ |
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static const struct pinmux_config uart_pins[] = { |
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{ pinmux(0), 4, 6 }, |
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{ pinmux(0), 4, 7 }, |
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{ pinmux(4), 2, 4 }, |
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{ pinmux(4), 2, 5 } |
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}; |
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|
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#ifdef CONFIG_DRIVER_TI_EMAC |
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static const struct pinmux_config emac_pins[] = { |
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{ pinmux(2), 8, 1 }, |
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{ pinmux(2), 8, 2 }, |
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{ pinmux(2), 8, 3 }, |
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{ pinmux(2), 8, 4 }, |
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{ pinmux(2), 8, 5 }, |
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{ pinmux(2), 8, 6 }, |
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{ pinmux(2), 8, 7 }, |
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{ pinmux(3), 8, 0 }, |
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{ pinmux(3), 8, 1 }, |
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{ pinmux(3), 8, 2 }, |
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{ pinmux(3), 8, 3 }, |
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{ pinmux(3), 8, 4 }, |
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{ pinmux(3), 8, 5 }, |
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{ pinmux(3), 8, 6 }, |
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{ pinmux(3), 8, 7 }, |
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{ pinmux(4), 8, 0 }, |
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{ pinmux(4), 8, 1 } |
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}; |
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#endif /* CONFIG_DRIVER_TI_EMAC */ |
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|
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/* I2C pin muxer settings */ |
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static const struct pinmux_config i2c_pins[] = { |
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{ pinmux(4), 2, 2 }, |
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{ pinmux(4), 2, 3 } |
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}; |
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|
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#ifdef CONFIG_NAND_DAVINCI |
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const struct pinmux_config nand_pins[] = { |
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{ pinmux(7), 1, 1 }, |
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{ pinmux(7), 1, 2 }, |
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{ pinmux(7), 1, 4 }, |
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{ pinmux(7), 1, 5 }, |
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{ pinmux(8), 1, 0 }, |
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{ pinmux(8), 1, 1 }, |
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{ pinmux(8), 1, 2 }, |
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{ pinmux(8), 1, 3 }, |
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{ pinmux(8), 1, 4 }, |
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{ pinmux(8), 1, 5 }, |
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{ pinmux(8), 1, 6 }, |
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{ pinmux(8), 1, 7 }, |
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{ pinmux(9), 1, 0 }, |
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{ pinmux(9), 1, 1 }, |
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{ pinmux(9), 1, 2 }, |
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{ pinmux(9), 1, 3 }, |
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{ pinmux(9), 1, 4 }, |
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{ pinmux(9), 1, 5 }, |
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{ pinmux(9), 1, 6 }, |
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{ pinmux(9), 1, 7 }, |
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{ pinmux(12), 1, 5 }, |
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{ pinmux(12), 1, 6 } |
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}; |
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#endif |
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#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII |
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#define HAS_RMII 1 |
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#else |
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#define HAS_RMII 0 |
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#endif |
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const struct pinmux_resource pinmuxes[] = { |
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PINMUX_ITEM(uart_pins), |
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PINMUX_ITEM(i2c_pins), |
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#ifdef CONFIG_NAND_DAVINCI |
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PINMUX_ITEM(nand_pins), |
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#endif |
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}; |
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const int pinmuxes_size = ARRAY_SIZE(pinmuxes); |
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const struct lpsc_resource lpsc[] = { |
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{ DAVINCI_LPSC_AEMIF }, /* NAND, NOR */ |
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{ DAVINCI_LPSC_SPI1 }, /* Serial Flash */ |
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{ DAVINCI_LPSC_EMAC }, /* image download */ |
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{ DAVINCI_LPSC_UART2 }, /* console */ |
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{ DAVINCI_LPSC_GPIO }, |
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#ifdef CONFIG_DAVINCI_MMC |
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{ DAVINCI_LPSC_MMC_SD }, |
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#endif |
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}; |
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const int lpsc_size = ARRAY_SIZE(lpsc); |
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|
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#ifndef CONFIG_DA850_EVM_MAX_CPU_CLK |
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#define CONFIG_DA850_EVM_MAX_CPU_CLK 456000000 |
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#endif |
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|
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/*
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* get_board_rev() - setup to pass kernel board revision information |
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* Returns: |
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* bit[0-3] Maximum cpu clock rate supported by onboard SoC |
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* 0000b - 300 MHz |
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* 0001b - 372 MHz |
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* 0010b - 408 MHz |
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* 0011b - 456 MHz |
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*/ |
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u32 get_board_rev(void) |
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{ |
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return 0; |
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} |
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|
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int board_early_init_f(void) |
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{ |
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/*
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* Power on required peripherals |
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* ARM does not have access by default to PSC0 and PSC1 |
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* assuming here that the DSP bootloader has set the IOPU |
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* such that PSC access is available to ARM |
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*/ |
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if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc))) |
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return 1; |
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return 0; |
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} |
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int board_init(void) |
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{ |
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#ifndef CONFIG_USE_IRQ |
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irq_init(); |
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#endif |
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|
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/* arch number of the board */ |
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gd->bd->bi_arch_number = MACH_TYPE_OMAPL138_LCDK; |
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|
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/* address of boot parameters */ |
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gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; |
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|
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/* setup the SUSPSRC for ARM to control emulation suspend */ |
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writel(readl(&davinci_syscfg_regs->suspsrc) & |
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~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C | |
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DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 | |
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DAVINCI_SYSCFG_SUSPSRC_UART2), |
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&davinci_syscfg_regs->suspsrc); |
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/* configure pinmux settings */ |
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if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes))) |
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return 1; |
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#ifdef CONFIG_NAND_DAVINCI |
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/*
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* NAND CS setup - cycle counts based on da850evm NAND timings in the |
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* Linux kernel @ 25MHz EMIFA |
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*/ |
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writel((DAVINCI_ABCR_WSETUP(15) | |
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DAVINCI_ABCR_WSTROBE(63) | |
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DAVINCI_ABCR_WHOLD(7) | |
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DAVINCI_ABCR_RSETUP(15) | |
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DAVINCI_ABCR_RSTROBE(63) | |
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DAVINCI_ABCR_RHOLD(7) | |
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DAVINCI_ABCR_TA(3) | |
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DAVINCI_ABCR_ASIZE_16BIT), |
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&davinci_emif_regs->ab2cr); /* CS3 */ |
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#endif |
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#ifdef CONFIG_DAVINCI_MMC |
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if (davinci_configure_pin_mux(mmc0_pins, ARRAY_SIZE(mmc0_pins)) != 0) |
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return 1; |
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#endif |
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#ifdef CONFIG_DRIVER_TI_EMAC |
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if (davinci_configure_pin_mux(emac_pins, ARRAY_SIZE(emac_pins)) != 0) |
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return 1; |
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davinci_emac_mii_mode_sel(HAS_RMII); |
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#endif /* CONFIG_DRIVER_TI_EMAC */ |
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|
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/* enable the console UART */ |
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writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST | |
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DAVINCI_UART_PWREMU_MGMT_UTRST), |
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&davinci_uart2_ctrl_regs->pwremu_mgmt); |
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return 0; |
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} |
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#ifdef CONFIG_DRIVER_TI_EMAC |
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/*
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* Initializes on-board ethernet controllers. |
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*/ |
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int board_eth_init(bd_t *bis) |
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{ |
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if (!davinci_emac_initialize()) { |
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printf("Error: Ethernet init failed!\n"); |
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return -1; |
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} |
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return 0; |
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} |
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#endif /* CONFIG_DRIVER_TI_EMAC */ |
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#define CFG_MAC_ADDR_SPI_BUS 0 |
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#define CFG_MAC_ADDR_SPI_CS 0 |
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#define CFG_MAC_ADDR_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED |
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#define CFG_MAC_ADDR_SPI_MODE SPI_MODE_3 |
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#define CFG_MAC_ADDR_OFFSET (flash->size - SZ_64K) |
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static int get_mac_addr(u8 *addr) |
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{ |
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/* Need to find a way to get MAC ADDRESS */ |
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return 0; |
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} |
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void dsp_lpsc_on(unsigned domain, unsigned int id) |
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{ |
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dv_reg_p mdstat, mdctl, ptstat, ptcmd; |
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struct davinci_psc_regs *psc_regs; |
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psc_regs = davinci_psc0_regs; |
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mdstat = &psc_regs->psc0.mdstat[id]; |
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mdctl = &psc_regs->psc0.mdctl[id]; |
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ptstat = &psc_regs->ptstat; |
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ptcmd = &psc_regs->ptcmd; |
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while (*ptstat & (0x1 << domain)) |
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; |
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if ((*mdstat & 0x1f) == 0x03) |
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return; /* Already on and enabled */ |
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*mdctl |= 0x03; |
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*ptcmd = 0x1 << domain; |
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while (*ptstat & (0x1 << domain)) |
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; |
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while ((*mdstat & 0x1f) != 0x03) |
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; /* Probably an overkill... */ |
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} |
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static void dspwake(void) |
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{ |
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unsigned *resetvect = (unsigned *)DAVINCI_L3CBARAM_BASE; |
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/* if the device is ARM only, return */ |
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if ((REG(CHIP_REV_ID_REG) & 0x3f) == 0x10) |
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return; |
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if (!strcmp(getenv("dspwake"), "no")) |
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return; |
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*resetvect++ = 0x1E000; /* DSP Idle */ |
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/* clear out the next 10 words as NOP */ |
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memset(resetvect, 0, sizeof(unsigned) * 10); |
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/* setup the DSP reset vector */ |
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REG(HOST1CFG) = DAVINCI_L3CBARAM_BASE; |
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dsp_lpsc_on(1, DAVINCI_LPSC_GEM); |
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REG(PSC0_MDCTL + (15 * 4)) |= 0x100; |
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} |
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#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII |
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/**
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* rmii_hw_init |
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* |
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*/ |
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int rmii_hw_init(void) |
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{ |
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return 0; |
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} |
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#endif /* CONFIG_DRIVER_TI_EMAC_USE_RMII */ |
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int misc_init_r(void) |
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{ |
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uint8_t tmp[20], addr[10]; |
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if (getenv("ethaddr") == NULL) { |
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/* Read Ethernet MAC address from EEPROM */ |
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if (dvevm_read_mac_address(addr)) { |
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/* Set Ethernet MAC address from EEPROM */ |
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davinci_sync_env_enetaddr(addr); |
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} else { |
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get_mac_addr(addr); |
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} |
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if (is_multicast_ethaddr(addr) || is_zero_ethaddr(addr)) { |
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printf("Invalid MAC address read.\n"); |
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return -EINVAL; |
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} |
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sprintf((char *)tmp, "%02x:%02x:%02x:%02x:%02x:%02x", addr[0], |
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addr[1], addr[2], addr[3], addr[4], addr[5]); |
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setenv("ethaddr", (char *)tmp); |
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} |
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#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII |
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/* Select RMII fucntion through the expander */ |
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if (rmii_hw_init()) |
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printf("RMII hardware init failed!!!\n"); |
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#endif |
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dspwake(); |
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return 0; |
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} |
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|
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#ifdef CONFIG_DAVINCI_MMC |
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static struct davinci_mmc mmc_sd0 = { |
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.reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE, |
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.host_caps = MMC_MODE_4BIT, /* DA850 supports only 4-bit SD/MMC */ |
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.voltages = MMC_VDD_32_33 | MMC_VDD_33_34, |
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.version = MMC_CTLR_VERSION_2, |
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}; |
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|
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int board_mmc_init(bd_t *bis) |
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{ |
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mmc_sd0.input_clk = clk_get(DAVINCI_MMCSD_CLKID); |
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|
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/* Add slot-0 to mmc subsystem */ |
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return davinci_mmc_init(bis, &mmc_sd0); |
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} |
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#endif |
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@ -0,0 +1,3 @@ |
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CONFIG_ARM=y |
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CONFIG_ARCH_DAVINCI=y |
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CONFIG_TARGET_OMAPL138_LCDK=y |
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@ -0,0 +1,330 @@ |
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/*
|
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* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
|
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* |
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* Based on davinci_dvevm.h. Original Copyrights follow: |
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* |
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* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation; either version 2 of the License, or |
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* (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
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*/ |
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|
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#ifndef __CONFIG_H |
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#define __CONFIG_H |
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|
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/*
|
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* Board |
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*/ |
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#define CONFIG_DRIVER_TI_EMAC |
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#undef CONFIG_USE_SPIFLASH |
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#undef CONFIG_SYS_USE_NOR |
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#define CONFIG_USE_NAND |
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|
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/*
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* SoC Configuration |
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*/ |
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#define CONFIG_MACH_OMAPL138_LCDK |
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#define CONFIG_ARM926EJS /* arm926ejs CPU core */ |
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#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */ |
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#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) |
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#define CONFIG_SYS_OSCIN_FREQ 24000000 |
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#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE |
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#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) |
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#define CONFIG_SYS_HZ 1000 |
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#define CONFIG_SKIP_LOWLEVEL_INIT |
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#define CONFIG_SYS_TEXT_BASE 0xc1080000 |
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|
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/*
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* Memory Info |
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*/ |
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#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ |
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#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ |
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#define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */ |
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#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ |
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|
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/* memtest start addr */ |
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#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000) |
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|
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/* memtest will be run on 16MB */ |
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#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024) |
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|
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#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ |
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#define CONFIG_STACKSIZE (256*1024) /* regular stack */ |
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|
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#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ |
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DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
|
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DAVINCI_SYSCFG_SUSPSRC_SPI1 | \
|
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DAVINCI_SYSCFG_SUSPSRC_UART2 | \
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DAVINCI_SYSCFG_SUSPSRC_EMAC | \
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DAVINCI_SYSCFG_SUSPSRC_I2C) |
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|
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/*
|
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* PLL configuration |
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*/ |
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#define CONFIG_SYS_DV_CLKMODE 0 |
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#define CONFIG_SYS_DA850_PLL0_POSTDIV 1 |
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#define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000 |
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#define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001 |
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#define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002 |
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#define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003 |
||||
#define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002 |
||||
#define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1 |
||||
#define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005 |
||||
|
||||
#define CONFIG_SYS_DA850_PLL1_POSTDIV 1 |
||||
#define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000 |
||||
#define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001 |
||||
#define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8003 |
||||
|
||||
#define CONFIG_SYS_DA850_PLL0_PLLM 24 |
||||
#define CONFIG_SYS_DA850_PLL1_PLLM 21 |
||||
|
||||
/*
|
||||
* Serial Driver info |
||||
*/ |
||||
#define CONFIG_SYS_NS16550 |
||||
#define CONFIG_SYS_NS16550_SERIAL |
||||
#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */ |
||||
#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */ |
||||
#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) |
||||
#define CONFIG_CONS_INDEX 1 /* use UART0 for console */ |
||||
#define CONFIG_BAUDRATE 115200 /* Default baud rate */ |
||||
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
||||
|
||||
#define CONFIG_SPI |
||||
#define CONFIG_SPI_FLASH |
||||
#define CONFIG_SPI_FLASH_STMICRO |
||||
#define CONFIG_SPI_FLASH_WINBOND |
||||
#define CONFIG_DAVINCI_SPI |
||||
#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE |
||||
#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID) |
||||
#define CONFIG_SF_DEFAULT_SPEED 30000000 |
||||
#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED |
||||
|
||||
#ifdef CONFIG_USE_SPIFLASH |
||||
#define CONFIG_SPL_SPI_SUPPORT |
||||
#define CONFIG_SPL_SPI_FLASH_SUPPORT |
||||
#define CONFIG_SPL_SPI_LOAD |
||||
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000 |
||||
#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x30000 |
||||
#endif |
||||
|
||||
/*
|
||||
* I2C Configuration |
||||
*/ |
||||
#define CONFIG_SYS_I2C |
||||
#define CONFIG_SYS_I2C_DAVINCI |
||||
#define CONFIG_SYS_DAVINCI_I2C_SPEED 25000 |
||||
#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ |
||||
#define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20 |
||||
|
||||
/*
|
||||
* Flash & Environment |
||||
*/ |
||||
#ifdef CONFIG_USE_NAND |
||||
#undef CONFIG_ENV_IS_IN_FLASH |
||||
#define CONFIG_NAND_DAVINCI |
||||
#define CONFIG_SYS_NO_FLASH |
||||
#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ |
||||
#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ |
||||
#define CONFIG_ENV_SIZE (128 << 9) |
||||
#define CONFIG_SYS_NAND_USE_FLASH_BBT |
||||
#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST |
||||
#define CONFIG_SYS_NAND_PAGE_2K |
||||
#define CONFIG_SYS_NAND_BUSWIDTH_16_BIT |
||||
#define CONFIG_SYS_NAND_CS 3 |
||||
#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE |
||||
#define CONFIG_SYS_CLE_MASK 0x10 |
||||
#define CONFIG_SYS_ALE_MASK 0x8 |
||||
#undef CONFIG_SYS_NAND_HW_ECC |
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ |
||||
#define NAND_MAX_CHIPS 1 |
||||
#endif |
||||
|
||||
#ifdef CONFIG_SYS_USE_NOR |
||||
#define CONFIG_ENV_IS_IN_FLASH |
||||
#undef CONFIG_SYS_NO_FLASH |
||||
#define CONFIG_FLASH_CFI_DRIVER |
||||
#define CONFIG_SYS_FLASH_CFI |
||||
#define CONFIG_SYS_FLASH_PROTECTION |
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */ |
||||
#define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */ |
||||
#define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ * 3) |
||||
#define CONFIG_ENV_SIZE (128 << 10) |
||||
#define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE |
||||
#define PHYS_FLASH_SIZE (8 << 20) /* Flash size 8MB */ |
||||
#define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\ |
||||
+ 3) |
||||
#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ |
||||
#endif |
||||
|
||||
#ifdef CONFIG_USE_SPIFLASH |
||||
#undef CONFIG_ENV_IS_IN_FLASH |
||||
#undef CONFIG_ENV_IS_IN_NAND |
||||
#define CONFIG_ENV_IS_IN_SPI_FLASH |
||||
#define CONFIG_ENV_SIZE (64 << 10) |
||||
#define CONFIG_ENV_OFFSET (256 << 10) |
||||
#define CONFIG_ENV_SECT_SIZE (64 << 10) |
||||
#define CONFIG_SYS_NO_FLASH |
||||
#endif |
||||
|
||||
/*
|
||||
* Network & Ethernet Configuration |
||||
*/ |
||||
#ifdef CONFIG_DRIVER_TI_EMAC |
||||
#define CONFIG_EMAC_MDIO_PHY_NUM 7 |
||||
#define CONFIG_MII |
||||
#undef CONFIG_DRIVER_TI_EMAC_USE_RMII |
||||
#define CONFIG_BOOTP_DEFAULT |
||||
#define CONFIG_BOOTP_DNS |
||||
#define CONFIG_BOOTP_DNS2 |
||||
#define CONFIG_BOOTP_SEND_HOSTNAME |
||||
#define CONFIG_NET_RETRY_COUNT 10 |
||||
#define CONFIG_NET_MULTI |
||||
#endif |
||||
|
||||
/*
|
||||
* U-Boot general configuration |
||||
*/ |
||||
#define CONFIG_SYS_GENERIC_BOARD |
||||
#define CONFIG_MISC_INIT_R |
||||
#define CONFIG_BOARD_EARLY_INIT_F |
||||
#define CONFIG_BOOTFILE "uImage" /* Boot file name */ |
||||
#define CONFIG_SYS_PROMPT "U-Boot > " /* Command Prompt */ |
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) |
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ |
||||
#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) |
||||
#define CONFIG_VERSION_VARIABLE |
||||
#define CONFIG_AUTO_COMPLETE |
||||
#define CONFIG_SYS_HUSH_PARSER |
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " |
||||
#define CONFIG_CMDLINE_EDITING |
||||
#define CONFIG_SYS_LONGHELP |
||||
#define CONFIG_CRC32_VERIFY |
||||
#define CONFIG_MX_CYCLIC |
||||
#define CONFIG_OF_LIBFDT |
||||
|
||||
/*
|
||||
* Linux Information |
||||
*/ |
||||
#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) |
||||
#define CONFIG_CMDLINE_TAG |
||||
#define CONFIG_REVISION_TAG |
||||
#define CONFIG_SETUP_MEMORY_TAGS |
||||
#define CONFIG_BOOTARGS "console=ttyS2,115200n8 root=/dev/mmcblk0p2 rw rootwait ip=off" |
||||
#define CONFIG_BOOTCOMMAND "if mmc rescan 0; then if fatload mmc 0 0xc0600000 boot.scr; then source 0xc0600000; else fatload mmc 0 0xc0700000 uImage; bootm c0700000; fi; else sf probe 0; sf read 0xc0700000 0x80000 0x220000; bootm 0xc0700000; fi" |
||||
#define CONFIG_BOOTDELAY 3 |
||||
|
||||
/*
|
||||
* U-Boot commands |
||||
*/ |
||||
#include <config_cmd_default.h> |
||||
#define CONFIG_CMD_ENV |
||||
#define CONFIG_CMD_ASKENV |
||||
#define CONFIG_CMD_DHCP |
||||
#define CONFIG_CMD_DIAG |
||||
#define CONFIG_CMD_MII |
||||
#define CONFIG_CMD_PING |
||||
#define CONFIG_CMD_SAVES |
||||
#define CONFIG_CMD_MEMORY |
||||
#ifdef CONFIG_CMD_BDI |
||||
#define CONFIG_CLOCKS |
||||
#endif |
||||
|
||||
#ifndef CONFIG_DRIVER_TI_EMAC |
||||
#undef CONFIG_CMD_NET |
||||
#undef CONFIG_CMD_DHCP |
||||
#undef CONFIG_CMD_MII |
||||
#undef CONFIG_CMD_PING |
||||
#endif |
||||
|
||||
#ifdef CONFIG_USE_NAND |
||||
#undef CONFIG_CMD_FLASH |
||||
#undef CONFIG_CMD_IMLS |
||||
#define CONFIG_CMD_NAND |
||||
|
||||
#define CONFIG_CMD_MTDPARTS |
||||
#define CONFIG_MTD_DEVICE |
||||
#define CONFIG_MTD_PARTITIONS |
||||
#define CONFIG_LZO |
||||
#define CONFIG_RBTREE |
||||
#define CONFIG_CMD_UBI |
||||
#define CONFIG_CMD_UBIFS |
||||
#endif |
||||
|
||||
#ifdef CONFIG_USE_SPIFLASH |
||||
#undef CONFIG_CMD_IMLS |
||||
#undef CONFIG_CMD_FLASH |
||||
#define CONFIG_CMD_SPI |
||||
#define CONFIG_CMD_SF |
||||
#define CONFIG_CMD_SAVEENV |
||||
#endif |
||||
|
||||
#if !defined(CONFIG_USE_NAND) && \ |
||||
!defined(CONFIG_SYS_USE_NOR) && \
|
||||
!defined(CONFIG_USE_SPIFLASH) |
||||
#define CONFIG_ENV_IS_NOWHERE |
||||
#define CONFIG_SYS_NO_FLASH |
||||
#define CONFIG_ENV_SIZE (16 << 10) |
||||
#undef CONFIG_CMD_IMLS |
||||
#undef CONFIG_CMD_ENV |
||||
#endif |
||||
|
||||
/* SD/MMC */ |
||||
#define CONFIG_MMC |
||||
#define CONFIG_GENERIC_MMC |
||||
#define CONFIG_DAVINCI_MMC |
||||
|
||||
#ifdef CONFIG_MMC |
||||
#define CONFIG_DOS_PARTITION |
||||
#define CONFIG_CMD_EXT2 |
||||
#define CONFIG_CMD_FAT |
||||
#define CONFIG_CMD_MMC |
||||
#undef CONFIG_ENV_IS_IN_MMC |
||||
#endif |
||||
|
||||
#ifdef CONFIG_ENV_IS_IN_MMC |
||||
#undef CONFIG_ENV_SIZE |
||||
#undef CONFIG_ENV_OFFSET |
||||
#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ |
||||
#define CONFIG_ENV_OFFSET (51 << 9) /* Sector 51 */ |
||||
#undef CONFIG_ENV_IS_IN_FLASH |
||||
#undef CONFIG_ENV_IS_IN_NAND |
||||
#undef CONFIG_ENV_IS_IN_SPI_FLASH |
||||
#endif |
||||
|
||||
#ifndef CONFIG_DIRECT_NOR_BOOT |
||||
/* defines for SPL */ |
||||
#define CONFIG_SPL_FRAMEWORK |
||||
#define CONFIG_SPL_BOARD_INIT |
||||
#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \ |
||||
CONFIG_SYS_MALLOC_LEN) |
||||
#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN |
||||
#define CONFIG_SPL_SERIAL_SUPPORT |
||||
#define CONFIG_SPL_LIBCOMMON_SUPPORT |
||||
#define CONFIG_SPL_LIBGENERIC_SUPPORT |
||||
#define CONFIG_SPL_LDSCRIPT "board/$(BOARDDIR)/u-boot-spl-da850evm.lds" |
||||
#define CONFIG_SPL_STACK 0x8001ff00 |
||||
#define CONFIG_SPL_TEXT_BASE 0x80000000 |
||||
#define CONFIG_SPL_MAX_FOOTPRINT 32768 |
||||
#define CONFIG_SPL_PAD_TO 32768 |
||||
#endif |
||||
|
||||
/* additions for new relocation code, must added to all boards */ |
||||
#define CONFIG_SYS_SDRAM_BASE 0xc0000000 |
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ |
||||
GENERATED_GBL_DATA_SIZE) |
||||
#endif /* __CONFIG_H */ |
||||
Loading…
Reference in new issue