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Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'

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Conflicts:
	include/micrel.h

The conflict above was trivial, caused by four lines being
added in both branches with different whitepace.
master
Albert ARIBAUD 11 years ago
parent 2931fa4db3 4611d5bab2
commit a891601ce5
64 changed files with 3439 additions and 3781 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
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  1. 12
      arch/arm/cpu/armv7/mx5/clock.c
  2. 23
      arch/arm/cpu/armv7/mx6/clock.c
  3. 110
      arch/arm/cpu/armv7/mx6/soc.c
  4. 3
      arch/arm/imx-common/Makefile
  5. 4
      arch/arm/imx-common/cpu.c
  6. 34
      arch/arm/imx-common/sata.c
  7. 1
      arch/arm/include/asm/arch-mx5/clock.h
  8. 3
      arch/arm/include/asm/arch-mx5/crm_regs.h
  9. 1
      arch/arm/include/asm/arch-mx6/crm_regs.h
  10. 23
      arch/arm/include/asm/arch-mx6/imx-regs.h
  11. 33
      arch/arm/include/asm/arch-mx6/mx6-pins.h
  12. 2728
      arch/arm/include/asm/arch-mx6/mx6dl_pins.h
  13. 2642
      arch/arm/include/asm/arch-mx6/mx6q_pins.h
  14. 2
      arch/arm/include/asm/arch-mx6/sys_proto.h
  15. 2
      arch/arm/include/asm/imx-common/iomux-v3.h
  16. 16
      arch/arm/include/asm/imx-common/sata.h
  17. 0
      board/barco/titanium/Makefile
  18. 0
      board/barco/titanium/imximage.cfg
  19. 110
      board/barco/titanium/titanium.c
  20. 197
      board/boundary/nitrogen6x/nitrogen6x.c
  21. 40
      board/congatec/cgtqmx6eval/cgtqmx6eval.c
  22. 73
      board/denx/m53evk/m53evk.c
  23. 2
      board/freescale/mx25pdk/mx25pdk.c
  24. 2
      board/freescale/mx31pdk/mx31pdk.c
  25. 2
      board/freescale/mx35pdk/mx35pdk.c
  26. 2
      board/freescale/mx51evk/mx51evk.c
  27. 2
      board/freescale/mx53evk/mx53evk.c
  28. 2
      board/freescale/mx53loco/mx53loco.c
  29. 68
      board/freescale/mx6qarm2/mx6qarm2.c
  30. 62
      board/freescale/mx6qsabreauto/mx6qsabreauto.c
  31. 155
      board/freescale/mx6sabresd/mx6sabresd.c
  32. 2
      board/genesi/mx51_efikamx/efikamx.c
  33. 55
      board/udoo/1066mhz_4x256mx16.cfg
  34. 32
      board/udoo/clocks.cfg
  35. 87
      board/udoo/ddr-setup.cfg
  36. 165
      board/udoo/udoo.c
  37. 29
      board/udoo/udoo.cfg
  38. 60
      board/wandboard/wandboard.c
  39. 4
      boards.cfg
  40. 76
      doc/README.imx6
  41. 4
      drivers/gpio/mxs_gpio.c
  42. 13
      drivers/misc/fsl_iim.c
  43. 177
      drivers/net/fec_mxc.c
  44. 3
      drivers/power/power_fsl.c
  45. 2
      include/configs/cgtqmx6eval.h
  46. 1
      include/configs/imx31_phycore.h
  47. 16
      include/configs/m53evk.h
  48. 2
      include/configs/mx25pdk.h
  49. 56
      include/configs/mx28evk.h
  50. 1
      include/configs/mx31pdk.h
  51. 2
      include/configs/mx35pdk.h
  52. 1
      include/configs/mx51evk.h
  53. 1
      include/configs/mx53ard.h
  54. 2
      include/configs/mx53evk.h
  55. 2
      include/configs/mx53loco.h
  56. 2
      include/configs/mx53smd.h
  57. 1
      include/configs/mx6_common.h
  58. 1
      include/configs/mx6qarm2.h
  59. 20
      include/configs/mx6sabre_common.h
  60. 13
      include/configs/nitrogen6x.h
  61. 1
      include/configs/titanium.h
  62. 31
      include/configs/udoo.h
  63. 3
      include/configs/wandboard.h
  64. 1
      tools/mxsimage.c

12
arch/arm/cpu/armv7/mx5/clock.c
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@ -749,6 +749,18 @@ void enable_nfc_clk(unsigned char enable)
MXC_CCM_CCGR5_EMI_ENFC(cg));
}
#ifdef CONFIG_FSL_IIM
void enable_efuse_prog_supply(bool enable)
{
if (enable)
setbits_le32(&mxc_ccm->cgpr,
MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE);
else
clrbits_le32(&mxc_ccm->cgpr,
MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE);
}
#endif
/* Config main_bus_clock for periphs */
static int config_periph_clk(u32 ref, u32 freq)
{

23
arch/arm/cpu/armv7/mx6/clock.c
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@ -94,7 +94,7 @@ static u32 decode_pll(enum pll_clocks pll, u32 infreq)
div = __raw_readl(&imx_ccm->analog_pll_enet);
div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
return (div == 3 ? 125000000 : 25000000 * (div << 1));
return 25000000 * (div + (div >> 1) + 1);
default:
return 0;
}
@ -310,7 +310,18 @@ static u32 get_mmdc_ch0_clk(void)
return freq / (podf + 1);
}
#else
static u32 get_mmdc_ch0_clk(void)
{
u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
u32 mmdc_ch0_podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
return get_periph_clk() / (mmdc_ch0_podf + 1);
}
#endif
#ifdef CONFIG_FEC_MXC
int enable_fec_anatop_clock(void)
{
u32 reg = 0;
@ -339,16 +350,6 @@ int enable_fec_anatop_clock(void)
return 0;
}
#else
static u32 get_mmdc_ch0_clk(void)
{
u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
u32 mmdc_ch0_podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
return get_periph_clk() / (mmdc_ch0_podf + 1);
}
#endif
static u32 get_usdhc_clk(u32 port)

110
arch/arm/cpu/armv7/mx6/soc.c
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@ -19,6 +19,14 @@
#include <asm/arch/mxc_hdmi.h>
#include <asm/arch/crm_regs.h>
#define VDDPU_MASK (0x1f << 9)
enum ldo_reg {
LDO_ARM,
LDO_SOC,
LDO_PU,
};
struct scu_regs {
u32 ctrl;
u32 config;
@ -93,6 +101,20 @@ void init_aips(void)
writel(0x00000000, &aips2->opacr4);
}
static void clear_ldo_ramp(void)
{
struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
int reg;
/* ROM may modify LDO ramp up time according to fuse setting, so in
* order to be in the safe side we neeed to reset these settings to
* match the reset value: 0'b00
*/
reg = readl(&anatop->ana_misc2);
reg &= ~(0x3f << 24);
writel(reg, &anatop->ana_misc2);
}
/*
* Set the VDDSOC
*
@ -101,10 +123,11 @@ void init_aips(void)
* Possible values are from 0.725V to 1.450V in steps of
* 0.025V (25mV).
*/
void set_vddsoc(u32 mv)
static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
{
struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
u32 val, reg = readl(&anatop->reg_core);
u32 val, step, old, reg = readl(&anatop->reg_core);
u8 shift;
if (mv < 725)
val = 0x00; /* Power gated off */
@ -113,12 +136,37 @@ void set_vddsoc(u32 mv)
else
val = (mv - 700) / 25;
clear_ldo_ramp();
switch (ldo) {
case LDO_SOC:
shift = 18;
break;
case LDO_PU:
shift = 9;
break;
case LDO_ARM:
shift = 0;
break;
default:
return -EINVAL;
}
old = (reg & (0x1F << shift)) >> shift;
step = abs(val - old);
if (step == 0)
return 0;
reg = (reg & ~(0x1F << shift)) | (val << shift);
writel(reg, &anatop->reg_core);
/*
* Mask out the REG_CORE[22:18] bits (REG2_TRIG)
* and set them to the calculated value (0.7V + val * 0.25V)
* The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
* step
*/
reg = (reg & ~(0x1F << 18)) | (val << 18);
writel(reg, &anatop->reg_core);
udelay(3 * step);
return 0;
}
static void imx_set_wdog_powerdown(bool enable)
@ -131,13 +179,50 @@ static void imx_set_wdog_powerdown(bool enable)
writew(enable, &wdog2->wmcr);
}
static void imx_set_vddpu_power_down(void)
{
struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
struct gpc_regs *gpc = (struct gpc_regs *)GPC_BASE_ADDR;
u32 reg;
/*
* Disable the brown out detection since we are going to be
* disabling the LDO.
*/
reg = readl(&anatop->ana_misc2);
reg &= ~ANADIG_ANA_MISC2_REG1_BO_EN;
writel(reg, &anatop->ana_misc2);
/* need to power down xPU in GPC before turning off PU LDO */
reg = readl(&gpc->gpu_ctrl);
writel(reg | 0x1, &gpc->gpu_ctrl);
reg = readl(&gpc->ctrl);
writel(reg | 0x1, &gpc->ctrl);
while (readl(&gpc->ctrl) & 0x1)
;
/* Mask the ANATOP brown out interrupt in the GPC. */
reg = readl(&gpc->imr4);
reg |= 0x80000000;
writel(reg, &gpc->imr4);
/* disable VDDPU */
writel(VDDPU_MASK, &anatop->reg_core_clr);
/* Clear the BO interrupt in the ANATOP. */
reg = readl(&anatop->ana_misc1);
reg |= 0x80000000;
writel(reg, &anatop->ana_misc1);
}
int arch_cpu_init(void)
{
init_aips();
set_vddsoc(1200); /* Set VDDSOC to 1.2V */
imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
imx_set_vddpu_power_down();
#ifdef CONFIG_APBH_DMA
/* Start APBH DMA */
@ -147,9 +232,18 @@ int arch_cpu_init(void)
return 0;
}
int board_postclk_init(void)
{
set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
return 0;
}
#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
{
/* Avoid random hang when download by usb */
invalidate_dcache_all();
/* Enable D-cache. I-cache is already enabled in start.S */
dcache_enable();
}

3
arch/arm/imx-common/Makefile
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@ -17,6 +17,9 @@ endif
ifeq ($(SOC),$(filter $(SOC),mx6 mxs))
obj-y += misc.o
endif
ifeq ($(SOC),$(filter $(SOC),mx6))
obj-$(CONFIG_CMD_SATA) += sata.o
endif
obj-$(CONFIG_CMD_BMODE) += cmd_bmode.o
obj-$(CONFIG_CMD_HDMIDETECT) += cmd_hdmidet.o

4
arch/arm/imx-common/cpu.c
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@ -51,9 +51,9 @@ char *get_reset_cause(void)
#if defined(CONFIG_MX53) || defined(CONFIG_MX6)
#if defined(CONFIG_MX53)
#define MEMCTL_BASE ESDCTL_BASE_ADDR;
#define MEMCTL_BASE ESDCTL_BASE_ADDR
#else
#define MEMCTL_BASE MMDC_P0_BASE_ADDR;
#define MEMCTL_BASE MMDC_P0_BASE_ADDR
#endif
static const unsigned char col_lookup[] = {9, 10, 11, 8, 12, 9, 9, 9};
static const unsigned char bank_lookup[] = {3, 2};

34
arch/arm/imx-common/sata.c
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@ -0,0 +1,34 @@
/*
* Copyright 2011 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/imx-common/iomux-v3.h>
#include <asm/arch/iomux.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
int setup_sata(void)
{
struct iomuxc_base_regs *const iomuxc_regs
= (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR;
int ret = enable_sata_clock();
if (ret)
return ret;
clrsetbits_le32(&iomuxc_regs->gpr[13],
IOMUXC_GPR13_SATA_MASK,
IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
|IOMUXC_GPR13_SATA_PHY_7_SATA2M
|IOMUXC_GPR13_SATA_SPEED_3G
|(3<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
|IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
|IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16
|IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB
|IOMUXC_GPR13_SATA_PHY_2_TX_1P104V
|IOMUXC_GPR13_SATA_PHY_1_SLOW);
return 0;
}

1
arch/arm/include/asm/arch-mx5/clock.h
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@ -53,5 +53,6 @@ void enable_usboh3_clk(bool enable);
void mxc_set_sata_internal_clock(void);
int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
void enable_nfc_clk(unsigned char enable);
void enable_efuse_prog_supply(bool enable);
#endif /* __ASM_ARCH_CLOCK_H */

3
arch/arm/include/asm/arch-mx5/crm_regs.h
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@ -305,6 +305,9 @@ struct mxc_ccm_reg {
/* Define the bits in register CCDR */
#define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 17)
/* Define the bits in register CGPR */
#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4)
/* Define the bits in register CCGRx */
#define MXC_CCM_CCGR_CG_MASK 0x3
#define MXC_CCM_CCGR_CG_OFF 0x0

1
arch/arm/include/asm/arch-mx6/crm_regs.h
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@ -890,4 +890,5 @@ struct mxc_ccm_reg {
#define BF_ANADIG_PFD_528_PFD0_FRAC(v) \
(((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC)
#define ANADIG_ANA_MISC2_REG1_BO_EN (1 << 13)
#endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */

23
arch/arm/include/asm/arch-mx6/imx-regs.h
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@ -659,5 +659,28 @@ struct wdog_regs {
u16 wmcr; /* Miscellaneous Control */
};
struct gpc_regs {
u32 ctrl; /* 0x000 */
u32 pgr; /* 0x004 */
u32 imr1; /* 0x008 */
u32 imr2; /* 0x00c */
u32 imr3; /* 0x010 */
u32 imr4; /* 0x014 */
u32 isr1; /* 0x018 */
u32 isr2; /* 0x01c */
u32 isr3; /* 0x020 */
u32 isr4; /* 0x024 */
u32 reserved1[0x86];
u32 gpu_ctrl; /* 0x260 */
u32 gpu_pupscr; /* 0x264 */
u32 gpu_pdnscr; /* 0x268 */
u32 gpu_sr; /* 0x26c */
u32 reserved2[0xc];
u32 cpu_ctrl; /* 0x2a0 */
u32 cpu_pupscr; /* 0x2a4 */
u32 cpu_pdnscr; /* 0x2a8 */
u32 cpu_sr; /* 0x2ac */
};
#endif /* __ASSEMBLER__*/
#endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */

33
arch/arm/include/asm/arch-mx6/mx6-pins.h
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@ -6,18 +6,37 @@
#ifndef __ASM_ARCH_MX6_PINS_H__
#define __ASM_ARCH_MX6_PINS_H__
#ifdef CONFIG_MX6Q
#include <asm/imx-common/iomux-v3.h>
#define MX6_PAD_DECLARE(prefix, name, pco, mc, mm, sio, si, pc) \
prefix##name = IOMUX_PAD(pco, mc, mm, sio, si, pc)
#ifdef CONFIG_MX6QDL
enum {
#define MX6_PAD_DECL(name, pco, mc, mm, sio, si, pc) \
MX6_PAD_DECLARE(MX6Q_PAD_,name, pco, mc, mm, sio, si, pc),
#include "mx6q_pins.h"
#else
#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
#undef MX6_PAD_DECL
#define MX6_PAD_DECL(name, pco, mc, mm, sio, si, pc) \
MX6_PAD_DECLARE(MX6DL_PAD_,name, pco, mc, mm, sio, si, pc),
#include "mx6dl_pins.h"
#else
#if defined(CONFIG_MX6SL)
};
#elif defined(CONFIG_MX6Q)
enum {
#define MX6_PAD_DECL(name, pco, mc, mm, sio, si, pc) \
MX6_PAD_DECLARE(MX6_PAD_,name, pco, mc, mm, sio, si, pc),
#include "mx6q_pins.h"
};
#elif defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
enum {
#define MX6_PAD_DECL(name, pco, mc, mm, sio, si, pc) \
MX6_PAD_DECLARE(MX6_PAD_,name, pco, mc, mm, sio, si, pc),
#include "mx6dl_pins.h"
};
#elif defined(CONFIG_MX6SL)
#include "mx6sl_pins.h"
#else
#error "Please select cpu"
#endif /* CONFIG_MX6SL */
#endif /* CONFIG_MX6DL or CONFIG_MX6S */
#endif /* CONFIG_MX6Q */
#endif /*__ASM_ARCH_MX6_PINS_H__ */

2728
arch/arm/include/asm/arch-mx6/mx6dl_pins.h
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File diff suppressed because it is too large Load Diff

2642
arch/arm/include/asm/arch-mx6/mx6q_pins.h
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File diff suppressed because it is too large Load Diff

2
arch/arm/include/asm/arch-mx6/sys_proto.h
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@ -29,8 +29,6 @@ u32 get_cpu_rev(void);
const char *get_imx_type(u32 imxtype);
unsigned imx_ddr_size(void);
void set_vddsoc(u32 mv);
/*
* Initializes on-chip ethernet controllers.
* to override, implement board_eth_init()

2
arch/arm/include/asm/imx-common/iomux-v3.h
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@ -63,6 +63,8 @@ typedef u64 iomux_v3_cfg_t;
#define MUX_SEL_INPUT_SHIFT 59
#define MUX_SEL_INPUT_MASK ((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT)
#define MUX_MODE_SION ((iomux_v3_cfg_t)IOMUX_CONFIG_SION << \
MUX_MODE_SHIFT)
#define MUX_PAD_CTRL(x) ((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT)
#define IOMUX_PAD(pad_ctrl_ofs, mux_ctrl_ofs, mux_mode, sel_input_ofs, \

16
arch/arm/include/asm/imx-common/sata.h
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@ -0,0 +1,16 @@
/*
* Copyright 2011 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __IMX_SATA_H_
#define __IMX_SATA_H_
/*
* SATA setup for i.mx6 quad based platform
*/
int setup_sata(void);
#endif

0
board/freescale/titanium/Makefile → board/barco/titanium/Makefile
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0
board/freescale/titanium/imximage.cfg → board/barco/titanium/imximage.cfg
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110
board/freescale/titanium/titanium.c → board/barco/titanium/titanium.c
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@ -9,7 +9,7 @@
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6q_pins.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
@ -45,18 +45,18 @@ int dram_init(void)
}
iomux_v3_cfg_t const uart1_pads[] = {
MX6_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
};
iomux_v3_cfg_t const uart2_pads[] = {
MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
};
iomux_v3_cfg_t const uart4_pads[] = {
MX6_PAD_CSI0_DAT12__UART4_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_CSI0_DAT13__UART4_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_CSI0_DAT12__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_CSI0_DAT13__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
};
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
@ -64,12 +64,12 @@ iomux_v3_cfg_t const uart4_pads[] = {
struct i2c_pads_info i2c_pad_info0 = {
.scl = {
.i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC,
.gpio_mode = MX6_PAD_CSI0_DAT9__GPIO_5_27 | PC,
.gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC,
.gp = IMX_GPIO_NR(5, 27)
},
.sda = {
.i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC,
.gpio_mode = MX6_PAD_CSI0_DAT8__GPIO_5_26 | PC,
.gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC,
.gp = IMX_GPIO_NR(5, 26)
}
};
@ -77,81 +77,81 @@ struct i2c_pads_info i2c_pad_info0 = {
struct i2c_pads_info i2c_pad_info2 = {
.scl = {
.i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
.gpio_mode = MX6_PAD_GPIO_3__GPIO_1_3 | PC,
.gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC,
.gp = IMX_GPIO_NR(1, 3)
},
.sda = {
.i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC,
.gpio_mode = MX6_PAD_GPIO_16__GPIO_7_11 | PC,
.gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11 | PC,
.gp = IMX_GPIO_NR(7, 11)
}
};
iomux_v3_cfg_t const usdhc3_pads[] = {
MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT5__GPIO_7_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
};
iomux_v3_cfg_t const enet_pads1[] = {
MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
/* pin 35 - 1 (PHY_AD2) on reset */
MX6_PAD_RGMII_RXC__GPIO_6_30 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* pin 32 - 1 - (MODE0) all */
MX6_PAD_RGMII_RD0__GPIO_6_25 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* pin 31 - 1 - (MODE1) all */
MX6_PAD_RGMII_RD1__GPIO_6_27 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* pin 28 - 1 - (MODE2) all */
MX6_PAD_RGMII_RD2__GPIO_6_28 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* pin 27 - 1 - (MODE3) all */
MX6_PAD_RGMII_RD3__GPIO_6_29 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
MX6_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* pin 42 PHY nRST */
MX6_PAD_EIM_D23__GPIO_3_23 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
iomux_v3_cfg_t const enet_pads2[] = {
MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
};
iomux_v3_cfg_t nfc_pads[] = {
MX6_PAD_NANDF_CLE__RAWNAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_ALE__RAWNAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_WP_B__RAWNAND_RESETN | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_RB0__RAWNAND_READY0 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_CS0__RAWNAND_CE0N | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_CS1__RAWNAND_CE1N | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_CS2__RAWNAND_CE2N | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_CS3__RAWNAND_CE3N | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_SD4_CMD__RAWNAND_RDN | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_SD4_CLK__RAWNAND_WRN | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_D0__RAWNAND_D0 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_D1__RAWNAND_D1 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_D2__RAWNAND_D2 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_D3__RAWNAND_D3 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_D4__RAWNAND_D4 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_D5__RAWNAND_D5 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_D6__RAWNAND_D6 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_D7__RAWNAND_D7 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_SD4_DAT0__RAWNAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_CS1__NAND_CE1_B | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_CS2__NAND_CE2_B | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_CS3__NAND_CE3_B | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static void setup_gpmi_nand(void)
@ -272,7 +272,7 @@ int board_eth_init(bd_t *bis)
if (ret)
printf("FEC MXC: %s:failed\n", __func__);
return 0;
return ret;
}
int board_early_init_f(void)

197
board/boundary/nitrogen6x/nitrogen6x.c
Unescape View File

@ -17,6 +17,7 @@
#include <asm/gpio.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/mxc_i2c.h>
#include <asm/imx-common/sata.h>
#include <asm/imx-common/boot_mode.h>
#include <mmc.h>
#include <fsl_esdhc.h>
@ -71,13 +72,13 @@ int dram_init(void)
}
iomux_v3_cfg_t const uart1_pads[] = {
MX6_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
};
iomux_v3_cfg_t const uart2_pads[] = {
MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
};
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
@ -86,12 +87,12 @@ iomux_v3_cfg_t const uart2_pads[] = {
struct i2c_pads_info i2c_pad_info0 = {
.scl = {
.i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC,
.gpio_mode = MX6_PAD_EIM_D21__GPIO_3_21 | PC,
.gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC,
.gp = IMX_GPIO_NR(3, 21)
},
.sda = {
.i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC,
.gpio_mode = MX6_PAD_EIM_D28__GPIO_3_28 | PC,
.gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC,
.gp = IMX_GPIO_NR(3, 28)
}
};
@ -100,12 +101,12 @@ struct i2c_pads_info i2c_pad_info0 = {
struct i2c_pads_info i2c_pad_info1 = {
.scl = {
.i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
.gpio_mode = MX6_PAD_KEY_COL3__GPIO_4_12 | PC,
.gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
.gp = IMX_GPIO_NR(4, 12)
},
.sda = {
.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
.gpio_mode = MX6_PAD_KEY_ROW3__GPIO_4_13 | PC,
.gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
.gp = IMX_GPIO_NR(4, 13)
}
};
@ -114,87 +115,87 @@ struct i2c_pads_info i2c_pad_info1 = {
struct i2c_pads_info i2c_pad_info2 = {
.scl = {
.i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC,
.gpio_mode = MX6_PAD_GPIO_5__GPIO_1_5 | PC,
.gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | PC,
.gp = IMX_GPIO_NR(1, 5)
},
.sda = {
.i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC,
.gpio_mode = MX6_PAD_GPIO_16__GPIO_7_11 | PC,
.gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11 | PC,
.gp = IMX_GPIO_NR(7, 11)
}
};
iomux_v3_cfg_t const usdhc3_pads[] = {
MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT5__GPIO_7_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
};
iomux_v3_cfg_t const usdhc4_pads[] = {
MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NANDF_D6__GPIO_2_6 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
};
iomux_v3_cfg_t const enet_pads1[] = {
MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
/* pin 35 - 1 (PHY_AD2) on reset */
MX6_PAD_RGMII_RXC__GPIO_6_30 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* pin 32 - 1 - (MODE0) all */
MX6_PAD_RGMII_RD0__GPIO_6_25 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* pin 31 - 1 - (MODE1) all */
MX6_PAD_RGMII_RD1__GPIO_6_27 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* pin 28 - 1 - (MODE2) all */
MX6_PAD_RGMII_RD2__GPIO_6_28 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* pin 27 - 1 - (MODE3) all */
MX6_PAD_RGMII_RD3__GPIO_6_29 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
MX6_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* pin 42 PHY nRST */
MX6_PAD_EIM_D23__GPIO_3_23 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_ENET_RXD0__GPIO_1_27 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
iomux_v3_cfg_t const enet_pads2[] = {
MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
};
static iomux_v3_cfg_t const misc_pads[] = {
MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(WEAK_PULLUP),
MX6_PAD_KEY_COL4__USBOH3_USBOTG_OC | MUX_PAD_CTRL(WEAK_PULLUP),
MX6_PAD_EIM_D30__USBOH3_USBH1_OC | MUX_PAD_CTRL(WEAK_PULLUP),
MX6_PAD_KEY_COL4__USB_OTG_OC | MUX_PAD_CTRL(WEAK_PULLUP),
MX6_PAD_EIM_D30__USB_H1_OC | MUX_PAD_CTRL(WEAK_PULLUP),
/* OTG Power enable */
MX6_PAD_EIM_D22__GPIO_3_22 | MUX_PAD_CTRL(OUTPUT_40OHM),
MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(OUTPUT_40OHM),
};
/* wl1271 pads on nitrogen6x */
iomux_v3_cfg_t const wl12xx_pads[] = {
(MX6_PAD_NANDF_CS1__GPIO_6_14 & ~MUX_PAD_CTRL_MASK)
(MX6_PAD_NANDF_CS1__GPIO6_IO14 & ~MUX_PAD_CTRL_MASK)
| MUX_PAD_CTRL(WEAK_PULLDOWN),
(MX6_PAD_NANDF_CS2__GPIO_6_15 & ~MUX_PAD_CTRL_MASK)
(MX6_PAD_NANDF_CS2__GPIO6_IO15 & ~MUX_PAD_CTRL_MASK)
| MUX_PAD_CTRL(OUTPUT_40OHM),
(MX6_PAD_NANDF_CS3__GPIO_6_16 & ~MUX_PAD_CTRL_MASK)
(MX6_PAD_NANDF_CS3__GPIO6_IO16 & ~MUX_PAD_CTRL_MASK)
| MUX_PAD_CTRL(OUTPUT_40OHM),
};
#define WL12XX_WL_IRQ_GP IMX_GPIO_NR(6, 14)
@ -204,17 +205,17 @@ iomux_v3_cfg_t const wl12xx_pads[] = {
/* Button assignments for J14 */
static iomux_v3_cfg_t const button_pads[] = {
/* Menu */
MX6_PAD_NANDF_D1__GPIO_2_1 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
MX6_PAD_NANDF_D1__GPIO2_IO01 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
/* Back */
MX6_PAD_NANDF_D2__GPIO_2_2 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
/* Labelled Search (mapped to Power under Android) */
MX6_PAD_NANDF_D3__GPIO_2_3 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
MX6_PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
/* Home */
MX6_PAD_NANDF_D4__GPIO_2_4 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
/* Volume Down */
MX6_PAD_GPIO_19__GPIO_4_5 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
/* Volume Up */
MX6_PAD_GPIO_18__GPIO_7_13 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
};
static void setup_iomux_enet(void)
@ -238,7 +239,7 @@ static void setup_iomux_enet(void)
}
iomux_v3_cfg_t const usb_pads[] = {
MX6_PAD_GPIO_17__GPIO_7_12 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static void setup_iomux_uart(void)
@ -330,7 +331,7 @@ int board_mmc_init(bd_t *bis)
#ifdef CONFIG_MXC_SPI
iomux_v3_cfg_t const ecspi1_pads[] = {
/* SS1 */
MX6_PAD_EIM_D19__GPIO_3_19 | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
@ -401,74 +402,48 @@ static void setup_buttons(void)
ARRAY_SIZE(button_pads));
}
#ifdef CONFIG_CMD_SATA
int setup_sata(void)
{
struct iomuxc_base_regs *const iomuxc_regs
= (struct iomuxc_base_regs *) IOMUXC_BASE_ADDR;
int ret = enable_sata_clock();
if (ret)
return ret;
clrsetbits_le32(&iomuxc_regs->gpr[13],
IOMUXC_GPR13_SATA_MASK,
IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
|IOMUXC_GPR13_SATA_PHY_7_SATA2M
|IOMUXC_GPR13_SATA_SPEED_3G
|(3<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
|IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
|IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16
|IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB
|IOMUXC_GPR13_SATA_PHY_2_TX_1P104V
|IOMUXC_GPR13_SATA_PHY_1_SLOW);
return 0;
}
#endif
#if defined(CONFIG_VIDEO_IPUV3)
static iomux_v3_cfg_t const backlight_pads[] = {
/* Backlight on RGB connector: J15 */
MX6_PAD_SD1_DAT3__GPIO_1_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
#define RGB_BACKLIGHT_GP IMX_GPIO_NR(1, 21)
/* Backlight on LVDS connector: J6 */
MX6_PAD_SD1_CMD__GPIO_1_18 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
#define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 18)
};
static iomux_v3_cfg_t const rgb_pads[] = {
MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2,
MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3,
MX6_PAD_DI0_PIN4__GPIO_4_20,
MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02,
MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03,
MX6_PAD_DI0_PIN4__GPIO4_IO20,
MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18,
MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19,
MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20,
MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21,
MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22,
MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23,
};
struct display_info_t {

40
board/congatec/cgtqmx6eval/cgtqmx6eval.c
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@ -35,32 +35,32 @@ int dram_init(void)
}
iomux_v3_cfg_t const uart2_pads[] = {
MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
};
iomux_v3_cfg_t const usdhc2_pads[] = {
MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_GPIO_4__GPIO_1_4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};
iomux_v3_cfg_t const usdhc4_pads[] = {
MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NANDF_D6__GPIO_2_6 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
};
static void setup_iomux_uart(void)

73
board/denx/m53evk/m53evk.c
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@ -13,6 +13,7 @@
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/iomux-mx53.h>
#include <asm/imx-common/mx5_video.h>
#include <asm/arch/spl.h>
#include <asm/errno.h>
#include <netdev.h>
@ -22,6 +23,11 @@
#include <fsl_esdhc.h>
#include <asm/gpio.h>
#include <usb/ehci-fsl.h>
#include <linux/fb.h>
#include <ipu_pixfmt.h>
/* Special MXCFB sync flags are here. */
#include "../drivers/video/mxcfb.h"
DECLARE_GLOBAL_DATA_PTR;
@ -166,6 +172,32 @@ int board_mmc_init(bd_t *bis)
}
#endif
#ifdef CONFIG_VIDEO
static struct fb_videomode const ampire_wvga = {
.name = "Ampire",
.refresh = 60,
.xres = 800,
.yres = 480,
.pixclock = 29851, /* picosecond (33.5 MHz) */
.left_margin = 89,
.right_margin = 164,
.upper_margin = 23,
.lower_margin = 10,
.hsync_len = 10,
.vsync_len = 10,
.sync = FB_SYNC_CLK_LAT_FALL,
};
int board_video_skip(void)
{
int ret;
ret = ipuv3_fb_init(&ampire_wvga, 1, IPU_PIX_FMT_RGB666);
if (ret)
printf("Ampire LCD cannot be configured: %d\n", ret);
return ret;
}
#endif
#define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
@ -179,6 +211,46 @@ static void setup_iomux_i2c(void)
imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
}
static void setup_iomux_video(void)
{
static const iomux_v3_cfg_t lcd_pads[] = {
MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0,
MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1,
MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2,
MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3,
MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4,
MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5,
MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6,
MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7,
MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8,
MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9,
MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10,
MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11,
MX53_PAD_EIM_A17__IPU_DISP1_DAT_12,
MX53_PAD_EIM_A18__IPU_DISP1_DAT_13,
MX53_PAD_EIM_A19__IPU_DISP1_DAT_14,
MX53_PAD_EIM_A20__IPU_DISP1_DAT_15,
MX53_PAD_EIM_A21__IPU_DISP1_DAT_16,
MX53_PAD_EIM_A22__IPU_DISP1_DAT_17,
MX53_PAD_EIM_A23__IPU_DISP1_DAT_18,
MX53_PAD_EIM_A24__IPU_DISP1_DAT_19,
MX53_PAD_EIM_D31__IPU_DISP1_DAT_20,
MX53_PAD_EIM_D30__IPU_DISP1_DAT_21,
MX53_PAD_EIM_D26__IPU_DISP1_DAT_22,
MX53_PAD_EIM_D27__IPU_DISP1_DAT_23,
MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK,
MX53_PAD_EIM_DA13__IPU_DI1_D0_CS,
MX53_PAD_EIM_DA14__IPU_DI1_D1_CS,
MX53_PAD_EIM_DA15__IPU_DI1_PIN1,
MX53_PAD_EIM_DA11__IPU_DI1_PIN2,
MX53_PAD_EIM_DA12__IPU_DI1_PIN3,
MX53_PAD_EIM_A25__IPU_DI1_PIN12,
MX53_PAD_EIM_DA10__IPU_DI1_PIN15,
};
imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
}
static void setup_iomux_nand(void)
{
static const iomux_v3_cfg_t nand_pads[] = {
@ -269,6 +341,7 @@ int board_early_init_f(void)
setup_iomux_fec();
setup_iomux_i2c();
setup_iomux_nand();
setup_iomux_video();
m53_set_clock();

2
board/freescale/mx25pdk/mx25pdk.c
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@ -138,7 +138,7 @@ int board_late_init(void)
mx25pdk_fec_init();
ret = pmic_init(I2C_PMIC);
ret = pmic_init(I2C_0);
if (ret)
return ret;

2
board/freescale/mx31pdk/mx31pdk.c
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@ -85,7 +85,7 @@ int board_late_init(void)
struct pmic *p;
int ret;
ret = pmic_init(I2C_PMIC);
ret = pmic_init(CONFIG_FSL_PMIC_BUS);
if (ret)
return ret;

2
board/freescale/mx35pdk/mx35pdk.c
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@ -213,7 +213,7 @@ int board_late_init(void)
struct pmic *p;
int ret;
ret = pmic_init(I2C_PMIC);
ret = pmic_init(I2C_0);
if (ret)
return ret;

2
board/freescale/mx51evk/mx51evk.c
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@ -174,7 +174,7 @@ static void power_init(void)
struct pmic *p;
int ret;
ret = pmic_init(I2C_PMIC);
ret = pmic_init(CONFIG_FSL_PMIC_BUS);
if (ret)
return;

2
board/freescale/mx53evk/mx53evk.c
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@ -81,7 +81,7 @@ void power_init(void)
struct pmic *p;
int ret;
ret = pmic_init(I2C_PMIC);
ret = pmic_init(I2C_0);
if (ret)
return;

2
board/freescale/mx53loco/mx53loco.c
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@ -258,7 +258,7 @@ static int power_init(void)
}
if (!i2c_probe(CONFIG_SYS_FSL_PMIC_I2C_ADDR)) {
ret = pmic_init(I2C_PMIC);
ret = pmic_init(I2C_0);
if (ret)
return ret;

68
board/freescale/mx6qarm2/mx6qarm2.c
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@ -7,7 +7,7 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/mx6q_pins.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/clock.h>
#include <asm/errno.h>
#include <asm/gpio.h>
@ -38,52 +38,52 @@ int dram_init(void)
}
iomux_v3_cfg_t const uart4_pads[] = {
MX6_PAD_KEY_COL0__UART4_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_KEY_ROW0__UART4_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
};
iomux_v3_cfg_t const usdhc3_pads[] = {
MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NANDF_CS0__GPIO_6_11 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
};
iomux_v3_cfg_t const usdhc4_pads[] = {
MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};
iomux_v3_cfg_t const enet_pads[] = {
MX6_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
};

62
board/freescale/mx6qsabreauto/mx6qsabreauto.c
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@ -11,7 +11,7 @@
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6q_pins.h>
#include <asm/arch/mx6-pins.h>
#include <asm/errno.h>
#include <asm/gpio.h>
#include <asm/imx-common/iomux-v3.h>
@ -51,25 +51,25 @@ int dram_init(void)
}
iomux_v3_cfg_t const uart4_pads[] = {
MX6_PAD_KEY_COL0__UART4_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_KEY_ROW0__UART4_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
};
iomux_v3_cfg_t const enet_pads[] = {
MX6_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
};
@ -77,12 +77,12 @@ iomux_v3_cfg_t const enet_pads[] = {
struct i2c_pads_info i2c_pad_info1 = {
.scl = {
.i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
.gpio_mode = MX6_PAD_EIM_EB2__GPIO_2_30 | PC,
.gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
.gp = IMX_GPIO_NR(2, 30)
},
.sda = {
.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
.gpio_mode = MX6_PAD_KEY_ROW3__GPIO_4_13 | PC,
.gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
.gp = IMX_GPIO_NR(4, 13)
}
};
@ -94,22 +94,22 @@ struct i2c_pads_info i2c_pad_info1 = {
struct i2c_pads_info i2c_pad_info2 = {
.scl = {
.i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
.gpio_mode = MX6_PAD_GPIO_3__GPIO_1_3 | PC,
.gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC,
.gp = IMX_GPIO_NR(1, 3)
},
.sda = {
.i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
.gpio_mode = MX6_PAD_EIM_D18__GPIO_3_18 | PC,
.gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
.gp = IMX_GPIO_NR(3, 18)
}
};
iomux_v3_cfg_t const i2c3_pads[] = {
MX6_PAD_EIM_A24__GPIO_5_4 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
iomux_v3_cfg_t const port_exp[] = {
MX6_PAD_SD2_DAT0__GPIO_1_15 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_SD2_DAT0__GPIO1_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static void setup_iomux_enet(void)
@ -118,18 +118,18 @@ static void setup_iomux_enet(void)
}
iomux_v3_cfg_t const usdhc3_pads[] = {
MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_GPIO_18__USDHC3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NANDF_CS2__GPIO_6_15 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_GPIO_18__SD3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static void setup_iomux_uart(void)

155
board/freescale/mx6sabresd/mx6sabresd.c
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@ -37,6 +37,9 @@ DECLARE_GLOBAL_DATA_PTR;
#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
int dram_init(void)
{
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
@ -45,28 +48,28 @@ int dram_init(void)
}
iomux_v3_cfg_t const uart1_pads[] = {
MX6_PAD_CSI0_DAT10__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
};
iomux_v3_cfg_t const enet_pads[] = {
MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
/* AR8031 PHY Reset */
MX6_PAD_ENET_CRS_DV__GPIO_1_25 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static void setup_iomux_enet(void)
@ -80,44 +83,62 @@ static void setup_iomux_enet(void)
}
iomux_v3_cfg_t const usdhc2_pads[] = {
MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NANDF_D4__USDHC2_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NANDF_D5__USDHC2_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NANDF_D6__USDHC2_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NANDF_D7__USDHC2_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NANDF_D2__GPIO_2_2 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NANDF_D4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NANDF_D5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NANDF_D6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NANDF_D7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
};
iomux_v3_cfg_t const usdhc3_pads[] = {
MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NANDF_D0__GPIO_2_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
};
iomux_v3_cfg_t const usdhc4_pads[] = {
MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};
iomux_v3_cfg_t const ecspi1_pads[] = {
MX6_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static void setup_spi(void)
{
imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
}
iomux_v3_cfg_t const di0_pads[] = {
MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* DISP0_CLK */
MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* DISP0_HSYNC */
MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, /* DISP0_VSYNC */
};
static void setup_iomux_uart(void)
@ -249,8 +270,22 @@ static int detect_hdmi(struct display_info_t const *dev)
return readb(&hdmi->phy_stat0) & HDMI_DVI_STAT;
}
static void disable_lvds(struct display_info_t const *dev)
{
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
int reg = readl(&iomux->gpr[2]);
reg &= ~(IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
writel(reg, &iomux->gpr[2]);
}
static void do_enable_hdmi(struct display_info_t const *dev)
{
disable_lvds(dev);
imx_enable_hdmi_phy();
}
@ -259,18 +294,19 @@ static void enable_lvds(struct display_info_t const *dev)
struct iomuxc *iomux = (struct iomuxc *)
IOMUXC_BASE_ADDR;
u32 reg = readl(&iomux->gpr[2]);
reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT;
reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT;
writel(reg, &iomux->gpr[2]);
}
static struct display_info_t const displays[] = {{
.bus = -1,
.addr = 0,
.pixfmt = IPU_PIX_FMT_RGB24,
.detect = detect_hdmi,
.enable = do_enable_hdmi,
.pixfmt = IPU_PIX_FMT_RGB666,
.detect = NULL,
.enable = enable_lvds,
.mode = {
.name = "HDMI",
.name = "Hannstar-XGA",
.refresh = 60,
.xres = 1024,
.yres = 768,
@ -286,11 +322,11 @@ static struct display_info_t const displays[] = {{
} }, {
.bus = -1,
.addr = 0,
.pixfmt = IPU_PIX_FMT_LVDS666,
.detect = NULL,
.enable = enable_lvds,
.pixfmt = IPU_PIX_FMT_RGB24,
.detect = detect_hdmi,
.enable = do_enable_hdmi,
.mode = {
.name = "Hannstar-XGA",
.name = "HDMI",
.refresh = 60,
.xres = 1024,
.yres = 768,
@ -356,11 +392,14 @@ static void setup_display(void)
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
int reg;
/* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */
imx_iomux_v3_setup_multiple_pads(di0_pads, ARRAY_SIZE(di0_pads));
enable_ipu_clock();
imx_setup_hdmi();
/* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */
reg = __raw_readl(&mxc_ccm->CCGR3);
reg = readl(&mxc_ccm->CCGR3);
reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
writel(reg, &mxc_ccm->CCGR3);
@ -440,6 +479,10 @@ int board_init(void)
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
#ifdef CONFIG_MXC_SPI
setup_spi();
#endif
return 0;
}

2
board/genesi/mx51_efikamx/efikamx.c
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@ -159,7 +159,7 @@ static void power_init(void)
struct pmic *p;
int ret;
ret = pmic_init(I2C_PMIC);
ret = pmic_init(CONFIG_FSL_PMIC_BUS);
if (ret)
return;

55
board/udoo/1066mhz_4x256mx16.cfg
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@ -0,0 +1,55 @@
/*
* Copyright (C) 2013 Boundary Devices
*
* SPDX-License-Identifier: GPL-2.0+
*/
DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036
DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
DATA 4, MX6_MMDC_P0_MDCFG0, 0x54597955
DATA 4, MX6_MMDC_P0_MDCFG1, 0xFF328F64
DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
DATA 4, MX6_MMDC_P0_MDOR, 0x00591023
DATA 4, MX6_MMDC_P0_MDASP, 0x00000027
DATA 4, MX6_MMDC_P0_MDCTL, 0x831A0000
DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
DATA 4, MX6_MMDC_P0_MDSCR, 0x09408030
DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1380003
DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1380003
DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00011117
DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00011117
DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x43510360
DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x0342033F
DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x033F033F
DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03290266
DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4B3E4141
DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x47413B4A
DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x42404843
DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4C3F4C45
DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x00350035
DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F
DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00010001
DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00010001
DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000

32
board/udoo/clocks.cfg
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@ -0,0 +1,32 @@
/*
* Copyright (C) 2013 Boundary Devices
*
* SPDX-License-Identifier: GPL-2.0+
*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
/* set the default clock gate to save power */
DATA 4, CCM_CCGR0, 0x00C03F3F
DATA 4, CCM_CCGR1, 0x0030FC03
DATA 4, CCM_CCGR2, 0x0FFFC000
DATA 4, CCM_CCGR3, 0x3FF00000
DATA 4, CCM_CCGR4, 0x00FFF300
DATA 4, CCM_CCGR5, 0x0F0000C3
DATA 4, CCM_CCGR6, 0x000003FF
/* enable AXI cache for VDOA/VPU/IPU */
DATA 4, MX6_IOMUXC_GPR4, 0xF00000FF
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
DATA 4, MX6_IOMUXC_GPR7, 0x007F007F

87
board/udoo/ddr-setup.cfg
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@ -0,0 +1,87 @@
/*
* Copyright (C) 2013 Boundary Devices
*
* SPDX-License-Identifier: GPL-2.0+
*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
/*
* DDR3 settings
* MX6Q ddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock),
* memory bus width: 64 bits x16/x32/x64
* MX6DL ddr is limited to 800 MHz(400 MHz clock)
* memory bus width: 64 bits x16/x32/x64
* MX6SOLO ddr is limited to 800 MHz(400 MHz clock)
* memory bus width: 32 bits x16/x32
*/
DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
DATA 4, MX6_IOM_GRP_B4DS, 0x00000030
DATA 4, MX6_IOM_GRP_B5DS, 0x00000030
DATA 4, MX6_IOM_GRP_B6DS, 0x00000030
DATA 4, MX6_IOM_GRP_B7DS, 0x00000030
DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030
DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030
DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030
DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030
DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030
DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030
DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030
DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030
DATA 4, MX6_IOM_DRAM_CAS, 0x00020030
DATA 4, MX6_IOM_DRAM_RAS, 0x00020030
DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030
DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030
DATA 4, MX6_IOM_DRAM_RESET, 0x00020030
DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000
DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030
DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030
/* (differential input) */
DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
/* (differential input) */
DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
/* disable ddr pullups */
DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
/* Read data DQ Byte0-3 delay */
DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333

165
board/udoo/udoo.c
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@ -9,15 +9,20 @@
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <malloc.h>
#include <asm/arch/mx6-pins.h>
#include <asm/errno.h>
#include <asm/gpio.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/sata.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <asm/arch/crm_regs.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <micrel.h>
#include <miiphy.h>
#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
@ -25,6 +30,9 @@ DECLARE_GLOBAL_DATA_PTR;
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
@ -40,24 +48,117 @@ int dram_init(void)
}
static iomux_v3_cfg_t const uart2_pads[] = {
MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
};
static iomux_v3_cfg_t const usdhc3_pads[] = {
MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};
static iomux_v3_cfg_t const wdog_pads[] = {
MX6_PAD_EIM_A24__GPIO_5_4 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_EIM_D19__GPIO_3_19,
MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_EIM_D19__GPIO3_IO19,
};
int mx6_rgmii_rework(struct phy_device *phydev)
{
/*
* Bug: Apparently uDoo does not works with Gigabit switches...
* Limiting speed to 10/100Mbps, and setting master mode, seems to
* be the only way to have a successfull PHY auto negotiation.
* How to fix: Understand why Linux kernel do not have this issue.
*/
phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0x1c00);
/* control data pad skew - devaddr = 0x02, register = 0x04 */
ksz9031_phy_extended_write(phydev, 0x02,
MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
/* rx data pad skew - devaddr = 0x02, register = 0x05 */
ksz9031_phy_extended_write(phydev, 0x02,
MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
/* tx data pad skew - devaddr = 0x02, register = 0x05 */
ksz9031_phy_extended_write(phydev, 0x02,
MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
/* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
ksz9031_phy_extended_write(phydev, 0x02,
MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);
return 0;
}
static iomux_v3_cfg_t const enet_pads1[] = {
MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
/* RGMII reset */
MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* Ethernet power supply */
MX6_PAD_EIM_EB3__GPIO2_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* pin 32 - 1 - (MODE0) all */
MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* pin 31 - 1 - (MODE1) all */
MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* pin 28 - 1 - (MODE2) all */
MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* pin 27 - 1 - (MODE3) all */
MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static iomux_v3_cfg_t const enet_pads2[] = {
MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
};
static void setup_iomux_enet(void)
{
imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
udelay(20);
gpio_direction_output(IMX_GPIO_NR(2, 31), 1); /* Power supply on */
gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* assert PHY rst */
gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
udelay(1000);
gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* deassert PHY rst */
/* Need 100ms delay to exit from reset. */
udelay(1000 * 100);
gpio_free(IMX_GPIO_NR(6, 24));
gpio_free(IMX_GPIO_NR(6, 25));
gpio_free(IMX_GPIO_NR(6, 27));
gpio_free(IMX_GPIO_NR(6, 28));
gpio_free(IMX_GPIO_NR(6, 29));
imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
}
static void setup_iomux_uart(void)
{
imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
@ -68,6 +169,7 @@ static void setup_iomux_wdog(void)
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
gpio_direction_output(WDT_TRG, 0);
gpio_direction_output(WDT_EN, 1);
gpio_direction_input(WDT_TRG);
}
static struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR };
@ -77,6 +179,37 @@ int board_mmc_getcd(struct mmc *mmc)
return 1; /* Always present */
}
int board_eth_init(bd_t *bis)
{
uint32_t base = IMX_FEC_BASE;
struct mii_dev *bus = NULL;
struct phy_device *phydev = NULL;
int ret;
setup_iomux_enet();
#ifdef CONFIG_FEC_MXC
bus = fec_get_miibus(base, -1);
if (!bus)
return 0;
/* scan phy 4,5,6,7 */
phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
if (!phydev) {
free(bus);
return 0;
}
printf("using phy at %d\n", phydev->addr);
ret = fec_probe(bis, -1, base, bus, phydev);
if (ret) {
printf("FEC MXC: %s:failed\n", __func__);
free(phydev);
free(bus);
}
#endif
return 0;
}
int board_mmc_init(bd_t *bis)
{
imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
@ -94,11 +227,23 @@ int board_early_init_f(void)
return 0;
}
int board_phy_config(struct phy_device *phydev)
{
mx6_rgmii_rework(phydev);
if (phydev->drv->config)
phydev->drv->config(phydev);
return 0;
}
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
#ifdef CONFIG_CMD_SATA
setup_sata();
#endif
return 0;
}

29
board/udoo/udoo.cfg
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@ -0,0 +1,29 @@
/*
* Copyright (C) 2013 Boundary Devices
*
* SPDX-License-Identifier: GPL-2.0+
*
* Refer doc/README.imximage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
/* image version */
IMAGE_VERSION 2
/*
* Boot Device : one of
* spi, sd (the board has no nand neither onenand)
*/
BOOT_FROM sd
#define __ASSEMBLY__
#include <config.h>
#include "asm/arch/mx6-ddr.h"
#include "asm/arch/iomux.h"
#include "asm/arch/crm_regs.h"
#include "ddr-setup.cfg"
#include "1066mhz_4x256mx16.cfg"
#include "clocks.cfg"

60
board/wandboard/wandboard.c
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@ -51,50 +51,50 @@ int dram_init(void)
}
static iomux_v3_cfg_t const uart1_pads[] = {
MX6_PAD_CSI0_DAT10__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
};
iomux_v3_cfg_t const usdhc1_pads[] = {
MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
/* Carrier MicroSD Card Detect */
MX6_PAD_GPIO_2__GPIO_1_2 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static iomux_v3_cfg_t const usdhc3_pads[] = {
MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
/* SOM MicroSD Card Detect */
MX6_PAD_EIM_DA9__GPIO_3_9 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_EIM_DA9__GPIO3_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static iomux_v3_cfg_t const enet_pads[] = {
MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
/* AR8031 PHY Reset */
MX6_PAD_EIM_D29__GPIO_3_29 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static void setup_iomux_uart(void)
@ -230,8 +230,10 @@ int board_video_skip(void)
ret = ipuv3_fb_init(&hdmi, 0, IPU_PIX_FMT_RGB24);
if (ret)
if (ret) {
printf("HDMI cannot be configured: %d\n", ret);
return ret;
}
imx_enable_hdmi_phy();
@ -263,7 +265,7 @@ int board_eth_init(bd_t *bis)
if (ret)
printf("FEC MXC: %s:failed\n", __func__);
return 0;
return ret;
}
int board_early_init_f(void)

4
boards.cfg
Unescape View File

@ -291,7 +291,7 @@ Active arm armv7 mx5 freescale mx53smd
Active arm armv7 mx5 genesi mx51_efikamx mx51_efikamx mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg -
Active arm armv7 mx5 genesi mx51_efikamx mx51_efikasb mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_sb.cfg -
Active arm armv7 mx5 ttcontrol vision2 vision2 vision2:IMX_CONFIG=board/ttcontrol/vision2/imximage_hynix.cfg Stefano Babic <sbabic@denx.de>
Active arm armv7 mx6 - udoo udoo_quad udoo:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024 Fabio Estevam <fabio.estevam@freescale.com>
Active arm armv7 mx6 - udoo udoo_quad udoo:IMX_CONFIG=board/udoo/udoo.cfg,MX6Q,DDR_MB=1024 Fabio Estevam <fabio.estevam@freescale.com>
Active arm armv7 mx6 - wandboard wandboard_dl wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024 Fabio Estevam <fabio.estevam@freescale.com>
Active arm armv7 mx6 - wandboard wandboard_quad wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048 Fabio Estevam <fabio.estevam@freescale.com>
Active arm armv7 mx6 - wandboard wandboard_solo wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512 Fabio Estevam <fabio.estevam@freescale.com>
@ -308,7 +308,7 @@ Active arm armv7 mx6 freescale mx6qsabreauto
Active arm armv7 mx6 freescale mx6sabresd mx6dlsabresd mx6sabresd:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL Fabio Estevam <fabio.estevam@freescale.com>
Active arm armv7 mx6 freescale mx6sabresd mx6qsabresd mx6sabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q Fabio Estevam <fabio.estevam@freescale.com>
Active arm armv7 mx6 freescale mx6slevk mx6slevk mx6slevk:IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL Fabio Estevam <fabio.estevam@freescale.com>
Active arm armv7 mx6 freescale titanium titanium titanium:IMX_CONFIG=board/freescale/titanium/imximage.cfg Stefan Roese <sr@denx.de>
Active arm armv7 mx6 barco titanium titanium titanium:IMX_CONFIG=board/barco/titanium/imximage.cfg Stefan Roese <sr@denx.de>
Active arm armv7 omap3 - overo omap3_overo - Steve Sakoman <sakoman@gmail.com>
Active arm armv7 omap3 - pandora omap3_pandora - Grazvydas Ignotas <notasas@gmail.com>
Active arm armv7 omap3 8dtech eco5pk eco5pk - Raphael Assenat <raph@8d.com>

76
doc/README.imx6
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@ -8,3 +8,79 @@ SoC.
1.1 MAC Address: It is stored in fuse bank 4, with the 32 lsbs in word 2 and the
16 msbs in word 3.
Example:
For reading the MAC address fuses on a MX6Q:
- The MAC address is stored in two fuse addresses (the fuse addresses are
described in the Fusemap Descriptions table from the mx6q Reference Manual):
0x620[31:0] - MAC_ADDR[31:0]
0x630[15:0] - MAC_ADDR[47:32]
In order to use the fuse API, we need to pass the bank and word values, which
are calculated as below:
Fuse address for the lower MAC address: 0x620
Base address for the fuses: 0x400
(0x620 - 0x400)/0x10 = 0x22 = 34 decimal
As the fuses are arranged in banks of 8 words:
34 / 8 = 4 and the remainder is 2, so in this case:
bank = 4
word = 2
And the U-boot command would be:
=> fuse read 4 2
Reading bank 4:
Word 0x00000002: 9f027772
Doing the same for the upper MAC address:
Fuse address for the upper MAC address: 0x630
Base address for the fuses: 0x400
(0x630 - 0x400)/0x10 = 0x23 = 35 decimal
As the fuses are arranged in banks of 8 words:
35 / 8 = 4 and the remainder is 3, so in this case:
bank = 4
word = 3
And the U-boot command would be:
=> fuse read 4 3
Reading bank 4:
Word 0x00000003: 00000004
,which matches the ethaddr value:
=> echo ${ethaddr}
00:04:9f:02:77:72
Some other useful hints:
- The 'bank' and 'word' numbers can be easily obtained from the mx6 Reference
Manual. For the mx6quad case, please check the "46.5 OCOTP Memory Map/Register
Definition" from the "i.MX 6Dual/6Quad Applications Processor Reference Manual,
Rev. 1, 04/2013" document. For example, for the MAC fuses we have:
Address:
21B_C620 Value of OTP Bank4 Word2 (MAC Address)(OCOTP_MAC0)
21B_C630 Value of OTP Bank4 Word3 (MAC Address)(OCOTP_MAC1)
- The command '=> fuse read 4 2 2' reads the whole MAC addresses at once:
=> fuse read 4 2 2
Reading bank 4:
Word 0x00000002: 9f027772 00000004

4
drivers/gpio/mxs_gpio.c
Unescape View File

@ -95,10 +95,10 @@ int gpio_direction_output(unsigned gpio, int value)
struct mxs_register_32 *reg =
(struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset);
writel(1 << PAD_PIN(gpio), &reg->reg_set);
gpio_set_value(gpio, value);
writel(1 << PAD_PIN(gpio), &reg->reg_set);
return 0;
}

13
drivers/misc/fsl_iim.c
Unescape View File

@ -16,6 +16,9 @@
#ifndef CONFIG_MPC512X
#include <asm/arch/imx-regs.h>
#endif
#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
#include <asm/arch/clock.h>
#endif
/* FSL IIM-specific constants */
#define STAT_BUSY 0x80
@ -93,6 +96,10 @@ struct fsl_iim {
} bank[8];
};
#if !defined(CONFIG_MX51) && !defined(CONFIG_MX53)
#define enable_efuse_prog_supply(enable)
#endif
static int prepare_access(struct fsl_iim **regs, u32 bank, u32 word, int assert,
const char *caller)
{
@ -237,12 +244,16 @@ int fuse_prog(u32 bank, u32 word, u32 val)
if (ret)
return ret;
enable_efuse_prog_supply(1);
for (bit = 0; val; bit++, val >>= 1)
if (val & 0x01) {
ret = prog_bit(regs, bank, word, bit);
if (ret)
if (ret) {
enable_efuse_prog_supply(0);
return ret;
}
}
enable_efuse_prog_supply(0);
return 0;
}

177
drivers/net/fec_mxc.c
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@ -270,49 +270,34 @@ static int fec_tx_task_disable(struct fec_priv *fec)
* @param[in] dsize desired size of each receive buffer
* @return 0 on success
*
* For this task we need additional memory for the data buffers. And each
* data buffer requires some alignment. Thy must be aligned to a specific
* boundary each.
* Init all RX descriptors to default values.
*/
static int fec_rbd_init(struct fec_priv *fec, int count, int dsize)
static void fec_rbd_init(struct fec_priv *fec, int count, int dsize)
{
uint32_t size;
uint8_t *data;
int i;
/*
* Allocate memory for the buffers. This allocation respects the
* alignment
* Reload the RX descriptors with default values and wipe
* the RX buffers.
*/
size = roundup(dsize, ARCH_DMA_MINALIGN);
for (i = 0; i < count; i++) {
uint32_t data_ptr = readl(&fec->rbd_base[i].data_pointer);
if (data_ptr == 0) {
uint8_t *data = memalign(ARCH_DMA_MINALIGN,
size);
if (!data) {
printf("%s: error allocating rxbuf %d\n",
__func__, i);
goto err;
}
writel((uint32_t)data, &fec->rbd_base[i].data_pointer);
} /* needs allocation */
writew(FEC_RBD_EMPTY, &fec->rbd_base[i].status);
writew(0, &fec->rbd_base[i].data_length);
data = (uint8_t *)fec->rbd_base[i].data_pointer;
memset(data, 0, dsize);
flush_dcache_range((uint32_t)data, (uint32_t)data + size);
fec->rbd_base[i].status = FEC_RBD_EMPTY;
fec->rbd_base[i].data_length = 0;
}
/* Mark the last RBD to close the ring. */
writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &fec->rbd_base[i - 1].status);
fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
fec->rbd_index = 0;
return 0;
err:
for (; i >= 0; i--) {
uint32_t data_ptr = readl(&fec->rbd_base[i].data_pointer);
free((void *)data_ptr);
}
return -ENOMEM;
flush_dcache_range((unsigned)fec->rbd_base,
(unsigned)fec->rbd_base + size);
}
/**
@ -332,10 +317,12 @@ static void fec_tbd_init(struct fec_priv *fec)
unsigned addr = (unsigned)fec->tbd_base;
unsigned size = roundup(2 * sizeof(struct fec_bd),
ARCH_DMA_MINALIGN);
writew(0x0000, &fec->tbd_base[0].status);
writew(FEC_TBD_WRAP, &fec->tbd_base[1].status);
memset(fec->tbd_base, 0, size);
fec->tbd_base[0].status = 0;
fec->tbd_base[1].status = FEC_TBD_WRAP;
fec->tbd_index = 0;
flush_dcache_range(addr, addr+size);
flush_dcache_range(addr, addr + size);
}
/**
@ -527,51 +514,18 @@ static int fec_init(struct eth_device *dev, bd_t* bd)
{
struct fec_priv *fec = (struct fec_priv *)dev->priv;
uint32_t mib_ptr = (uint32_t)&fec->eth->rmon_t_drop;
uint32_t size;
int i, ret;
int i;
/* Initialize MAC address */
fec_set_hwaddr(dev);
/*
* Allocate transmit descriptors, there are two in total. This
* allocation respects cache alignment.
* Setup transmit descriptors, there are two in total.
*/
if (!fec->tbd_base) {
size = roundup(2 * sizeof(struct fec_bd),
ARCH_DMA_MINALIGN);
fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size);
if (!fec->tbd_base) {
ret = -ENOMEM;
goto err1;
}
memset(fec->tbd_base, 0, size);
fec_tbd_init(fec);
}
fec_tbd_init(fec);
/*
* Allocate receive descriptors. This allocation respects cache
* alignment.
*/
if (!fec->rbd_base) {
size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd),
ARCH_DMA_MINALIGN);
fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size);
if (!fec->rbd_base) {
ret = -ENOMEM;
goto err2;
}
memset(fec->rbd_base, 0, size);
/*
* Initialize RxBD ring
*/
if (fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE) < 0) {
ret = -ENOMEM;
goto err3;
}
flush_dcache_range((unsigned)fec->rbd_base,
(unsigned)fec->rbd_base + size);
}
/* Setup receive descriptors. */
fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE);
fec_reg_setup(fec);
@ -608,13 +562,6 @@ static int fec_init(struct eth_device *dev, bd_t* bd)
#endif
fec_open(dev);
return 0;
err3:
free(fec->rbd_base);
err2:
free(fec->tbd_base);
err1:
return ret;
}
/**
@ -907,6 +854,74 @@ static void fec_set_dev_name(char *dest, int dev_id)
sprintf(dest, (dev_id == -1) ? "FEC" : "FEC%i", dev_id);
}
static int fec_alloc_descs(struct fec_priv *fec)
{
unsigned int size;
int i;
uint8_t *data;
/* Allocate TX descriptors. */
size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size);
if (!fec->tbd_base)
goto err_tx;
/* Allocate RX descriptors. */
size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size);
if (!fec->rbd_base)
goto err_rx;
memset(fec->rbd_base, 0, size);
/* Allocate RX buffers. */
/* Maximum RX buffer size. */
size = roundup(FEC_MAX_PKT_SIZE, ARCH_DMA_MINALIGN);
for (i = 0; i < FEC_RBD_NUM; i++) {
data = memalign(ARCH_DMA_MINALIGN, size);
if (!data) {
printf("%s: error allocating rxbuf %d\n", __func__, i);
goto err_ring;
}
memset(data, 0, size);
fec->rbd_base[i].data_pointer = (uint32_t)data;
fec->rbd_base[i].status = FEC_RBD_EMPTY;
fec->rbd_base[i].data_length = 0;
/* Flush the buffer to memory. */
flush_dcache_range((uint32_t)data, (uint32_t)data + size);
}
/* Mark the last RBD to close the ring. */
fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
fec->rbd_index = 0;
fec->tbd_index = 0;
return 0;
err_ring:
for (; i >= 0; i--)
free((void *)fec->rbd_base[i].data_pointer);
free(fec->rbd_base);
err_rx:
free(fec->tbd_base);
err_tx:
return -ENOMEM;
}
static void fec_free_descs(struct fec_priv *fec)
{
int i;
for (i = 0; i < FEC_RBD_NUM; i++)
free((void *)fec->rbd_base[i].data_pointer);
free(fec->rbd_base);
free(fec->tbd_base);
}
#ifdef CONFIG_PHYLIB
int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
struct mii_dev *bus, struct phy_device *phydev)
@ -939,6 +954,10 @@ static int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
memset(edev, 0, sizeof(*edev));
memset(fec, 0, sizeof(*fec));
ret = fec_alloc_descs(fec);
if (ret)
goto err3;
edev->priv = fec;
edev->init = fec_init;
edev->send = fec_send;
@ -957,7 +976,7 @@ static int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) {
if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
printf("FEC MXC: Timeout reseting chip\n");
goto err3;
goto err4;
}
udelay(10);
}
@ -984,6 +1003,8 @@ static int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
eth_setenv_enetaddr("ethaddr", ethaddr);
}
return ret;
err4:
fec_free_descs(fec);
err3:
free(fec);
err2:

3
drivers/power/power_fsl.c
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@ -36,10 +36,10 @@ int pmic_init(unsigned char bus)
p->name = name;
p->number_of_regs = PMIC_NUM_OF_REGS;
p->bus = bus;
#if defined(CONFIG_POWER_SPI)
p->interface = PMIC_SPI;
p->bus = CONFIG_FSL_PMIC_BUS;
p->hw.spi.cs = CONFIG_FSL_PMIC_CS;
p->hw.spi.clk = CONFIG_FSL_PMIC_CLK;
p->hw.spi.mode = CONFIG_FSL_PMIC_MODE;
@ -50,7 +50,6 @@ int pmic_init(unsigned char bus)
p->interface = PMIC_I2C;
p->hw.i2c.addr = CONFIG_SYS_FSL_PMIC_I2C_ADDR;
p->hw.i2c.tx_num = FSL_PMIC_I2C_LENGTH;
p->bus = bus;
#else
#error "You must select CONFIG_POWER_SPI or CONFIG_PMIC_I2C"
#endif

2
include/configs/cgtqmx6eval.h
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@ -81,7 +81,7 @@
"console=ttymxc1\0" \
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
"fdt_addr=0x11000000\0" \
"fdt_addr=0x18000000\0" \
"boot_fdt=try\0" \
"mmcdev=1\0" \
"mmcpart=1\0" \

1
include/configs/imx31_phycore.h
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@ -37,7 +37,6 @@
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_SPD_BUS_NUM 1 /* I2C2 */
#define CONFIG_SYS_I2C_CLK_OFFSET I2C2_CLK_OFFSET
#define CONFIG_MXC_UART

16
include/configs/m53evk.h
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@ -37,6 +37,7 @@
#define CONFIG_CMD_PING
#define CONFIG_CMD_SATA
#define CONFIG_CMD_USB
#define CONFIG_VIDEO
/*
* Memory configurations
@ -201,6 +202,21 @@
#endif
/*
* LCD
*/
#ifdef CONFIG_VIDEO
#define CONFIG_VIDEO_IPUV3
#define CONFIG_CFB_CONSOLE
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_VIDEO_BMP_RLE8
#define CONFIG_SPLASH_SCREEN
#define CONFIG_BMP_16BPP
#define CONFIG_VIDEO_LOGO
#define CONFIG_IPUV3_CLK 200000000
#endif
/*
* Boot Linux
*/
#define CONFIG_CMDLINE_TAG

2
include/configs/mx25pdk.h
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@ -68,7 +68,6 @@
#define CONFIG_SYS_MMC_ENV_DEV 0
/* U-Boot general configuration */
#define CONFIG_SYS_PROMPT "MX25PDK U-Boot > "
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
/* Print buffer sz */
@ -116,7 +115,6 @@
#define CONFIG_CMD_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_SPD_BUS_NUM 0 /* I2C1 */
/* RTC */
#define CONFIG_RTC_IMXDI

56
include/configs/mx28evk.h
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@ -14,7 +14,6 @@
/* System configurations */
#define CONFIG_MX28 /* i.MX28 SoC */
#define CONFIG_MACH_TYPE MACH_TYPE_MX28EVK
#define CONFIG_SYS_PROMPT "MX28EVK U-Boot > "
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
@ -97,7 +96,7 @@
"512k(environment)," \
"512k(redundant-environment)," \
"4m(kernel)," \
"128k(fdt)," \
"512k(fdt)," \
"8m(ramdisk)," \
"-(filesystem)"
#endif
@ -161,9 +160,9 @@
/* Extra Environment */
#define CONFIG_EXTRA_ENV_SETTINGS \
"ubifs_file=filesystem.ubifs\0" \
"update_nand_full_filename=u-boot.nand\0" \
"update_nand_firmware_filename=u-boot.sb\0" \
"update_sd_firmware_filename=u-boot.sd\0" \
"update_nand_firmware_maxsz=0x100000\0" \
"update_nand_stride=0x40\0" /* MX28 datasheet ch. 12.12 */ \
"update_nand_count=0x4\0" /* MX28 datasheet ch. 12.12 */ \
@ -172,7 +171,7 @@
"nand info ; " \
"setexpr fcb_sz ${update_nand_stride} * ${update_nand_count};" \
"setexpr update_nand_fcb ${fcb_sz} * ${nand_writesize}\0" \
"update_nand_full=" /* Update FCB, DBBT and FW */ \
"update_nand_firmware_full=" /* Update FCB, DBBT and FW */ \
"if tftp ${update_nand_full_filename} ; then " \
"run update_nand_get_fcb_size ; " \
"nand scrub -y 0x0 ${filesize} ; " \
@ -191,6 +190,55 @@
"nand write ${loadaddr} ${fcb_sz} ${filesize} ; " \
"nand write ${loadaddr} ${fw_off} ${filesize} ; " \
"fi\0" \
"update_nand_kernel=" /* Update kernel */ \
"mtdparts default; " \
"nand erase.part kernel; " \
"if test ${ip_dyn} = yes; then " \
"setenv get_cmd dhcp; " \
"else " \
"setenv get_cmd tftp; " \
"fi; " \
"${get_cmd} ${uimage}; " \
"nand write ${loadaddr} kernel ${filesize}\0" \
"update_nand_fdt=" /* Update fdt */ \
"mtdparts default; " \
"nand erase.part fdt; " \
"if test ${ip_dyn} = yes; then " \
"setenv get_cmd dhcp; " \
"else " \
"setenv get_cmd tftp; " \
"fi; " \
"${get_cmd} ${fdt_file}; " \
"nand write ${loadaddr} fdt ${filesize}\0" \
"update_nand_filesystem=" /* Update filesystem */ \
"mtdparts default; " \
"nand erase.part filesystem; " \
"if test ${ip_dyn} = yes; then " \
"setenv get_cmd dhcp; " \
"else " \
"setenv get_cmd tftp; " \
"fi; " \
"${get_cmd} ${ubifs_file}; " \
"ubi part filesystem; " \
"ubi create filesystem; " \
"ubi write ${loadaddr} filesystem ${filesize}\0" \
"nandargs=setenv bootargs console=${console_mainline},${baudrate} " \
"rootfstype=ubifs ubi.mtd=6 root=ubi0_0 ${mtdparts}\0" \
"nandboot=" /* Boot from NAND */ \
"mtdparts default; " \
"run nandargs; " \
"nand read ${loadaddr} kernel 0x00400000; " \
"if test ${boot_fdt} = yes; then " \
"nand read ${fdt_addr} fdt 0x00080000; " \
"bootm ${loadaddr} - ${fdt_addr}; " \
"else " \
"if test ${boot_fdt} = no; then " \
"bootm; " \
"else " \
"echo \"ERROR: Set boot_fdt to yes or no.\"; " \
"fi; " \
"fi\0" \
"update_sd_firmware_filename=u-boot.sd\0" \
"update_sd_firmware=" /* Update the SD firmware partition */ \
"if mmc rescan ; then " \
"if tftp ${update_sd_firmware_filename} ; then " \

1
include/configs/mx31pdk.h
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@ -120,7 +120,6 @@
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_PROMPT "MX31PDK U-Boot > "
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \

2
include/configs/mx35pdk.h
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@ -42,7 +42,6 @@
*/
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_SPD_BUS_NUM 0 /* I2C1 */
#define CONFIG_MXC_SPI
#define CONFIG_MXC_GPIO
@ -135,7 +134,6 @@
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_PROMPT "MX35 U-Boot > "
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */

1
include/configs/mx51evk.h
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@ -219,7 +219,6 @@
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
#define CONFIG_SYS_PROMPT "MX51EVK U-Boot > "
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
/* Print Buffer Size */

1
include/configs/mx53ard.h
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@ -46,7 +46,6 @@
#define CONFIG_CMD_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_SPD_BUS_NUM 1 /* I2C2 */
/* MMC Configs */
#define CONFIG_FSL_ESDHC

2
include/configs/mx53evk.h
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@ -39,7 +39,6 @@
#define CONFIG_CMD_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_SPD_BUS_NUM 1 /* I2C2 */
/* PMIC Configs */
#define CONFIG_POWER
@ -135,7 +134,6 @@
/* Miscellaneous configurable options */
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
#define CONFIG_SYS_PROMPT "MX53EVK U-Boot > "
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */

2
include/configs/mx53loco.h
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@ -73,7 +73,6 @@
/* I2C Configs */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_SPD_BUS_NUM 0 /* I2C1 */
/* PMIC Controller */
#define CONFIG_POWER
@ -177,7 +176,6 @@
/* Miscellaneous configurable options */
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
#define CONFIG_SYS_PROMPT "MX53LOCO U-Boot > "
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */

2
include/configs/mx53smd.h
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@ -36,7 +36,6 @@
#define CONFIG_CMD_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_SPD_BUS_NUM 1 /* I2C2 */
/* MMC Configs */
#define CONFIG_FSL_ESDHC
@ -120,7 +119,6 @@
/* Miscellaneous configurable options */
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
#define CONFIG_SYS_PROMPT "MX53SMD U-Boot > "
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */

1
include/configs/mx6_common.h
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@ -20,5 +20,6 @@
#define CONFIG_ARM_ERRATA_742230
#define CONFIG_ARM_ERRATA_743622
#define CONFIG_ARM_ERRATA_751472
#define CONFIG_BOARD_POSTCLK_INIT
#endif

1
include/configs/mx6qarm2.h
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@ -114,7 +114,6 @@
/* Miscellaneous configurable options */
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT "MX6QARM2 U-Boot > "
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_CBSIZE 256

20
include/configs/mx6sabre_common.h
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@ -18,6 +18,7 @@
#define CONFIG_DISPLAY_BOARDINFO
#include <asm/arch/imx-regs.h>
#include <asm/imx-common/gpio.h>
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
@ -33,6 +34,11 @@
#define CONFIG_MXC_UART
#define CONFIG_CMD_FUSE
#ifdef CONFIG_CMD_FUSE
#define CONFIG_MXC_OCOTP
#endif
/* MMC Configs */
#define CONFIG_FSL_ESDHC
#define CONFIG_FSL_USDHC
@ -60,6 +66,17 @@
#define CONFIG_PHYLIB
#define CONFIG_PHY_ATHEROS
#define CONFIG_CMD_SF
#ifdef CONFIG_CMD_SF
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_MXC_SPI
#define CONFIG_SF_DEFAULT_BUS 0
#define CONFIG_SF_DEFAULT_CS (0 | (IMX_GPIO_NR(4, 9) << 8))
#define CONFIG_SF_DEFAULT_SPEED 20000000
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#endif
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_CONS_INDEX 1
@ -82,7 +99,7 @@
"script=boot.scr\0" \
"uimage=uImage\0" \
"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
"fdt_addr=0x11000000\0" \
"fdt_addr=0x18000000\0" \
"boot_fdt=try\0" \
"ip_dyn=yes\0" \
"console=" CONFIG_CONSOLE_DEV "\0" \
@ -171,7 +188,6 @@
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_PROMPT "U-Boot > "
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_CBSIZE 256

13
include/configs/nitrogen6x.h
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@ -10,6 +10,7 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#include "mx6_common.h"
#define CONFIG_MX6
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
@ -62,16 +63,6 @@
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_SPEED 100000
/* OCOTP Configs */
#define CONFIG_CMD_IMXOTP
#ifdef CONFIG_CMD_IMXOTP
#define CONFIG_IMX_OTP
#define IMX_OTP_BASE OCOTP_BASE_ADDR
#define IMX_OTP_ADDR_MAX 0x7F
#define IMX_OTP_DATA_ERROR_VAL 0xBADABADA
#define IMX_OTPWRITE_ENABLED
#endif
/* MMC Configs */
#define CONFIG_FSL_ESDHC
#define CONFIG_FSL_USDHC
@ -189,7 +180,7 @@
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
"fdt_file=imx6q-sabrelite.dtb\0" \
"fdt_addr=0x11000000\0" \
"fdt_addr=0x18000000\0" \
"boot_fdt=try\0" \
"ip_dyn=yes\0" \
"mmcdev=0\0" \

1
include/configs/titanium.h
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@ -13,6 +13,7 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#include "mx6_common.h"
#include <asm/arch/imx-regs.h>
#include <asm/imx-common/gpio.h>

31
include/configs/udoo.h
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@ -9,6 +9,7 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#include "mx6_common.h"
#include <asm/arch/imx-regs.h>
#include <asm/imx-common/gpio.h>
#include <asm/sizes.h>
@ -34,6 +35,34 @@
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART2_BASE
/* SATA Configs */
#define CONFIG_CMD_SATA
#ifdef CONFIG_CMD_SATA
#define CONFIG_DWC_AHSATA
#define CONFIG_SYS_SATA_MAX_DEVICE 1
#define CONFIG_DWC_AHSATA_PORT_ID 0
#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
#define CONFIG_LBA48
#define CONFIG_LIBATA
#endif
/* Network support */
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#define CONFIG_FEC_MXC
#define CONFIG_MII
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 6
#define CONFIG_PHYLIB
#define CONFIG_PHY_MICREL
#define CONFIG_PHY_MICREL_KSZ9031
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_CONS_INDEX 1
@ -77,7 +106,7 @@
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
"fdt_addr=0x11000000\0" \
"fdt_addr=0x18000000\0" \
"boot_fdt=try\0" \
"ip_dyn=yes\0" \
"mmcdev=0\0" \

3
include/configs/wandboard.h
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@ -9,6 +9,7 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#include "mx6_common.h"
#include <asm/arch/imx-regs.h>
#include <asm/imx-common/gpio.h>
#include <asm/sizes.h>
@ -113,7 +114,7 @@
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
"fdt_addr=0x11000000\0" \
"fdt_addr=0x18000000\0" \
"boot_fdt=try\0" \
"ip_dyn=yes\0" \
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \

1
tools/mxsimage.c
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@ -502,6 +502,7 @@ static int sb_token_to_long(char *tok, uint32_t *rid)
tok += 2;
errno = 0;
id = strtoul(tok, &endptr, 16);
if ((errno == ERANGE && id == ULONG_MAX) || (errno != 0 && id == 0)) {
fprintf(stderr, "ERR: Value can't be decoded!\n");

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