Tom Rini
7 years ago
commit
a89302cc79
@ -0,0 +1,376 @@ |
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/* |
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* Device Tree Source for the H3ULCB (R-Car Starter Kit Premier) board |
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* |
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* Copyright (C) 2016 Renesas Electronics Corp. |
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* Copyright (C) 2016 Cogent Embedded, Inc. |
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* |
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* This file is licensed under the terms of the GNU General Public License |
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* version 2. This program is licensed "as is" without any warranty of any |
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* kind, whether express or implied. |
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*/ |
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|
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/dts-v1/; |
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#include "r8a7795.dtsi" |
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#include <dt-bindings/gpio/gpio.h> |
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#include <dt-bindings/input/input.h> |
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|
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/ { |
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model = "Renesas H3ULCB board based on r8a7795"; |
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compatible = "renesas,h3ulcb", "renesas,r8a7795"; |
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|
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aliases { |
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serial0 = &scif2; |
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ethernet0 = &avb; |
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}; |
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|
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chosen { |
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stdout-path = "serial0:115200n8"; |
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}; |
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|
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memory@48000000 { |
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device_type = "memory"; |
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/* first 128MB is reserved for secure area. */ |
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reg = <0x0 0x48000000 0x0 0x38000000>; |
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}; |
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|
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memory@500000000 { |
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device_type = "memory"; |
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reg = <0x5 0x00000000 0x0 0x40000000>; |
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}; |
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|
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memory@600000000 { |
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device_type = "memory"; |
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reg = <0x6 0x00000000 0x0 0x40000000>; |
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}; |
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|
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memory@700000000 { |
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device_type = "memory"; |
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reg = <0x7 0x00000000 0x0 0x40000000>; |
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}; |
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|
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leds { |
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compatible = "gpio-leds"; |
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|
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led5 { |
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gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>; |
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}; |
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led6 { |
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gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; |
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}; |
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}; |
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|
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keyboard { |
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compatible = "gpio-keys"; |
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|
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key-1 { |
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linux,code = <KEY_1>; |
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label = "SW3"; |
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wakeup-source; |
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debounce-interval = <20>; |
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gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; |
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}; |
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}; |
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|
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x12_clk: x12 { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <24576000>; |
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}; |
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|
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reg_1p8v: regulator0 { |
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compatible = "regulator-fixed"; |
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regulator-name = "fixed-1.8V"; |
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regulator-min-microvolt = <1800000>; |
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regulator-max-microvolt = <1800000>; |
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regulator-boot-on; |
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regulator-always-on; |
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}; |
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|
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reg_3p3v: regulator1 { |
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compatible = "regulator-fixed"; |
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regulator-name = "fixed-3.3V"; |
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regulator-min-microvolt = <3300000>; |
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regulator-max-microvolt = <3300000>; |
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regulator-boot-on; |
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regulator-always-on; |
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}; |
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|
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vcc_sdhi0: regulator-vcc-sdhi0 { |
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compatible = "regulator-fixed"; |
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|
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regulator-name = "SDHI0 Vcc"; |
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regulator-min-microvolt = <3300000>; |
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regulator-max-microvolt = <3300000>; |
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gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; |
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enable-active-high; |
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}; |
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vccq_sdhi0: regulator-vccq-sdhi0 { |
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compatible = "regulator-gpio"; |
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regulator-name = "SDHI0 VccQ"; |
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regulator-min-microvolt = <1800000>; |
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regulator-max-microvolt = <3300000>; |
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|
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gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; |
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gpios-states = <1>; |
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states = <3300000 1 |
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1800000 0>; |
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}; |
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audio_clkout: audio-clkout { |
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/* |
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* This is same as <&rcar_sound 0> |
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* but needed to avoid cs2000/rcar_sound probe dead-lock |
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*/ |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <11289600>; |
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}; |
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|
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rsnd_ak4613: sound { |
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compatible = "simple-audio-card"; |
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simple-audio-card,format = "left_j"; |
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simple-audio-card,bitclock-master = <&sndcpu>; |
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simple-audio-card,frame-master = <&sndcpu>; |
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sndcpu: simple-audio-card,cpu { |
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sound-dai = <&rcar_sound>; |
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}; |
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sndcodec: simple-audio-card,codec { |
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sound-dai = <&ak4613>; |
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}; |
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}; |
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}; |
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&extal_clk { |
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clock-frequency = <16666666>; |
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}; |
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&extalr_clk { |
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clock-frequency = <32768>; |
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}; |
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|
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&pfc { |
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pinctrl-0 = <&scif_clk_pins>; |
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pinctrl-names = "default"; |
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scif2_pins: scif2 { |
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groups = "scif2_data_a"; |
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function = "scif2"; |
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}; |
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scif_clk_pins: scif_clk { |
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groups = "scif_clk_a"; |
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function = "scif_clk"; |
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}; |
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|
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i2c2_pins: i2c2 { |
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groups = "i2c2_a"; |
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function = "i2c2"; |
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}; |
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|
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avb_pins: avb { |
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groups = "avb_mdc"; |
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function = "avb"; |
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}; |
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|
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sdhi0_pins: sd0 { |
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groups = "sdhi0_data4", "sdhi0_ctrl"; |
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function = "sdhi0"; |
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power-source = <3300>; |
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}; |
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sdhi0_pins_uhs: sd0_uhs { |
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groups = "sdhi0_data4", "sdhi0_ctrl"; |
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function = "sdhi0"; |
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power-source = <1800>; |
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}; |
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sdhi2_pins: sd2 { |
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groups = "sdhi2_data8", "sdhi2_ctrl"; |
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function = "sdhi2"; |
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power-source = <3300>; |
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}; |
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sdhi2_pins_uhs: sd2_uhs { |
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groups = "sdhi2_data8", "sdhi2_ctrl"; |
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function = "sdhi2"; |
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power-source = <1800>; |
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}; |
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sound_pins: sound { |
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groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a"; |
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function = "ssi"; |
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}; |
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sound_clk_pins: sound-clk { |
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groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clk_c_a", |
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"audio_clkout_a", "audio_clkout3_a"; |
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function = "audio_clk"; |
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}; |
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usb1_pins: usb1 { |
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groups = "usb1"; |
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function = "usb1"; |
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}; |
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}; |
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&scif2 { |
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pinctrl-0 = <&scif2_pins>; |
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pinctrl-names = "default"; |
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status = "okay"; |
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}; |
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&scif_clk { |
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clock-frequency = <14745600>; |
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}; |
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&i2c2 { |
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pinctrl-0 = <&i2c2_pins>; |
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pinctrl-names = "default"; |
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status = "okay"; |
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clock-frequency = <100000>; |
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ak4613: codec@10 { |
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compatible = "asahi-kasei,ak4613"; |
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#sound-dai-cells = <0>; |
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reg = <0x10>; |
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clocks = <&rcar_sound 3>; |
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asahi-kasei,in1-single-end; |
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asahi-kasei,in2-single-end; |
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asahi-kasei,out1-single-end; |
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asahi-kasei,out2-single-end; |
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asahi-kasei,out3-single-end; |
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asahi-kasei,out4-single-end; |
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asahi-kasei,out5-single-end; |
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asahi-kasei,out6-single-end; |
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}; |
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cs2000: clk-multiplier@4f { |
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#clock-cells = <0>; |
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compatible = "cirrus,cs2000-cp"; |
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reg = <0x4f>; |
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clocks = <&audio_clkout>, <&x12_clk>; |
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clock-names = "clk_in", "ref_clk"; |
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assigned-clocks = <&cs2000>; |
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assigned-clock-rates = <24576000>; /* 1/1 divide */ |
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}; |
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}; |
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&rcar_sound { |
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pinctrl-0 = <&sound_pins &sound_clk_pins>; |
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pinctrl-names = "default"; |
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/* Single DAI */ |
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#sound-dai-cells = <0>; |
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/* audio_clkout0/1/2/3 */ |
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#clock-cells = <1>; |
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clock-frequency = <11289600>; |
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status = "okay"; |
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/* update <audio_clk_b> to <cs2000> */ |
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clocks = <&cpg CPG_MOD 1005>, |
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<&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, |
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<&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, |
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<&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, |
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<&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, |
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<&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, |
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<&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, |
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<&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, |
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<&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, |
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<&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, |
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<&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, |
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<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, |
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<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, |
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<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, |
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<&audio_clk_a>, <&cs2000>, |
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<&audio_clk_c>, |
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<&cpg CPG_CORE R8A7795_CLK_S0D4>; |
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rcar_sound,dai { |
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dai0 { |
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playback = <&ssi0 &src0 &dvc0>; |
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capture = <&ssi1 &src1 &dvc1>; |
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}; |
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}; |
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}; |
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&sdhi0 { |
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pinctrl-0 = <&sdhi0_pins>; |
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pinctrl-1 = <&sdhi0_pins_uhs>; |
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pinctrl-names = "default", "state_uhs"; |
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vmmc-supply = <&vcc_sdhi0>; |
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vqmmc-supply = <&vccq_sdhi0>; |
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cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; |
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bus-width = <4>; |
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sd-uhs-sdr50; |
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status = "okay"; |
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}; |
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&sdhi2 { |
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/* used for on-board 8bit eMMC */ |
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pinctrl-0 = <&sdhi2_pins>; |
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pinctrl-1 = <&sdhi2_pins_uhs>; |
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pinctrl-names = "default", "state_uhs"; |
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vmmc-supply = <®_3p3v>; |
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vqmmc-supply = <®_1p8v>; |
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bus-width = <8>; |
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non-removable; |
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status = "okay"; |
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}; |
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&ssi1 { |
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shared-pin; |
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}; |
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&wdt0 { |
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timeout-sec = <60>; |
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status = "okay"; |
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}; |
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&audio_clk_a { |
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clock-frequency = <22579200>; |
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}; |
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&avb { |
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pinctrl-0 = <&avb_pins>; |
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pinctrl-names = "default"; |
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renesas,no-ether-link; |
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phy-handle = <&phy0>; |
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status = "okay"; |
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phy0: ethernet-phy@0 { |
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rxc-skew-ps = <1500>; |
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reg = <0>; |
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interrupt-parent = <&gpio2>; |
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interrupts = <11 IRQ_TYPE_LEVEL_LOW>; |
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}; |
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}; |
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&usb2_phy1 { |
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pinctrl-0 = <&usb1_pins>; |
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pinctrl-names = "default"; |
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status = "okay"; |
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}; |
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&ehci1 { |
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status = "okay"; |
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}; |
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&ohci1 { |
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status = "okay"; |
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}; |
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@ -0,0 +1,584 @@ |
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/* |
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* Device Tree Source for the Salvator-X board |
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* |
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* Copyright (C) 2015 Renesas Electronics Corp. |
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* |
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* This file is licensed under the terms of the GNU General Public License |
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* version 2. This program is licensed "as is" without any warranty of any |
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* kind, whether express or implied. |
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*/ |
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|
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/* |
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* SSI-AK4613 |
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* |
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* This command is required when Playback/Capture |
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* |
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* amixer set "DVC Out" 100% |
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* amixer set "DVC In" 100% |
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* |
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* You can use Mute |
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* |
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* amixer set "DVC Out Mute" on |
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* amixer set "DVC In Mute" on |
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* |
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* You can use Volume Ramp |
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* |
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* amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps" |
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* amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps" |
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* amixer set "DVC Out Ramp" on |
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* aplay xxx.wav & |
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* amixer set "DVC Out" 80% // Volume Down |
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* amixer set "DVC Out" 100% // Volume Up |
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*/ |
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/dts-v1/; |
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#include "r8a7795.dtsi" |
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#include <dt-bindings/gpio/gpio.h> |
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/ { |
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model = "Renesas Salvator-X board based on r8a7795"; |
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compatible = "renesas,salvator-x", "renesas,r8a7795"; |
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|
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aliases { |
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serial0 = &scif2; |
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serial1 = &scif1; |
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ethernet0 = &avb; |
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}; |
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|
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chosen { |
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bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; |
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stdout-path = "serial0:115200n8"; |
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}; |
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|
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memory@48000000 { |
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device_type = "memory"; |
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/* first 128MB is reserved for secure area. */ |
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reg = <0x0 0x48000000 0x0 0x38000000>; |
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}; |
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|
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x12_clk: x12 { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <24576000>; |
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}; |
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|
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reg_1p8v: regulator0 { |
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compatible = "regulator-fixed"; |
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regulator-name = "fixed-1.8V"; |
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regulator-min-microvolt = <1800000>; |
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regulator-max-microvolt = <1800000>; |
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regulator-boot-on; |
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regulator-always-on; |
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}; |
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|
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reg_3p3v: regulator1 { |
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compatible = "regulator-fixed"; |
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regulator-name = "fixed-3.3V"; |
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regulator-min-microvolt = <3300000>; |
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regulator-max-microvolt = <3300000>; |
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regulator-boot-on; |
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regulator-always-on; |
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}; |
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|
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vcc_sdhi0: regulator-vcc-sdhi0 { |
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compatible = "regulator-fixed"; |
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|
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regulator-name = "SDHI0 Vcc"; |
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regulator-min-microvolt = <3300000>; |
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regulator-max-microvolt = <3300000>; |
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|
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gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; |
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enable-active-high; |
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}; |
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|
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vccq_sdhi0: regulator-vccq-sdhi0 { |
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compatible = "regulator-gpio"; |
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|
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regulator-name = "SDHI0 VccQ"; |
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regulator-min-microvolt = <1800000>; |
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regulator-max-microvolt = <3300000>; |
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|
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gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; |
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gpios-states = <1>; |
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states = <3300000 1 |
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1800000 0>; |
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}; |
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|
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vcc_sdhi3: regulator-vcc-sdhi3 { |
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compatible = "regulator-fixed"; |
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|
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regulator-name = "SDHI3 Vcc"; |
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regulator-min-microvolt = <3300000>; |
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regulator-max-microvolt = <3300000>; |
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|
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gpio = <&gpio3 15 GPIO_ACTIVE_HIGH>; |
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enable-active-high; |
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}; |
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|
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vccq_sdhi3: regulator-vccq-sdhi3 { |
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compatible = "regulator-gpio"; |
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|
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regulator-name = "SDHI3 VccQ"; |
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regulator-min-microvolt = <1800000>; |
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regulator-max-microvolt = <3300000>; |
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|
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gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; |
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gpios-states = <1>; |
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states = <3300000 1 |
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1800000 0>; |
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}; |
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|
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vbus0_usb2: regulator-vbus0-usb2 { |
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compatible = "regulator-fixed"; |
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|
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regulator-name = "USB20_VBUS0"; |
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regulator-min-microvolt = <5000000>; |
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regulator-max-microvolt = <5000000>; |
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|
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gpio = <&gpio6 16 GPIO_ACTIVE_HIGH>; |
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enable-active-high; |
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}; |
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|
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audio_clkout: audio_clkout { |
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/* |
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* This is same as <&rcar_sound 0> |
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* but needed to avoid cs2000/rcar_sound probe dead-lock |
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*/ |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <11289600>; |
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}; |
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|
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rsnd_ak4613: sound { |
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compatible = "simple-audio-card"; |
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|
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simple-audio-card,format = "left_j"; |
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simple-audio-card,bitclock-master = <&sndcpu>; |
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simple-audio-card,frame-master = <&sndcpu>; |
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|
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sndcpu: simple-audio-card,cpu { |
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sound-dai = <&rcar_sound>; |
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}; |
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|
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sndcodec: simple-audio-card,codec { |
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sound-dai = <&ak4613>; |
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}; |
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}; |
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|
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vga-encoder { |
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compatible = "adi,adv7123"; |
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|
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ports { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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|
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port@0 { |
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reg = <0>; |
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adv7123_in: endpoint { |
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remote-endpoint = <&du_out_rgb>; |
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}; |
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}; |
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port@1 { |
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reg = <1>; |
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adv7123_out: endpoint { |
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remote-endpoint = <&vga_in>; |
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}; |
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}; |
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}; |
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}; |
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|
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vga { |
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compatible = "vga-connector"; |
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|
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port { |
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vga_in: endpoint { |
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remote-endpoint = <&adv7123_out>; |
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}; |
||||
}; |
||||
}; |
||||
}; |
||||
|
||||
&du { |
||||
pinctrl-0 = <&du_pins>; |
||||
pinctrl-names = "default"; |
||||
status = "okay"; |
||||
|
||||
ports { |
||||
port@0 { |
||||
endpoint { |
||||
remote-endpoint = <&adv7123_in>; |
||||
}; |
||||
}; |
||||
port@3 { |
||||
lvds_connector: endpoint { |
||||
}; |
||||
}; |
||||
}; |
||||
}; |
||||
|
||||
&extal_clk { |
||||
clock-frequency = <16666666>; |
||||
}; |
||||
|
||||
&extalr_clk { |
||||
clock-frequency = <32768>; |
||||
}; |
||||
|
||||
&pfc { |
||||
pinctrl-0 = <&scif_clk_pins>; |
||||
pinctrl-names = "default"; |
||||
|
||||
scif1_pins: scif1 { |
||||
groups = "scif1_data_a", "scif1_ctrl"; |
||||
function = "scif1"; |
||||
}; |
||||
scif2_pins: scif2 { |
||||
groups = "scif2_data_a"; |
||||
function = "scif2"; |
||||
}; |
||||
scif_clk_pins: scif_clk { |
||||
groups = "scif_clk_a"; |
||||
function = "scif_clk"; |
||||
}; |
||||
|
||||
i2c2_pins: i2c2 { |
||||
groups = "i2c2_a"; |
||||
function = "i2c2"; |
||||
}; |
||||
|
||||
avb_pins: avb { |
||||
mux { |
||||
groups = "avb_link", "avb_phy_int", "avb_mdc", |
||||
"avb_mii"; |
||||
function = "avb"; |
||||
}; |
||||
|
||||
pins_mdc { |
||||
groups = "avb_mdc"; |
||||
drive-strength = <24>; |
||||
}; |
||||
|
||||
pins_mii_tx { |
||||
pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0", |
||||
"PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3"; |
||||
drive-strength = <12>; |
||||
}; |
||||
}; |
||||
|
||||
du_pins: du { |
||||
groups = "du_rgb888", "du_sync", "du_oddf", "du_clk_out_0"; |
||||
function = "du"; |
||||
}; |
||||
|
||||
sdhi0_pins: sd0 { |
||||
groups = "sdhi0_data4", "sdhi0_ctrl"; |
||||
function = "sdhi0"; |
||||
power-source = <3300>; |
||||
}; |
||||
|
||||
sdhi0_pins_uhs: sd0_uhs { |
||||
groups = "sdhi0_data4", "sdhi0_ctrl"; |
||||
function = "sdhi0"; |
||||
power-source = <1800>; |
||||
}; |
||||
|
||||
sdhi2_pins: sd2 { |
||||
groups = "sdhi2_data8", "sdhi2_ctrl"; |
||||
function = "sdhi2"; |
||||
power-source = <3300>; |
||||
}; |
||||
|
||||
sdhi2_pins_uhs: sd2_uhs { |
||||
groups = "sdhi2_data8", "sdhi2_ctrl"; |
||||
function = "sdhi2"; |
||||
power-source = <1800>; |
||||
}; |
||||
|
||||
sdhi3_pins: sd3 { |
||||
groups = "sdhi3_data4", "sdhi3_ctrl"; |
||||
function = "sdhi3"; |
||||
power-source = <3300>; |
||||
}; |
||||
|
||||
sdhi3_pins_uhs: sd3_uhs { |
||||
groups = "sdhi3_data4", "sdhi3_ctrl"; |
||||
function = "sdhi3"; |
||||
power-source = <1800>; |
||||
}; |
||||
|
||||
sound_pins: sound { |
||||
groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a"; |
||||
function = "ssi"; |
||||
}; |
||||
|
||||
sound_clk_pins: sound_clk { |
||||
groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clk_c_a", |
||||
"audio_clkout_a", "audio_clkout3_a"; |
||||
function = "audio_clk"; |
||||
}; |
||||
|
||||
usb0_pins: usb0 { |
||||
groups = "usb0"; |
||||
function = "usb0"; |
||||
}; |
||||
|
||||
usb1_pins: usb1 { |
||||
mux { |
||||
groups = "usb1"; |
||||
function = "usb1"; |
||||
}; |
||||
|
||||
ovc { |
||||
pins = "GP_6_27"; |
||||
bias-pull-up; |
||||
}; |
||||
|
||||
pwen { |
||||
pins = "GP_6_26"; |
||||
bias-pull-down; |
||||
}; |
||||
}; |
||||
|
||||
usb2_pins: usb2 { |
||||
groups = "usb2"; |
||||
function = "usb2"; |
||||
}; |
||||
}; |
||||
|
||||
&scif1 { |
||||
pinctrl-0 = <&scif1_pins>; |
||||
pinctrl-names = "default"; |
||||
|
||||
uart-has-rtscts; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&scif2 { |
||||
pinctrl-0 = <&scif2_pins>; |
||||
pinctrl-names = "default"; |
||||
|
||||
status = "okay"; |
||||
}; |
||||
|
||||
&scif_clk { |
||||
clock-frequency = <14745600>; |
||||
}; |
||||
|
||||
&i2c2 { |
||||
pinctrl-0 = <&i2c2_pins>; |
||||
pinctrl-names = "default"; |
||||
|
||||
status = "okay"; |
||||
|
||||
clock-frequency = <100000>; |
||||
|
||||
ak4613: codec@10 { |
||||
compatible = "asahi-kasei,ak4613"; |
||||
#sound-dai-cells = <0>; |
||||
reg = <0x10>; |
||||
clocks = <&rcar_sound 3>; |
||||
|
||||
asahi-kasei,in1-single-end; |
||||
asahi-kasei,in2-single-end; |
||||
asahi-kasei,out1-single-end; |
||||
asahi-kasei,out2-single-end; |
||||
asahi-kasei,out3-single-end; |
||||
asahi-kasei,out4-single-end; |
||||
asahi-kasei,out5-single-end; |
||||
asahi-kasei,out6-single-end; |
||||
}; |
||||
|
||||
cs2000: clk_multiplier@4f { |
||||
#clock-cells = <0>; |
||||
compatible = "cirrus,cs2000-cp"; |
||||
reg = <0x4f>; |
||||
clocks = <&audio_clkout>, <&x12_clk>; |
||||
clock-names = "clk_in", "ref_clk"; |
||||
|
||||
assigned-clocks = <&cs2000>; |
||||
assigned-clock-rates = <24576000>; /* 1/1 divide */ |
||||
}; |
||||
}; |
||||
|
||||
&rcar_sound { |
||||
pinctrl-0 = <&sound_pins &sound_clk_pins>; |
||||
pinctrl-names = "default"; |
||||
|
||||
/* Single DAI */ |
||||
#sound-dai-cells = <0>; |
||||
|
||||
/* audio_clkout0/1/2/3 */ |
||||
#clock-cells = <1>; |
||||
clock-frequency = <11289600>; |
||||
|
||||
status = "okay"; |
||||
|
||||
/* update <audio_clk_b> to <cs2000> */ |
||||
clocks = <&cpg CPG_MOD 1005>, |
||||
<&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, |
||||
<&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, |
||||
<&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, |
||||
<&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, |
||||
<&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, |
||||
<&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, |
||||
<&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, |
||||
<&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, |
||||
<&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, |
||||
<&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, |
||||
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, |
||||
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, |
||||
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, |
||||
<&audio_clk_a>, <&cs2000>, |
||||
<&audio_clk_c>, |
||||
<&cpg CPG_CORE R8A7795_CLK_S0D4>; |
||||
|
||||
rcar_sound,dai { |
||||
dai0 { |
||||
playback = <&ssi0 &src0 &dvc0>; |
||||
capture = <&ssi1 &src1 &dvc1>; |
||||
}; |
||||
}; |
||||
}; |
||||
|
||||
&sata { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&sdhi0 { |
||||
pinctrl-0 = <&sdhi0_pins>; |
||||
pinctrl-1 = <&sdhi0_pins_uhs>; |
||||
pinctrl-names = "default", "state_uhs"; |
||||
|
||||
vmmc-supply = <&vcc_sdhi0>; |
||||
vqmmc-supply = <&vccq_sdhi0>; |
||||
cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; |
||||
wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; |
||||
bus-width = <4>; |
||||
sd-uhs-sdr50; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&sdhi2 { |
||||
/* used for on-board 8bit eMMC */ |
||||
pinctrl-0 = <&sdhi2_pins>; |
||||
pinctrl-1 = <&sdhi2_pins_uhs>; |
||||
pinctrl-names = "default", "state_uhs"; |
||||
|
||||
vmmc-supply = <®_3p3v>; |
||||
vqmmc-supply = <®_1p8v>; |
||||
bus-width = <8>; |
||||
non-removable; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&sdhi3 { |
||||
pinctrl-0 = <&sdhi3_pins>; |
||||
pinctrl-1 = <&sdhi3_pins_uhs>; |
||||
pinctrl-names = "default", "state_uhs"; |
||||
|
||||
vmmc-supply = <&vcc_sdhi3>; |
||||
vqmmc-supply = <&vccq_sdhi3>; |
||||
cd-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; |
||||
wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; |
||||
bus-width = <4>; |
||||
sd-uhs-sdr50; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&ssi1 { |
||||
shared-pin; |
||||
}; |
||||
|
||||
&wdt0 { |
||||
timeout-sec = <60>; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&audio_clk_a { |
||||
clock-frequency = <22579200>; |
||||
}; |
||||
|
||||
&i2c_dvfs { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&avb { |
||||
pinctrl-0 = <&avb_pins>; |
||||
pinctrl-names = "default"; |
||||
renesas,no-ether-link; |
||||
phy-handle = <&phy0>; |
||||
status = "okay"; |
||||
|
||||
phy0: ethernet-phy@0 { |
||||
rxc-skew-ps = <1500>; |
||||
reg = <0>; |
||||
interrupt-parent = <&gpio2>; |
||||
interrupts = <11 IRQ_TYPE_LEVEL_LOW>; |
||||
}; |
||||
}; |
||||
|
||||
&xhci0 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&usb2_phy0 { |
||||
pinctrl-0 = <&usb0_pins>; |
||||
pinctrl-names = "default"; |
||||
|
||||
vbus-supply = <&vbus0_usb2>; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&usb2_phy1 { |
||||
pinctrl-0 = <&usb1_pins>; |
||||
pinctrl-names = "default"; |
||||
|
||||
status = "okay"; |
||||
}; |
||||
|
||||
&usb2_phy2 { |
||||
pinctrl-0 = <&usb2_pins>; |
||||
pinctrl-names = "default"; |
||||
|
||||
status = "okay"; |
||||
}; |
||||
|
||||
&ehci0 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&ehci1 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&ehci2 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&ohci0 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&ohci1 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&ohci2 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&hsusb { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&pcie_bus_clk { |
||||
clock-frequency = <100000000>; |
||||
}; |
||||
|
||||
&pciec0 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&pciec1 { |
||||
status = "okay"; |
||||
}; |
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,188 @@ |
||||
/* |
||||
* Device Tree Source for the M3ULCB (R-Car Starter Kit Pro) board |
||||
* |
||||
* Copyright (C) 2016 Renesas Electronics Corp. |
||||
* Copyright (C) 2016 Cogent Embedded, Inc. |
||||
* |
||||
* This file is licensed under the terms of the GNU General Public License |
||||
* version 2. This program is licensed "as is" without any warranty of any |
||||
* kind, whether express or implied. |
||||
*/ |
||||
|
||||
/dts-v1/; |
||||
#include "r8a7796.dtsi" |
||||
#include <dt-bindings/gpio/gpio.h> |
||||
#include <dt-bindings/input/input.h> |
||||
|
||||
/ { |
||||
model = "Renesas M3ULCB board based on r8a7796"; |
||||
compatible = "renesas,m3ulcb", "renesas,r8a7796"; |
||||
|
||||
aliases { |
||||
serial0 = &scif2; |
||||
}; |
||||
|
||||
chosen { |
||||
stdout-path = "serial0:115200n8"; |
||||
}; |
||||
|
||||
memory@48000000 { |
||||
device_type = "memory"; |
||||
/* first 128MB is reserved for secure area. */ |
||||
reg = <0x0 0x48000000 0x0 0x38000000>; |
||||
}; |
||||
|
||||
leds { |
||||
compatible = "gpio-leds"; |
||||
|
||||
led5 { |
||||
gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>; |
||||
}; |
||||
led6 { |
||||
gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; |
||||
}; |
||||
}; |
||||
|
||||
keyboard { |
||||
compatible = "gpio-keys"; |
||||
|
||||
key-1 { |
||||
linux,code = <KEY_1>; |
||||
label = "SW3"; |
||||
wakeup-source; |
||||
debounce-interval = <20>; |
||||
gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; |
||||
}; |
||||
}; |
||||
|
||||
reg_1p8v: regulator0 { |
||||
compatible = "regulator-fixed"; |
||||
regulator-name = "fixed-1.8V"; |
||||
regulator-min-microvolt = <1800000>; |
||||
regulator-max-microvolt = <1800000>; |
||||
regulator-boot-on; |
||||
regulator-always-on; |
||||
}; |
||||
|
||||
reg_3p3v: regulator1 { |
||||
compatible = "regulator-fixed"; |
||||
regulator-name = "fixed-3.3V"; |
||||
regulator-min-microvolt = <3300000>; |
||||
regulator-max-microvolt = <3300000>; |
||||
regulator-boot-on; |
||||
regulator-always-on; |
||||
}; |
||||
|
||||
vcc_sdhi0: regulator-vcc-sdhi0 { |
||||
compatible = "regulator-fixed"; |
||||
|
||||
regulator-name = "SDHI0 Vcc"; |
||||
regulator-min-microvolt = <3300000>; |
||||
regulator-max-microvolt = <3300000>; |
||||
|
||||
gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; |
||||
enable-active-high; |
||||
}; |
||||
|
||||
vccq_sdhi0: regulator-vccq-sdhi0 { |
||||
compatible = "regulator-gpio"; |
||||
|
||||
regulator-name = "SDHI0 VccQ"; |
||||
regulator-min-microvolt = <1800000>; |
||||
regulator-max-microvolt = <3300000>; |
||||
|
||||
gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; |
||||
gpios-states = <1>; |
||||
states = <3300000 1 |
||||
1800000 0>; |
||||
}; |
||||
}; |
||||
|
||||
&extal_clk { |
||||
clock-frequency = <16666666>; |
||||
}; |
||||
|
||||
&extalr_clk { |
||||
clock-frequency = <32768>; |
||||
}; |
||||
|
||||
&pfc { |
||||
pinctrl-0 = <&scif_clk_pins>; |
||||
pinctrl-names = "default"; |
||||
|
||||
scif2_pins: scif2 { |
||||
groups = "scif2_data_a"; |
||||
function = "scif2"; |
||||
}; |
||||
|
||||
scif_clk_pins: scif_clk { |
||||
groups = "scif_clk_a"; |
||||
function = "scif_clk"; |
||||
}; |
||||
|
||||
sdhi0_pins: sd0 { |
||||
groups = "sdhi0_data4", "sdhi0_ctrl"; |
||||
function = "sdhi0"; |
||||
power-source = <3300>; |
||||
}; |
||||
|
||||
sdhi0_pins_uhs: sd0_uhs { |
||||
groups = "sdhi0_data4", "sdhi0_ctrl"; |
||||
function = "sdhi0"; |
||||
power-source = <1800>; |
||||
}; |
||||
|
||||
sdhi2_pins: sd2 { |
||||
groups = "sdhi2_data8", "sdhi2_ctrl"; |
||||
function = "sdhi2"; |
||||
power-source = <3300>; |
||||
}; |
||||
|
||||
sdhi2_pins_uhs: sd2_uhs { |
||||
groups = "sdhi2_data8", "sdhi2_ctrl"; |
||||
function = "sdhi2"; |
||||
power-source = <1800>; |
||||
}; |
||||
}; |
||||
|
||||
&sdhi0 { |
||||
pinctrl-0 = <&sdhi0_pins>; |
||||
pinctrl-1 = <&sdhi0_pins_uhs>; |
||||
pinctrl-names = "default", "state_uhs"; |
||||
|
||||
vmmc-supply = <&vcc_sdhi0>; |
||||
vqmmc-supply = <&vccq_sdhi0>; |
||||
cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; |
||||
bus-width = <4>; |
||||
sd-uhs-sdr50; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&sdhi2 { |
||||
/* used for on-board 8bit eMMC */ |
||||
pinctrl-0 = <&sdhi2_pins>; |
||||
pinctrl-1 = <&sdhi2_pins_uhs>; |
||||
pinctrl-names = "default", "state_uhs"; |
||||
|
||||
vmmc-supply = <®_3p3v>; |
||||
vqmmc-supply = <®_1p8v>; |
||||
bus-width = <8>; |
||||
non-removable; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&scif2 { |
||||
pinctrl-0 = <&scif2_pins>; |
||||
pinctrl-names = "default"; |
||||
|
||||
status = "okay"; |
||||
}; |
||||
|
||||
&scif_clk { |
||||
clock-frequency = <14745600>; |
||||
}; |
||||
|
||||
&wdt0 { |
||||
timeout-sec = <60>; |
||||
status = "okay"; |
||||
}; |
||||
@ -0,0 +1,269 @@ |
||||
/* |
||||
* Device Tree Source for the Salvator-X board |
||||
* |
||||
* Copyright (C) 2016 Renesas Electronics Corp. |
||||
* |
||||
* This file is licensed under the terms of the GNU General Public License |
||||
* version 2. This program is licensed "as is" without any warranty of any |
||||
* kind, whether express or implied. |
||||
*/ |
||||
|
||||
/dts-v1/; |
||||
#include "r8a7796.dtsi" |
||||
#include <dt-bindings/gpio/gpio.h> |
||||
|
||||
/ { |
||||
model = "Renesas Salvator-X board based on r8a7796"; |
||||
compatible = "renesas,salvator-x", "renesas,r8a7796"; |
||||
|
||||
aliases { |
||||
serial0 = &scif2; |
||||
serial1 = &scif1; |
||||
ethernet0 = &avb; |
||||
}; |
||||
|
||||
chosen { |
||||
bootargs = "ignore_loglevel"; |
||||
stdout-path = "serial0:115200n8"; |
||||
}; |
||||
|
||||
memory@48000000 { |
||||
device_type = "memory"; |
||||
/* first 128MB is reserved for secure area. */ |
||||
reg = <0x0 0x48000000 0x0 0x78000000>; |
||||
}; |
||||
|
||||
memory@600000000 { |
||||
device_type = "memory"; |
||||
reg = <0x6 0x00000000 0x0 0x80000000>; |
||||
}; |
||||
|
||||
reg_1p8v: regulator0 { |
||||
compatible = "regulator-fixed"; |
||||
regulator-name = "fixed-1.8V"; |
||||
regulator-min-microvolt = <1800000>; |
||||
regulator-max-microvolt = <1800000>; |
||||
regulator-boot-on; |
||||
regulator-always-on; |
||||
}; |
||||
|
||||
reg_3p3v: regulator1 { |
||||
compatible = "regulator-fixed"; |
||||
regulator-name = "fixed-3.3V"; |
||||
regulator-min-microvolt = <3300000>; |
||||
regulator-max-microvolt = <3300000>; |
||||
regulator-boot-on; |
||||
regulator-always-on; |
||||
}; |
||||
|
||||
vcc_sdhi0: regulator-vcc-sdhi0 { |
||||
compatible = "regulator-fixed"; |
||||
|
||||
regulator-name = "SDHI0 Vcc"; |
||||
regulator-min-microvolt = <3300000>; |
||||
regulator-max-microvolt = <3300000>; |
||||
|
||||
gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; |
||||
enable-active-high; |
||||
}; |
||||
|
||||
vccq_sdhi0: regulator-vccq-sdhi0 { |
||||
compatible = "regulator-gpio"; |
||||
|
||||
regulator-name = "SDHI0 VccQ"; |
||||
regulator-min-microvolt = <1800000>; |
||||
regulator-max-microvolt = <3300000>; |
||||
|
||||
gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; |
||||
gpios-states = <1>; |
||||
states = <3300000 1 |
||||
1800000 0>; |
||||
}; |
||||
|
||||
vcc_sdhi3: regulator-vcc-sdhi3 { |
||||
compatible = "regulator-fixed"; |
||||
|
||||
regulator-name = "SDHI3 Vcc"; |
||||
regulator-min-microvolt = <3300000>; |
||||
regulator-max-microvolt = <3300000>; |
||||
|
||||
gpio = <&gpio3 15 GPIO_ACTIVE_HIGH>; |
||||
enable-active-high; |
||||
}; |
||||
|
||||
vccq_sdhi3: regulator-vccq-sdhi3 { |
||||
compatible = "regulator-gpio"; |
||||
|
||||
regulator-name = "SDHI3 VccQ"; |
||||
regulator-min-microvolt = <1800000>; |
||||
regulator-max-microvolt = <3300000>; |
||||
|
||||
gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; |
||||
gpios-states = <1>; |
||||
states = <3300000 1 |
||||
1800000 0>; |
||||
}; |
||||
}; |
||||
|
||||
&pfc { |
||||
pinctrl-0 = <&scif_clk_pins>; |
||||
pinctrl-names = "default"; |
||||
|
||||
avb_pins: avb { |
||||
groups = "avb_mdc"; |
||||
function = "avb"; |
||||
}; |
||||
|
||||
scif1_pins: scif1 { |
||||
groups = "scif1_data_a", "scif1_ctrl"; |
||||
function = "scif1"; |
||||
}; |
||||
|
||||
scif2_pins: scif2 { |
||||
groups = "scif2_data_a"; |
||||
function = "scif2"; |
||||
}; |
||||
scif_clk_pins: scif_clk { |
||||
groups = "scif_clk_a"; |
||||
function = "scif_clk"; |
||||
}; |
||||
|
||||
i2c2_pins: i2c2 { |
||||
groups = "i2c2_a"; |
||||
function = "i2c2"; |
||||
}; |
||||
|
||||
sdhi0_pins: sd0 { |
||||
groups = "sdhi0_data4", "sdhi0_ctrl"; |
||||
function = "sdhi0"; |
||||
power-source = <3300>; |
||||
}; |
||||
|
||||
sdhi0_pins_uhs: sd0_uhs { |
||||
groups = "sdhi0_data4", "sdhi0_ctrl"; |
||||
function = "sdhi0"; |
||||
power-source = <1800>; |
||||
}; |
||||
|
||||
sdhi2_pins: sd2 { |
||||
groups = "sdhi2_data8", "sdhi2_ctrl"; |
||||
function = "sdhi2"; |
||||
power-source = <3300>; |
||||
}; |
||||
|
||||
sdhi2_pins_uhs: sd2_uhs { |
||||
groups = "sdhi2_data8", "sdhi2_ctrl"; |
||||
function = "sdhi2"; |
||||
power-source = <1800>; |
||||
}; |
||||
|
||||
sdhi3_pins: sd3 { |
||||
groups = "sdhi3_data4", "sdhi3_ctrl"; |
||||
function = "sdhi3"; |
||||
power-source = <3300>; |
||||
}; |
||||
|
||||
sdhi3_pins_uhs: sd3_uhs { |
||||
groups = "sdhi3_data4", "sdhi3_ctrl"; |
||||
function = "sdhi3"; |
||||
power-source = <1800>; |
||||
}; |
||||
}; |
||||
|
||||
&avb { |
||||
pinctrl-0 = <&avb_pins>; |
||||
pinctrl-names = "default"; |
||||
renesas,no-ether-link; |
||||
phy-handle = <&phy0>; |
||||
status = "okay"; |
||||
|
||||
phy0: ethernet-phy@0 { |
||||
rxc-skew-ps = <1500>; |
||||
reg = <0>; |
||||
interrupt-parent = <&gpio2>; |
||||
interrupts = <11 IRQ_TYPE_LEVEL_LOW>; |
||||
}; |
||||
}; |
||||
|
||||
&extal_clk { |
||||
clock-frequency = <16666666>; |
||||
}; |
||||
|
||||
&extalr_clk { |
||||
clock-frequency = <32768>; |
||||
}; |
||||
|
||||
&sdhi0 { |
||||
pinctrl-0 = <&sdhi0_pins>; |
||||
pinctrl-1 = <&sdhi0_pins_uhs>; |
||||
pinctrl-names = "default", "state_uhs"; |
||||
|
||||
vmmc-supply = <&vcc_sdhi0>; |
||||
vqmmc-supply = <&vccq_sdhi0>; |
||||
cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; |
||||
wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; |
||||
bus-width = <4>; |
||||
sd-uhs-sdr50; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&sdhi2 { |
||||
/* used for on-board 8bit eMMC */ |
||||
pinctrl-0 = <&sdhi2_pins>; |
||||
pinctrl-1 = <&sdhi2_pins_uhs>; |
||||
pinctrl-names = "default", "state_uhs"; |
||||
|
||||
vmmc-supply = <®_3p3v>; |
||||
vqmmc-supply = <®_1p8v>; |
||||
bus-width = <8>; |
||||
non-removable; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&sdhi3 { |
||||
pinctrl-0 = <&sdhi3_pins>; |
||||
pinctrl-1 = <&sdhi3_pins_uhs>; |
||||
pinctrl-names = "default", "state_uhs"; |
||||
|
||||
vmmc-supply = <&vcc_sdhi3>; |
||||
vqmmc-supply = <&vccq_sdhi3>; |
||||
cd-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; |
||||
wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; |
||||
bus-width = <4>; |
||||
sd-uhs-sdr50; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&scif1 { |
||||
pinctrl-0 = <&scif1_pins>; |
||||
pinctrl-names = "default"; |
||||
|
||||
uart-has-rtscts; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&scif2 { |
||||
pinctrl-0 = <&scif2_pins>; |
||||
pinctrl-names = "default"; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&scif_clk { |
||||
clock-frequency = <14745600>; |
||||
}; |
||||
|
||||
&i2c2 { |
||||
pinctrl-0 = <&i2c2_pins>; |
||||
pinctrl-names = "default"; |
||||
|
||||
status = "okay"; |
||||
}; |
||||
|
||||
&wdt0 { |
||||
timeout-sec = <60>; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&i2c_dvfs { |
||||
status = "okay"; |
||||
}; |
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,15 @@ |
||||
if TARGET_ULCB |
||||
|
||||
config SYS_SOC |
||||
default "rmobile" |
||||
|
||||
config SYS_BOARD |
||||
default "ulcb" |
||||
|
||||
config SYS_VENDOR |
||||
default "renesas" |
||||
|
||||
config SYS_CONFIG_NAME |
||||
default "ulcb" |
||||
|
||||
endif |
||||
@ -0,0 +1,7 @@ |
||||
ULCB BOARD |
||||
M: Marek Vasut <marek.vasut+renesas@gmail.com> |
||||
S: Maintained |
||||
F: board/renesas/ulcb/ |
||||
F: include/configs/ulcb.h |
||||
F: configs/r8a7795_ulcb_defconfig |
||||
F: configs/r8a7796_ulcb_defconfig |
||||
@ -0,0 +1,9 @@ |
||||
#
|
||||
# board/renesas/ulcb/Makefile
|
||||
#
|
||||
# Copyright (C) 2017 Renesas Electronics Corporation
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y := ulcb.o cpld.o ../rcar-common/common.o
|
||||
@ -0,0 +1,167 @@ |
||||
/*
|
||||
* ULCB board CPLD access support |
||||
* |
||||
* Copyright (C) 2017 Renesas Electronics Corporation |
||||
* Copyright (C) 2017 Cogent Embedded, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <spi.h> |
||||
#include <asm/io.h> |
||||
#include <asm/gpio.h> |
||||
|
||||
#define SCLK GPIO_GP_6_8 |
||||
#define SSTBZ GPIO_GP_2_3 |
||||
#define MOSI GPIO_GP_6_7 |
||||
#define MISO GPIO_GP_6_10 |
||||
|
||||
#define CPLD_ADDR_MODE 0x00 /* RW */ |
||||
#define CPLD_ADDR_MUX 0x02 /* RW */ |
||||
#define CPLD_ADDR_DIPSW6 0x08 /* R */ |
||||
#define CPLD_ADDR_RESET 0x80 /* RW */ |
||||
#define CPLD_ADDR_VERSION 0xFF /* R */ |
||||
|
||||
static int cpld_initialized; |
||||
|
||||
int spi_cs_is_valid(unsigned int bus, unsigned int cs) |
||||
{ |
||||
/* Always valid */ |
||||
return 1; |
||||
} |
||||
|
||||
void spi_cs_activate(struct spi_slave *slave) |
||||
{ |
||||
/* Always active */ |
||||
} |
||||
|
||||
void spi_cs_deactivate(struct spi_slave *slave) |
||||
{ |
||||
/* Always active */ |
||||
} |
||||
|
||||
void ulcb_softspi_sda(int set) |
||||
{ |
||||
gpio_set_value(MOSI, set); |
||||
} |
||||
|
||||
void ulcb_softspi_scl(int set) |
||||
{ |
||||
gpio_set_value(SCLK, set); |
||||
} |
||||
|
||||
unsigned char ulcb_softspi_read(void) |
||||
{ |
||||
return !!gpio_get_value(MISO); |
||||
} |
||||
|
||||
static void cpld_rw(u8 write) |
||||
{ |
||||
gpio_set_value(MOSI, write); |
||||
gpio_set_value(SSTBZ, 0); |
||||
gpio_set_value(SCLK, 1); |
||||
gpio_set_value(SCLK, 0); |
||||
gpio_set_value(SSTBZ, 1); |
||||
} |
||||
|
||||
static u32 cpld_read(u8 addr) |
||||
{ |
||||
u32 data = 0; |
||||
|
||||
spi_xfer(NULL, 8, &addr, NULL, SPI_XFER_BEGIN | SPI_XFER_END); |
||||
|
||||
cpld_rw(0); |
||||
|
||||
spi_xfer(NULL, 32, NULL, &data, SPI_XFER_BEGIN | SPI_XFER_END); |
||||
|
||||
return swab32(data); |
||||
} |
||||
|
||||
static void cpld_write(u8 addr, u32 data) |
||||
{ |
||||
data = swab32(data); |
||||
|
||||
spi_xfer(NULL, 32, &data, NULL, SPI_XFER_BEGIN | SPI_XFER_END); |
||||
|
||||
spi_xfer(NULL, 8, NULL, &addr, SPI_XFER_BEGIN | SPI_XFER_END); |
||||
|
||||
cpld_rw(1); |
||||
} |
||||
|
||||
static void cpld_init(void) |
||||
{ |
||||
if (cpld_initialized) |
||||
return; |
||||
|
||||
/* PULL-UP on MISO line */ |
||||
setbits_le32(PFC_PUEN5, PUEN_SSI_SDATA4); |
||||
|
||||
gpio_request(SCLK, NULL); |
||||
gpio_request(SSTBZ, NULL); |
||||
gpio_request(MOSI, NULL); |
||||
gpio_request(MISO, NULL); |
||||
|
||||
gpio_direction_output(SCLK, 0); |
||||
gpio_direction_output(SSTBZ, 1); |
||||
gpio_direction_output(MOSI, 0); |
||||
gpio_direction_input(MISO); |
||||
|
||||
/* Dummy read */ |
||||
cpld_read(CPLD_ADDR_VERSION); |
||||
|
||||
cpld_initialized = 1; |
||||
} |
||||
|
||||
static int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
||||
{ |
||||
u32 addr, val; |
||||
|
||||
cpld_init(); |
||||
|
||||
if (argc == 2 && strcmp(argv[1], "info") == 0) { |
||||
printf("CPLD version:\t\t\t0x%08x\n", |
||||
cpld_read(CPLD_ADDR_VERSION)); |
||||
printf("H3 Mode setting (MD0..28):\t0x%08x\n", |
||||
cpld_read(CPLD_ADDR_MODE)); |
||||
printf("Multiplexer settings:\t\t0x%08x\n", |
||||
cpld_read(CPLD_ADDR_MUX)); |
||||
printf("DIPSW (SW6):\t\t\t0x%08x\n", |
||||
cpld_read(CPLD_ADDR_DIPSW6)); |
||||
return 0; |
||||
} |
||||
|
||||
if (argc < 3) |
||||
return CMD_RET_USAGE; |
||||
|
||||
addr = simple_strtoul(argv[2], NULL, 16); |
||||
if (!(addr == CPLD_ADDR_VERSION || addr == CPLD_ADDR_MODE || |
||||
addr == CPLD_ADDR_MUX || addr == CPLD_ADDR_DIPSW6 || |
||||
addr == CPLD_ADDR_RESET)) { |
||||
printf("Invalid CPLD register address\n"); |
||||
return CMD_RET_USAGE; |
||||
} |
||||
|
||||
if (argc == 3 && strcmp(argv[1], "read") == 0) { |
||||
printf("0x%x\n", cpld_read(addr)); |
||||
} else if (argc == 4 && strcmp(argv[1], "write") == 0) { |
||||
val = simple_strtoul(argv[3], NULL, 16); |
||||
cpld_write(addr, val); |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
U_BOOT_CMD( |
||||
cpld, 4, 1, do_cpld, |
||||
"CPLD access", |
||||
"info\n" |
||||
"cpld read addr\n" |
||||
"cpld write addr val\n" |
||||
); |
||||
|
||||
void reset_cpu(ulong addr) |
||||
{ |
||||
cpld_init(); |
||||
cpld_write(CPLD_ADDR_RESET, 1); |
||||
} |
||||
@ -0,0 +1,257 @@ |
||||
/*
|
||||
* board/renesas/ulcb/ulcb.c |
||||
* This file is ULCB board support. |
||||
* |
||||
* Copyright (C) 2017 Renesas Electronics Corporation |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <malloc.h> |
||||
#include <netdev.h> |
||||
#include <dm.h> |
||||
#include <dm/platform_data/serial_sh.h> |
||||
#include <asm/processor.h> |
||||
#include <asm/mach-types.h> |
||||
#include <asm/io.h> |
||||
#include <linux/errno.h> |
||||
#include <asm/arch/sys_proto.h> |
||||
#include <asm/gpio.h> |
||||
#include <asm/arch/gpio.h> |
||||
#include <asm/arch/rmobile.h> |
||||
#include <asm/arch/rcar-mstp.h> |
||||
#include <asm/arch/sh_sdhi.h> |
||||
#include <i2c.h> |
||||
#include <mmc.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
#define CPGWPCR 0xE6150904 |
||||
#define CPGWPR 0xE615090C |
||||
|
||||
#define CLK2MHZ(clk) (clk / 1000 / 1000) |
||||
void s_init(void) |
||||
{ |
||||
struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; |
||||
struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; |
||||
|
||||
/* Watchdog init */ |
||||
writel(0xA5A5A500, &rwdt->rwtcsra); |
||||
writel(0xA5A5A500, &swdt->swtcsra); |
||||
|
||||
writel(0xA5A50000, CPGWPCR); |
||||
writel(0xFFFFFFFF, CPGWPR); |
||||
} |
||||
|
||||
#define GSX_MSTP112 BIT(12) /* 3DG */ |
||||
#define TMU0_MSTP125 BIT(25) /* secure */ |
||||
#define TMU1_MSTP124 BIT(24) /* non-secure */ |
||||
#define SCIF2_MSTP310 BIT(10) /* SCIF2 */ |
||||
#define ETHERAVB_MSTP812 BIT(12) |
||||
#define DVFS_MSTP926 BIT(26) |
||||
#define SD0_MSTP314 BIT(14) |
||||
#define SD1_MSTP313 BIT(13) |
||||
#define SD2_MSTP312 BIT(12) /* either MMC0 */ |
||||
|
||||
#define SD0CKCR 0xE6150074 |
||||
#define SD1CKCR 0xE6150078 |
||||
#define SD2CKCR 0xE6150268 |
||||
#define SD3CKCR 0xE615026C |
||||
|
||||
int board_early_init_f(void) |
||||
{ |
||||
/* TMU0,1 */ /* which use ? */ |
||||
mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125 | TMU1_MSTP124); |
||||
/* SCIF2 */ |
||||
mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SCIF2_MSTP310); |
||||
/* EHTERAVB */ |
||||
mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHERAVB_MSTP812); |
||||
/* eMMC */ |
||||
mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD1_MSTP313 | SD2_MSTP312); |
||||
/* SDHI0 */ |
||||
mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD0_MSTP314); |
||||
|
||||
writel(0, SD0CKCR); |
||||
writel(0, SD1CKCR); |
||||
writel(0, SD2CKCR); |
||||
writel(0, SD3CKCR); |
||||
|
||||
#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH) |
||||
/* DVFS for reset */ |
||||
mstp_clrbits_le32(MSTPSR9, SMSTPCR9, DVFS_MSTP926); |
||||
#endif |
||||
return 0; |
||||
} |
||||
|
||||
/* SYSC */ |
||||
/* R/- 32 Power status register 2(3DG) */ |
||||
#define SYSC_PWRSR2 0xE6180100 |
||||
/* -/W 32 Power resume control register 2 (3DG) */ |
||||
#define SYSC_PWRONCR2 0xE618010C |
||||
|
||||
int board_init(void) |
||||
{ |
||||
/* adress of boot parameters */ |
||||
gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000; |
||||
|
||||
/* Init PFC controller */ |
||||
#if defined(CONFIG_R8A7795) |
||||
r8a7795_pinmux_init(); |
||||
#elif defined(CONFIG_R8A7796) |
||||
r8a7796_pinmux_init(); |
||||
#endif |
||||
|
||||
/* USB1 pull-up */ |
||||
setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN); |
||||
|
||||
#ifdef CONFIG_RAVB |
||||
/* EtherAVB Enable */ |
||||
/* GPSR2 */ |
||||
gpio_request(GPIO_GFN_AVB_AVTP_CAPTURE_A, NULL); |
||||
gpio_request(GPIO_GFN_AVB_AVTP_MATCH_A, NULL); |
||||
gpio_request(GPIO_GFN_AVB_LINK, NULL); |
||||
gpio_request(GPIO_GFN_AVB_PHY_INT, NULL); |
||||
gpio_request(GPIO_GFN_AVB_MAGIC, NULL); |
||||
gpio_request(GPIO_GFN_AVB_MDC, NULL); |
||||
|
||||
/* IPSR0 */ |
||||
gpio_request(GPIO_IFN_AVB_MDC, NULL); |
||||
gpio_request(GPIO_IFN_AVB_MAGIC, NULL); |
||||
gpio_request(GPIO_IFN_AVB_PHY_INT, NULL); |
||||
gpio_request(GPIO_IFN_AVB_LINK, NULL); |
||||
gpio_request(GPIO_IFN_AVB_AVTP_MATCH_A, NULL); |
||||
gpio_request(GPIO_IFN_AVB_AVTP_CAPTURE_A, NULL); |
||||
/* IPSR1 */ |
||||
gpio_request(GPIO_FN_AVB_AVTP_PPS, NULL); |
||||
/* IPSR2 */ |
||||
gpio_request(GPIO_FN_AVB_AVTP_MATCH_B, NULL); |
||||
/* IPSR3 */ |
||||
gpio_request(GPIO_FN_AVB_AVTP_CAPTURE_B, NULL); |
||||
|
||||
/* AVB_PHY_RST */ |
||||
gpio_request(GPIO_GP_2_10, NULL); |
||||
gpio_direction_output(GPIO_GP_2_10, 0); |
||||
mdelay(20); |
||||
gpio_set_value(GPIO_GP_2_10, 1); |
||||
udelay(1); |
||||
#endif |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static struct eth_pdata salvator_x_ravb_platdata = { |
||||
.iobase = 0xE6800000, |
||||
.phy_interface = 0, |
||||
.max_speed = 1000, |
||||
}; |
||||
|
||||
U_BOOT_DEVICE(salvator_x_ravb) = { |
||||
.name = "ravb", |
||||
.platdata = &salvator_x_ravb_platdata, |
||||
}; |
||||
|
||||
#ifdef CONFIG_SH_SDHI |
||||
int board_mmc_init(bd_t *bis) |
||||
{ |
||||
int ret = -ENODEV; |
||||
|
||||
/* SDHI0 */ |
||||
gpio_request(GPIO_GFN_SD0_DAT0, NULL); |
||||
gpio_request(GPIO_GFN_SD0_DAT1, NULL); |
||||
gpio_request(GPIO_GFN_SD0_DAT2, NULL); |
||||
gpio_request(GPIO_GFN_SD0_DAT3, NULL); |
||||
gpio_request(GPIO_GFN_SD0_CLK, NULL); |
||||
gpio_request(GPIO_GFN_SD0_CMD, NULL); |
||||
gpio_request(GPIO_GFN_SD0_CD, NULL); |
||||
gpio_request(GPIO_GFN_SD0_WP, NULL); |
||||
|
||||
gpio_request(GPIO_GP_5_2, NULL); |
||||
gpio_request(GPIO_GP_5_1, NULL); |
||||
gpio_direction_output(GPIO_GP_5_2, 1); /* power on */ |
||||
gpio_direction_output(GPIO_GP_5_1, 1); /* 1: 3.3V, 0: 1.8V */ |
||||
|
||||
ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0, |
||||
SH_SDHI_QUIRK_64BIT_BUF); |
||||
if (ret) |
||||
return ret; |
||||
|
||||
/* SDHI1/SDHI2 eMMC */ |
||||
gpio_request(GPIO_GFN_SD1_DAT0, NULL); |
||||
gpio_request(GPIO_GFN_SD1_DAT1, NULL); |
||||
gpio_request(GPIO_GFN_SD1_DAT2, NULL); |
||||
gpio_request(GPIO_GFN_SD1_DAT3, NULL); |
||||
gpio_request(GPIO_GFN_SD2_DAT0, NULL); |
||||
gpio_request(GPIO_GFN_SD2_DAT1, NULL); |
||||
gpio_request(GPIO_GFN_SD2_DAT2, NULL); |
||||
gpio_request(GPIO_GFN_SD2_DAT3, NULL); |
||||
gpio_request(GPIO_GFN_SD2_CLK, NULL); |
||||
#if defined(CONFIG_R8A7795) |
||||
gpio_request(GPIO_GFN_SD2_CMD, NULL); |
||||
#elif defined(CONFIG_R8A7796) |
||||
gpio_request(GPIO_FN_SD2_CMD, NULL); |
||||
#else |
||||
#error Only R8A7795 and R87796 is supported |
||||
#endif |
||||
gpio_request(GPIO_GP_5_3, NULL); |
||||
gpio_request(GPIO_GP_5_9, NULL); |
||||
gpio_direction_output(GPIO_GP_5_3, 0); /* 1: 3.3V, 0: 1.8V */ |
||||
gpio_direction_output(GPIO_GP_5_9, 0); /* 1: 3.3V, 0: 1.8V */ |
||||
|
||||
ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 1, |
||||
SH_SDHI_QUIRK_64BIT_BUF); |
||||
|
||||
return ret; |
||||
} |
||||
#endif |
||||
|
||||
int dram_init(void) |
||||
{ |
||||
gd->ram_size = PHYS_SDRAM_1_SIZE; |
||||
#if (CONFIG_NR_DRAM_BANKS >= 2) |
||||
gd->ram_size += PHYS_SDRAM_2_SIZE; |
||||
#endif |
||||
#if (CONFIG_NR_DRAM_BANKS >= 3) |
||||
gd->ram_size += PHYS_SDRAM_3_SIZE; |
||||
#endif |
||||
#if (CONFIG_NR_DRAM_BANKS >= 4) |
||||
gd->ram_size += PHYS_SDRAM_4_SIZE; |
||||
#endif |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int dram_init_banksize(void) |
||||
{ |
||||
gd->bd->bi_dram[0].start = PHYS_SDRAM_1; |
||||
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; |
||||
#if (CONFIG_NR_DRAM_BANKS >= 2) |
||||
gd->bd->bi_dram[1].start = PHYS_SDRAM_2; |
||||
gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; |
||||
#endif |
||||
#if (CONFIG_NR_DRAM_BANKS >= 3) |
||||
gd->bd->bi_dram[2].start = PHYS_SDRAM_3; |
||||
gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; |
||||
#endif |
||||
#if (CONFIG_NR_DRAM_BANKS >= 4) |
||||
gd->bd->bi_dram[3].start = PHYS_SDRAM_4; |
||||
gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; |
||||
#endif |
||||
return 0; |
||||
} |
||||
|
||||
const struct rmobile_sysinfo sysinfo = { |
||||
CONFIG_RCAR_BOARD_STRING |
||||
}; |
||||
|
||||
static const struct sh_serial_platdata serial_platdata = { |
||||
.base = SCIF2_BASE, |
||||
.type = PORT_SCIF, |
||||
.clk = CONFIG_SH_SCIF_CLK_FREQ, |
||||
.clk_mode = INT_CLK, |
||||
}; |
||||
|
||||
U_BOOT_DEVICE(salvator_x_scif2) = { |
||||
.name = "serial_sh", |
||||
.platdata = &serial_platdata, |
||||
}; |
||||
@ -0,0 +1,27 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_ARCH_RMOBILE=y |
||||
CONFIG_SYS_MALLOC_F_LEN=0x2000 |
||||
CONFIG_RCAR_GEN3=y |
||||
CONFIG_TARGET_ULCB=y |
||||
CONFIG_DEFAULT_DEVICE_TREE="r8a7795-h3ulcb" |
||||
CONFIG_SMBIOS_PRODUCT_NAME="" |
||||
CONFIG_DEFAULT_FDT_FILE="r8a7795-h3ulcb.dtb" |
||||
CONFIG_VERSION_VARIABLE=y |
||||
CONFIG_CMD_BOOTZ=y |
||||
# CONFIG_CMD_IMLS is not set |
||||
CONFIG_CMD_MMC=y |
||||
CONFIG_CMD_USB=y |
||||
CONFIG_CMD_DHCP=y |
||||
CONFIG_CMD_MII=y |
||||
CONFIG_CMD_PING=y |
||||
CONFIG_OF_CONTROL=y |
||||
CONFIG_CLK=y |
||||
CONFIG_CLK_RENESAS=y |
||||
CONFIG_SH_SDHI=y |
||||
CONFIG_DM_ETH=y |
||||
CONFIG_RENESAS_RAVB=y |
||||
CONFIG_SCIF_CONSOLE=y |
||||
CONFIG_USB=y |
||||
CONFIG_USB_EHCI_HCD=y |
||||
CONFIG_USB_STORAGE=y |
||||
CONFIG_SMBIOS_MANUFACTURER="" |
||||
@ -0,0 +1,28 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_ARCH_RMOBILE=y |
||||
CONFIG_SYS_MALLOC_F_LEN=0x2000 |
||||
CONFIG_RCAR_GEN3=y |
||||
CONFIG_R8A7796=y |
||||
CONFIG_TARGET_ULCB=y |
||||
CONFIG_DEFAULT_DEVICE_TREE="r8a7796-m3ulcb" |
||||
CONFIG_SMBIOS_PRODUCT_NAME="" |
||||
CONFIG_DEFAULT_FDT_FILE="r8a7796-m3ulcb.dtb" |
||||
CONFIG_VERSION_VARIABLE=y |
||||
CONFIG_CMD_BOOTZ=y |
||||
# CONFIG_CMD_IMLS is not set |
||||
CONFIG_CMD_MMC=y |
||||
CONFIG_CMD_USB=y |
||||
CONFIG_CMD_DHCP=y |
||||
CONFIG_CMD_MII=y |
||||
CONFIG_CMD_PING=y |
||||
CONFIG_OF_CONTROL=y |
||||
CONFIG_CLK=y |
||||
CONFIG_CLK_RENESAS=y |
||||
CONFIG_SH_SDHI=y |
||||
CONFIG_DM_ETH=y |
||||
CONFIG_RENESAS_RAVB=y |
||||
CONFIG_SCIF_CONSOLE=y |
||||
CONFIG_USB=y |
||||
CONFIG_USB_EHCI_HCD=y |
||||
CONFIG_USB_STORAGE=y |
||||
CONFIG_SMBIOS_MANUFACTURER="" |
||||
@ -0,0 +1,13 @@ |
||||
config CLK_RENESAS |
||||
bool "Renesas clock drivers" |
||||
depends on CLK && ARCH_RMOBILE |
||||
help |
||||
Enable support for clock present on Renesas RCar SoCs. |
||||
|
||||
config CLK_RCAR_GEN3 |
||||
bool "Renesas RCar Gen3 R8A7795/R8A7796 clock driver" |
||||
def_bool y if RCAR_GEN3 |
||||
depends on CLK_RENESAS |
||||
help |
||||
Enable this to support the clocks on Renesas RCar Gen3 |
||||
R8A7795 and R8A7796 SoC. |
||||
@ -0,0 +1 @@ |
||||
obj-$(CONFIG_CLK_RCAR_GEN3) += clk-rcar-gen3.o
|
||||
@ -0,0 +1,951 @@ |
||||
/*
|
||||
* Renesas RCar Gen3 R8A7795/R8A7796 CPG MSSR driver |
||||
* |
||||
* Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com> |
||||
* |
||||
* Based on the following driver from Linux kernel: |
||||
* r8a7796 Clock Pulse Generator / Module Standby and Software Reset |
||||
* |
||||
* Copyright (C) 2016 Glider bvba |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <clk-uclass.h> |
||||
#include <dm.h> |
||||
#include <errno.h> |
||||
#include <wait_bit.h> |
||||
#include <asm/io.h> |
||||
|
||||
#include <dt-bindings/clock/r8a7795-cpg-mssr.h> |
||||
#include <dt-bindings/clock/r8a7796-cpg-mssr.h> |
||||
|
||||
#define CPG_RST_MODEMR 0x0060 |
||||
|
||||
#define CPG_PLL0CR 0x00d8 |
||||
#define CPG_PLL2CR 0x002c |
||||
#define CPG_PLL4CR 0x01f4 |
||||
|
||||
/*
|
||||
* Module Standby and Software Reset register offets. |
||||
* |
||||
* If the registers exist, these are valid for SH-Mobile, R-Mobile, |
||||
* R-Car Gen2, R-Car Gen3, and RZ/G1. |
||||
* These are NOT valid for R-Car Gen1 and RZ/A1! |
||||
*/ |
||||
|
||||
/*
|
||||
* Module Stop Status Register offsets |
||||
*/ |
||||
|
||||
static const u16 mstpsr[] = { |
||||
0x030, 0x038, 0x040, 0x048, 0x04C, 0x03C, 0x1C0, 0x1C4, |
||||
0x9A0, 0x9A4, 0x9A8, 0x9AC, |
||||
}; |
||||
|
||||
#define MSTPSR(i) mstpsr[i] |
||||
|
||||
|
||||
/*
|
||||
* System Module Stop Control Register offsets |
||||
*/ |
||||
|
||||
static const u16 smstpcr[] = { |
||||
0x130, 0x134, 0x138, 0x13C, 0x140, 0x144, 0x148, 0x14C, |
||||
0x990, 0x994, 0x998, 0x99C, |
||||
}; |
||||
|
||||
#define SMSTPCR(i) smstpcr[i] |
||||
|
||||
|
||||
/* Realtime Module Stop Control Register offsets */ |
||||
#define RMSTPCR(i) (smstpcr[i] - 0x20) |
||||
|
||||
/* Modem Module Stop Control Register offsets (r8a73a4) */ |
||||
#define MMSTPCR(i) (smstpcr[i] + 0x20) |
||||
|
||||
/* Software Reset Clearing Register offsets */ |
||||
#define SRSTCLR(i) (0x940 + (i) * 4) |
||||
|
||||
struct gen3_clk_priv { |
||||
void __iomem *base; |
||||
struct clk clk_extal; |
||||
struct clk clk_extalr; |
||||
const struct rcar_gen3_cpg_pll_config *cpg_pll_config; |
||||
const struct mssr_mod_clk *mod_clk; |
||||
u32 mod_clk_size; |
||||
}; |
||||
|
||||
/*
|
||||
* Definitions of CPG Core Clocks |
||||
* |
||||
* These include: |
||||
* - Clock outputs exported to DT |
||||
* - External input clocks |
||||
* - Internal CPG clocks |
||||
*/ |
||||
struct cpg_core_clk { |
||||
/* Common */ |
||||
const char *name; |
||||
unsigned int id; |
||||
unsigned int type; |
||||
/* Depending on type */ |
||||
unsigned int parent; /* Core Clocks only */ |
||||
unsigned int div; |
||||
unsigned int mult; |
||||
unsigned int offset; |
||||
}; |
||||
|
||||
enum clk_types { |
||||
/* Generic */ |
||||
CLK_TYPE_IN, /* External Clock Input */ |
||||
CLK_TYPE_FF, /* Fixed Factor Clock */ |
||||
|
||||
/* Custom definitions start here */ |
||||
CLK_TYPE_CUSTOM, |
||||
}; |
||||
|
||||
#define DEF_TYPE(_name, _id, _type...) \ |
||||
{ .name = _name, .id = _id, .type = _type } |
||||
#define DEF_BASE(_name, _id, _type, _parent...) \ |
||||
DEF_TYPE(_name, _id, _type, .parent = _parent) |
||||
|
||||
#define DEF_INPUT(_name, _id) \ |
||||
DEF_TYPE(_name, _id, CLK_TYPE_IN) |
||||
#define DEF_FIXED(_name, _id, _parent, _div, _mult) \ |
||||
DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult) |
||||
#define DEF_GEN3_SD(_name, _id, _parent, _offset) \ |
||||
DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset) |
||||
|
||||
/*
|
||||
* Definitions of Module Clocks |
||||
*/ |
||||
struct mssr_mod_clk { |
||||
const char *name; |
||||
unsigned int id; |
||||
unsigned int parent; /* Add MOD_CLK_BASE for Module Clocks */ |
||||
}; |
||||
|
||||
/* Convert from sparse base-100 to packed index space */ |
||||
#define MOD_CLK_PACK(x) ((x) - ((x) / 100) * (100 - 32)) |
||||
|
||||
#define MOD_CLK_ID(x) (MOD_CLK_BASE + MOD_CLK_PACK(x)) |
||||
|
||||
#define DEF_MOD(_name, _mod, _parent...) \ |
||||
{ .name = _name, .id = MOD_CLK_ID(_mod), .parent = _parent } |
||||
|
||||
enum rcar_gen3_clk_types { |
||||
CLK_TYPE_GEN3_MAIN = CLK_TYPE_CUSTOM, |
||||
CLK_TYPE_GEN3_PLL0, |
||||
CLK_TYPE_GEN3_PLL1, |
||||
CLK_TYPE_GEN3_PLL2, |
||||
CLK_TYPE_GEN3_PLL3, |
||||
CLK_TYPE_GEN3_PLL4, |
||||
CLK_TYPE_GEN3_SD, |
||||
CLK_TYPE_GEN3_R, |
||||
}; |
||||
|
||||
struct rcar_gen3_cpg_pll_config { |
||||
unsigned int extal_div; |
||||
unsigned int pll1_mult; |
||||
unsigned int pll3_mult; |
||||
}; |
||||
|
||||
enum clk_ids { |
||||
/* Core Clock Outputs exported to DT */ |
||||
LAST_DT_CORE_CLK = R8A7796_CLK_OSC, |
||||
|
||||
/* External Input Clocks */ |
||||
CLK_EXTAL, |
||||
CLK_EXTALR, |
||||
|
||||
/* Internal Core Clocks */ |
||||
CLK_MAIN, |
||||
CLK_PLL0, |
||||
CLK_PLL1, |
||||
CLK_PLL2, |
||||
CLK_PLL3, |
||||
CLK_PLL4, |
||||
CLK_PLL1_DIV2, |
||||
CLK_PLL1_DIV4, |
||||
CLK_S0, |
||||
CLK_S1, |
||||
CLK_S2, |
||||
CLK_S3, |
||||
CLK_SDSRC, |
||||
CLK_SSPSRC, |
||||
CLK_RINT, |
||||
|
||||
/* Module Clocks */ |
||||
MOD_CLK_BASE |
||||
}; |
||||
|
||||
static const struct cpg_core_clk gen3_core_clks[] = { |
||||
/* External Clock Inputs */ |
||||
DEF_INPUT("extal", CLK_EXTAL), |
||||
DEF_INPUT("extalr", CLK_EXTALR), |
||||
|
||||
/* Internal Core Clocks */ |
||||
DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL), |
||||
DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN), |
||||
DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN), |
||||
DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN), |
||||
DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN), |
||||
DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN), |
||||
|
||||
DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), |
||||
DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1), |
||||
DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1), |
||||
DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1), |
||||
DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1), |
||||
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), |
||||
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), |
||||
|
||||
/* Core Clock Outputs */ |
||||
DEF_FIXED("ztr", R8A7796_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), |
||||
DEF_FIXED("ztrd2", R8A7796_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), |
||||
DEF_FIXED("zt", R8A7796_CLK_ZT, CLK_PLL1_DIV2, 4, 1), |
||||
DEF_FIXED("zx", R8A7796_CLK_ZX, CLK_PLL1_DIV2, 2, 1), |
||||
DEF_FIXED("s0d1", R8A7796_CLK_S0D1, CLK_S0, 1, 1), |
||||
DEF_FIXED("s0d2", R8A7796_CLK_S0D2, CLK_S0, 2, 1), |
||||
DEF_FIXED("s0d3", R8A7796_CLK_S0D3, CLK_S0, 3, 1), |
||||
DEF_FIXED("s0d4", R8A7796_CLK_S0D4, CLK_S0, 4, 1), |
||||
DEF_FIXED("s0d6", R8A7796_CLK_S0D6, CLK_S0, 6, 1), |
||||
DEF_FIXED("s0d8", R8A7796_CLK_S0D8, CLK_S0, 8, 1), |
||||
DEF_FIXED("s0d12", R8A7796_CLK_S0D12, CLK_S0, 12, 1), |
||||
DEF_FIXED("s1d1", R8A7796_CLK_S1D1, CLK_S1, 1, 1), |
||||
DEF_FIXED("s1d2", R8A7796_CLK_S1D2, CLK_S1, 2, 1), |
||||
DEF_FIXED("s1d4", R8A7796_CLK_S1D4, CLK_S1, 4, 1), |
||||
DEF_FIXED("s2d1", R8A7796_CLK_S2D1, CLK_S2, 1, 1), |
||||
DEF_FIXED("s2d2", R8A7796_CLK_S2D2, CLK_S2, 2, 1), |
||||
DEF_FIXED("s2d4", R8A7796_CLK_S2D4, CLK_S2, 4, 1), |
||||
DEF_FIXED("s3d1", R8A7796_CLK_S3D1, CLK_S3, 1, 1), |
||||
DEF_FIXED("s3d2", R8A7796_CLK_S3D2, CLK_S3, 2, 1), |
||||
DEF_FIXED("s3d4", R8A7796_CLK_S3D4, CLK_S3, 4, 1), |
||||
|
||||
DEF_GEN3_SD("sd0", R8A7796_CLK_SD0, CLK_SDSRC, 0x074), |
||||
DEF_GEN3_SD("sd1", R8A7796_CLK_SD1, CLK_SDSRC, 0x078), |
||||
DEF_GEN3_SD("sd2", R8A7796_CLK_SD2, CLK_SDSRC, 0x268), |
||||
DEF_GEN3_SD("sd3", R8A7796_CLK_SD3, CLK_SDSRC, 0x26c), |
||||
|
||||
DEF_FIXED("cl", R8A7796_CLK_CL, CLK_PLL1_DIV2, 48, 1), |
||||
DEF_FIXED("cp", R8A7796_CLK_CP, CLK_EXTAL, 2, 1), |
||||
|
||||
/* NOTE: HDMI, CSI, CAN etc. clock are missing */ |
||||
|
||||
DEF_BASE("r", R8A7796_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT), |
||||
}; |
||||
|
||||
static const struct mssr_mod_clk r8a7795_mod_clks[] = { |
||||
DEF_MOD("fdp1-2", 117, R8A7795_CLK_S2D1), /* ES1.x */ |
||||
DEF_MOD("fdp1-1", 118, R8A7795_CLK_S0D1), |
||||
DEF_MOD("fdp1-0", 119, R8A7795_CLK_S0D1), |
||||
DEF_MOD("scif5", 202, R8A7795_CLK_S3D4), |
||||
DEF_MOD("scif4", 203, R8A7795_CLK_S3D4), |
||||
DEF_MOD("scif3", 204, R8A7795_CLK_S3D4), |
||||
DEF_MOD("scif1", 206, R8A7795_CLK_S3D4), |
||||
DEF_MOD("scif0", 207, R8A7795_CLK_S3D4), |
||||
DEF_MOD("msiof3", 208, R8A7795_CLK_MSO), |
||||
DEF_MOD("msiof2", 209, R8A7795_CLK_MSO), |
||||
DEF_MOD("msiof1", 210, R8A7795_CLK_MSO), |
||||
DEF_MOD("msiof0", 211, R8A7795_CLK_MSO), |
||||
DEF_MOD("sys-dmac2", 217, R8A7795_CLK_S0D3), |
||||
DEF_MOD("sys-dmac1", 218, R8A7795_CLK_S0D3), |
||||
DEF_MOD("sys-dmac0", 219, R8A7795_CLK_S0D3), |
||||
DEF_MOD("cmt3", 300, R8A7795_CLK_R), |
||||
DEF_MOD("cmt2", 301, R8A7795_CLK_R), |
||||
DEF_MOD("cmt1", 302, R8A7795_CLK_R), |
||||
DEF_MOD("cmt0", 303, R8A7795_CLK_R), |
||||
DEF_MOD("scif2", 310, R8A7795_CLK_S3D4), |
||||
DEF_MOD("sdif3", 311, R8A7795_CLK_SD3), |
||||
DEF_MOD("sdif2", 312, R8A7795_CLK_SD2), |
||||
DEF_MOD("sdif1", 313, R8A7795_CLK_SD1), |
||||
DEF_MOD("sdif0", 314, R8A7795_CLK_SD0), |
||||
DEF_MOD("pcie1", 318, R8A7795_CLK_S3D1), |
||||
DEF_MOD("pcie0", 319, R8A7795_CLK_S3D1), |
||||
DEF_MOD("usb-dmac30", 326, R8A7795_CLK_S3D1), |
||||
DEF_MOD("usb3-if1", 327, R8A7795_CLK_S3D1), /* ES1.x */ |
||||
DEF_MOD("usb3-if0", 328, R8A7795_CLK_S3D1), |
||||
DEF_MOD("usb-dmac31", 329, R8A7795_CLK_S3D1), |
||||
DEF_MOD("usb-dmac0", 330, R8A7795_CLK_S3D1), |
||||
DEF_MOD("usb-dmac1", 331, R8A7795_CLK_S3D1), |
||||
DEF_MOD("rwdt", 402, R8A7795_CLK_R), |
||||
DEF_MOD("intc-ex", 407, R8A7795_CLK_CP), |
||||
DEF_MOD("intc-ap", 408, R8A7795_CLK_S3D1), |
||||
DEF_MOD("audmac1", 501, R8A7795_CLK_S0D3), |
||||
DEF_MOD("audmac0", 502, R8A7795_CLK_S0D3), |
||||
DEF_MOD("drif7", 508, R8A7795_CLK_S3D2), |
||||
DEF_MOD("drif6", 509, R8A7795_CLK_S3D2), |
||||
DEF_MOD("drif5", 510, R8A7795_CLK_S3D2), |
||||
DEF_MOD("drif4", 511, R8A7795_CLK_S3D2), |
||||
DEF_MOD("drif3", 512, R8A7795_CLK_S3D2), |
||||
DEF_MOD("drif2", 513, R8A7795_CLK_S3D2), |
||||
DEF_MOD("drif1", 514, R8A7795_CLK_S3D2), |
||||
DEF_MOD("drif0", 515, R8A7795_CLK_S3D2), |
||||
DEF_MOD("hscif4", 516, R8A7795_CLK_S3D1), |
||||
DEF_MOD("hscif3", 517, R8A7795_CLK_S3D1), |
||||
DEF_MOD("hscif2", 518, R8A7795_CLK_S3D1), |
||||
DEF_MOD("hscif1", 519, R8A7795_CLK_S3D1), |
||||
DEF_MOD("hscif0", 520, R8A7795_CLK_S3D1), |
||||
DEF_MOD("thermal", 522, R8A7795_CLK_CP), |
||||
DEF_MOD("pwm", 523, R8A7795_CLK_S0D12), |
||||
DEF_MOD("fcpvd3", 600, R8A7795_CLK_S2D1), /* ES1.x */ |
||||
DEF_MOD("fcpvd2", 601, R8A7795_CLK_S0D2), |
||||
DEF_MOD("fcpvd1", 602, R8A7795_CLK_S0D2), |
||||
DEF_MOD("fcpvd0", 603, R8A7795_CLK_S0D2), |
||||
DEF_MOD("fcpvb1", 606, R8A7795_CLK_S0D1), |
||||
DEF_MOD("fcpvb0", 607, R8A7795_CLK_S0D1), |
||||
DEF_MOD("fcpvi2", 609, R8A7795_CLK_S2D1), /* ES1.x */ |
||||
DEF_MOD("fcpvi1", 610, R8A7795_CLK_S0D1), |
||||
DEF_MOD("fcpvi0", 611, R8A7795_CLK_S0D1), |
||||
DEF_MOD("fcpf2", 613, R8A7795_CLK_S2D1), /* ES1.x */ |
||||
DEF_MOD("fcpf1", 614, R8A7795_CLK_S0D1), |
||||
DEF_MOD("fcpf0", 615, R8A7795_CLK_S0D1), |
||||
DEF_MOD("fcpci1", 616, R8A7795_CLK_S2D1), /* ES1.x */ |
||||
DEF_MOD("fcpci0", 617, R8A7795_CLK_S2D1), /* ES1.x */ |
||||
DEF_MOD("fcpcs", 619, R8A7795_CLK_S0D1), |
||||
DEF_MOD("vspd3", 620, R8A7795_CLK_S2D1), /* ES1.x */ |
||||
DEF_MOD("vspd2", 621, R8A7795_CLK_S0D2), |
||||
DEF_MOD("vspd1", 622, R8A7795_CLK_S0D2), |
||||
DEF_MOD("vspd0", 623, R8A7795_CLK_S0D2), |
||||
DEF_MOD("vspbc", 624, R8A7795_CLK_S0D1), |
||||
DEF_MOD("vspbd", 626, R8A7795_CLK_S0D1), |
||||
DEF_MOD("vspi2", 629, R8A7795_CLK_S2D1), /* ES1.x */ |
||||
DEF_MOD("vspi1", 630, R8A7795_CLK_S0D1), |
||||
DEF_MOD("vspi0", 631, R8A7795_CLK_S0D1), |
||||
DEF_MOD("ehci3", 700, R8A7795_CLK_S3D4), |
||||
DEF_MOD("ehci2", 701, R8A7795_CLK_S3D4), |
||||
DEF_MOD("ehci1", 702, R8A7795_CLK_S3D4), |
||||
DEF_MOD("ehci0", 703, R8A7795_CLK_S3D4), |
||||
DEF_MOD("hsusb", 704, R8A7795_CLK_S3D4), |
||||
DEF_MOD("hsusb3", 705, R8A7795_CLK_S3D4), |
||||
DEF_MOD("csi21", 713, R8A7795_CLK_CSI0), /* ES1.x */ |
||||
DEF_MOD("csi20", 714, R8A7795_CLK_CSI0), |
||||
DEF_MOD("csi41", 715, R8A7795_CLK_CSI0), |
||||
DEF_MOD("csi40", 716, R8A7795_CLK_CSI0), |
||||
DEF_MOD("du3", 721, R8A7795_CLK_S2D1), |
||||
DEF_MOD("du2", 722, R8A7795_CLK_S2D1), |
||||
DEF_MOD("du1", 723, R8A7795_CLK_S2D1), |
||||
DEF_MOD("du0", 724, R8A7795_CLK_S2D1), |
||||
DEF_MOD("lvds", 727, R8A7795_CLK_S0D4), |
||||
DEF_MOD("hdmi1", 728, R8A7795_CLK_HDMI), |
||||
DEF_MOD("hdmi0", 729, R8A7795_CLK_HDMI), |
||||
DEF_MOD("vin7", 804, R8A7795_CLK_S0D2), |
||||
DEF_MOD("vin6", 805, R8A7795_CLK_S0D2), |
||||
DEF_MOD("vin5", 806, R8A7795_CLK_S0D2), |
||||
DEF_MOD("vin4", 807, R8A7795_CLK_S0D2), |
||||
DEF_MOD("vin3", 808, R8A7795_CLK_S0D2), |
||||
DEF_MOD("vin2", 809, R8A7795_CLK_S0D2), |
||||
DEF_MOD("vin1", 810, R8A7795_CLK_S0D2), |
||||
DEF_MOD("vin0", 811, R8A7795_CLK_S0D2), |
||||
DEF_MOD("etheravb", 812, R8A7795_CLK_S0D6), |
||||
DEF_MOD("sata0", 815, R8A7795_CLK_S3D2), |
||||
DEF_MOD("imr3", 820, R8A7795_CLK_S0D2), |
||||
DEF_MOD("imr2", 821, R8A7795_CLK_S0D2), |
||||
DEF_MOD("imr1", 822, R8A7795_CLK_S0D2), |
||||
DEF_MOD("imr0", 823, R8A7795_CLK_S0D2), |
||||
DEF_MOD("gpio7", 905, R8A7795_CLK_S3D4), |
||||
DEF_MOD("gpio6", 906, R8A7795_CLK_S3D4), |
||||
DEF_MOD("gpio5", 907, R8A7795_CLK_S3D4), |
||||
DEF_MOD("gpio4", 908, R8A7795_CLK_S3D4), |
||||
DEF_MOD("gpio3", 909, R8A7795_CLK_S3D4), |
||||
DEF_MOD("gpio2", 910, R8A7795_CLK_S3D4), |
||||
DEF_MOD("gpio1", 911, R8A7795_CLK_S3D4), |
||||
DEF_MOD("gpio0", 912, R8A7795_CLK_S3D4), |
||||
DEF_MOD("can-fd", 914, R8A7795_CLK_S3D2), |
||||
DEF_MOD("can-if1", 915, R8A7795_CLK_S3D4), |
||||
DEF_MOD("can-if0", 916, R8A7795_CLK_S3D4), |
||||
DEF_MOD("i2c6", 918, R8A7795_CLK_S0D6), |
||||
DEF_MOD("i2c5", 919, R8A7795_CLK_S0D6), |
||||
DEF_MOD("i2c-dvfs", 926, R8A7795_CLK_CP), |
||||
DEF_MOD("i2c4", 927, R8A7795_CLK_S0D6), |
||||
DEF_MOD("i2c3", 928, R8A7795_CLK_S0D6), |
||||
DEF_MOD("i2c2", 929, R8A7795_CLK_S3D2), |
||||
DEF_MOD("i2c1", 930, R8A7795_CLK_S3D2), |
||||
DEF_MOD("i2c0", 931, R8A7795_CLK_S3D2), |
||||
DEF_MOD("ssi-all", 1005, R8A7795_CLK_S3D4), |
||||
DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)), |
||||
DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)), |
||||
DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)), |
||||
DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)), |
||||
DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)), |
||||
DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)), |
||||
DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)), |
||||
DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)), |
||||
DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)), |
||||
DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)), |
||||
DEF_MOD("scu-all", 1017, R8A7795_CLK_S3D4), |
||||
DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)), |
||||
DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)), |
||||
DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)), |
||||
DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)), |
||||
DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)), |
||||
DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)), |
||||
DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)), |
||||
DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)), |
||||
DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)), |
||||
DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)), |
||||
DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)), |
||||
DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)), |
||||
DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)), |
||||
DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)), |
||||
}; |
||||
|
||||
static const struct mssr_mod_clk r8a7796_mod_clks[] = { |
||||
DEF_MOD("scif5", 202, R8A7796_CLK_S3D4), |
||||
DEF_MOD("scif4", 203, R8A7796_CLK_S3D4), |
||||
DEF_MOD("scif3", 204, R8A7796_CLK_S3D4), |
||||
DEF_MOD("scif1", 206, R8A7796_CLK_S3D4), |
||||
DEF_MOD("scif0", 207, R8A7796_CLK_S3D4), |
||||
DEF_MOD("msiof3", 208, R8A7796_CLK_MSO), |
||||
DEF_MOD("msiof2", 209, R8A7796_CLK_MSO), |
||||
DEF_MOD("msiof1", 210, R8A7796_CLK_MSO), |
||||
DEF_MOD("msiof0", 211, R8A7796_CLK_MSO), |
||||
DEF_MOD("sys-dmac2", 217, R8A7796_CLK_S0D3), |
||||
DEF_MOD("sys-dmac1", 218, R8A7796_CLK_S0D3), |
||||
DEF_MOD("sys-dmac0", 219, R8A7796_CLK_S0D3), |
||||
DEF_MOD("cmt3", 300, R8A7796_CLK_R), |
||||
DEF_MOD("cmt2", 301, R8A7796_CLK_R), |
||||
DEF_MOD("cmt1", 302, R8A7796_CLK_R), |
||||
DEF_MOD("cmt0", 303, R8A7796_CLK_R), |
||||
DEF_MOD("scif2", 310, R8A7796_CLK_S3D4), |
||||
DEF_MOD("sdif3", 311, R8A7796_CLK_SD3), |
||||
DEF_MOD("sdif2", 312, R8A7796_CLK_SD2), |
||||
DEF_MOD("sdif1", 313, R8A7796_CLK_SD1), |
||||
DEF_MOD("sdif0", 314, R8A7796_CLK_SD0), |
||||
DEF_MOD("pcie1", 318, R8A7796_CLK_S3D1), |
||||
DEF_MOD("pcie0", 319, R8A7796_CLK_S3D1), |
||||
DEF_MOD("usb-dmac0", 330, R8A7796_CLK_S3D1), |
||||
DEF_MOD("usb-dmac1", 331, R8A7796_CLK_S3D1), |
||||
DEF_MOD("rwdt", 402, R8A7796_CLK_R), |
||||
DEF_MOD("intc-ex", 407, R8A7796_CLK_CP), |
||||
DEF_MOD("intc-ap", 408, R8A7796_CLK_S3D1), |
||||
DEF_MOD("audmac1", 501, R8A7796_CLK_S0D3), |
||||
DEF_MOD("audmac0", 502, R8A7796_CLK_S0D3), |
||||
DEF_MOD("drif7", 508, R8A7796_CLK_S3D2), |
||||
DEF_MOD("drif6", 509, R8A7796_CLK_S3D2), |
||||
DEF_MOD("drif5", 510, R8A7796_CLK_S3D2), |
||||
DEF_MOD("drif4", 511, R8A7796_CLK_S3D2), |
||||
DEF_MOD("drif3", 512, R8A7796_CLK_S3D2), |
||||
DEF_MOD("drif2", 513, R8A7796_CLK_S3D2), |
||||
DEF_MOD("drif1", 514, R8A7796_CLK_S3D2), |
||||
DEF_MOD("drif0", 515, R8A7796_CLK_S3D2), |
||||
DEF_MOD("hscif4", 516, R8A7796_CLK_S3D1), |
||||
DEF_MOD("hscif3", 517, R8A7796_CLK_S3D1), |
||||
DEF_MOD("hscif2", 518, R8A7796_CLK_S3D1), |
||||
DEF_MOD("hscif1", 519, R8A7796_CLK_S3D1), |
||||
DEF_MOD("hscif0", 520, R8A7796_CLK_S3D1), |
||||
DEF_MOD("thermal", 522, R8A7796_CLK_CP), |
||||
DEF_MOD("pwm", 523, R8A7796_CLK_S0D12), |
||||
DEF_MOD("fcpvd2", 601, R8A7796_CLK_S0D2), |
||||
DEF_MOD("fcpvd1", 602, R8A7796_CLK_S0D2), |
||||
DEF_MOD("fcpvd0", 603, R8A7796_CLK_S0D2), |
||||
DEF_MOD("fcpvb0", 607, R8A7796_CLK_S0D1), |
||||
DEF_MOD("fcpvi0", 611, R8A7796_CLK_S0D1), |
||||
DEF_MOD("fcpf0", 615, R8A7796_CLK_S0D1), |
||||
DEF_MOD("fcpci0", 617, R8A7796_CLK_S0D2), |
||||
DEF_MOD("fcpcs", 619, R8A7796_CLK_S0D2), |
||||
DEF_MOD("vspd2", 621, R8A7796_CLK_S0D2), |
||||
DEF_MOD("vspd1", 622, R8A7796_CLK_S0D2), |
||||
DEF_MOD("vspd0", 623, R8A7796_CLK_S0D2), |
||||
DEF_MOD("vspb", 626, R8A7796_CLK_S0D1), |
||||
DEF_MOD("vspi0", 631, R8A7796_CLK_S0D1), |
||||
DEF_MOD("ehci1", 702, R8A7796_CLK_S3D4), |
||||
DEF_MOD("ehci0", 703, R8A7796_CLK_S3D4), |
||||
DEF_MOD("hsusb", 704, R8A7796_CLK_S3D4), |
||||
DEF_MOD("csi20", 714, R8A7796_CLK_CSI0), |
||||
DEF_MOD("csi40", 716, R8A7796_CLK_CSI0), |
||||
DEF_MOD("du2", 722, R8A7796_CLK_S2D1), |
||||
DEF_MOD("du1", 723, R8A7796_CLK_S2D1), |
||||
DEF_MOD("du0", 724, R8A7796_CLK_S2D1), |
||||
DEF_MOD("lvds", 727, R8A7796_CLK_S2D1), |
||||
DEF_MOD("hdmi0", 729, R8A7796_CLK_HDMI), |
||||
DEF_MOD("vin7", 804, R8A7796_CLK_S0D2), |
||||
DEF_MOD("vin6", 805, R8A7796_CLK_S0D2), |
||||
DEF_MOD("vin5", 806, R8A7796_CLK_S0D2), |
||||
DEF_MOD("vin4", 807, R8A7796_CLK_S0D2), |
||||
DEF_MOD("vin3", 808, R8A7796_CLK_S0D2), |
||||
DEF_MOD("vin2", 809, R8A7796_CLK_S0D2), |
||||
DEF_MOD("vin1", 810, R8A7796_CLK_S0D2), |
||||
DEF_MOD("vin0", 811, R8A7796_CLK_S0D2), |
||||
DEF_MOD("etheravb", 812, R8A7796_CLK_S0D6), |
||||
DEF_MOD("imr1", 822, R8A7796_CLK_S0D2), |
||||
DEF_MOD("imr0", 823, R8A7796_CLK_S0D2), |
||||
DEF_MOD("gpio7", 905, R8A7796_CLK_S3D4), |
||||
DEF_MOD("gpio6", 906, R8A7796_CLK_S3D4), |
||||
DEF_MOD("gpio5", 907, R8A7796_CLK_S3D4), |
||||
DEF_MOD("gpio4", 908, R8A7796_CLK_S3D4), |
||||
DEF_MOD("gpio3", 909, R8A7796_CLK_S3D4), |
||||
DEF_MOD("gpio2", 910, R8A7796_CLK_S3D4), |
||||
DEF_MOD("gpio1", 911, R8A7796_CLK_S3D4), |
||||
DEF_MOD("gpio0", 912, R8A7796_CLK_S3D4), |
||||
DEF_MOD("can-fd", 914, R8A7796_CLK_S3D2), |
||||
DEF_MOD("can-if1", 915, R8A7796_CLK_S3D4), |
||||
DEF_MOD("can-if0", 916, R8A7796_CLK_S3D4), |
||||
DEF_MOD("i2c6", 918, R8A7796_CLK_S0D6), |
||||
DEF_MOD("i2c5", 919, R8A7796_CLK_S0D6), |
||||
DEF_MOD("i2c-dvfs", 926, R8A7796_CLK_CP), |
||||
DEF_MOD("i2c4", 927, R8A7796_CLK_S0D6), |
||||
DEF_MOD("i2c3", 928, R8A7796_CLK_S0D6), |
||||
DEF_MOD("i2c2", 929, R8A7796_CLK_S3D2), |
||||
DEF_MOD("i2c1", 930, R8A7796_CLK_S3D2), |
||||
DEF_MOD("i2c0", 931, R8A7796_CLK_S3D2), |
||||
DEF_MOD("ssi-all", 1005, R8A7796_CLK_S3D4), |
||||
DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)), |
||||
DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)), |
||||
DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)), |
||||
DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)), |
||||
DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)), |
||||
DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)), |
||||
DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)), |
||||
DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)), |
||||
DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)), |
||||
DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)), |
||||
DEF_MOD("scu-all", 1017, R8A7796_CLK_S3D4), |
||||
DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)), |
||||
DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)), |
||||
DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)), |
||||
DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)), |
||||
DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)), |
||||
DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)), |
||||
DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)), |
||||
DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)), |
||||
DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)), |
||||
DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)), |
||||
DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)), |
||||
DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)), |
||||
DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)), |
||||
DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)), |
||||
}; |
||||
|
||||
/*
|
||||
* CPG Clock Data |
||||
*/ |
||||
|
||||
/*
|
||||
* MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 |
||||
* 14 13 19 17 (MHz) |
||||
*------------------------------------------------------------------- |
||||
* 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 |
||||
* 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 |
||||
* 0 0 1 0 Prohibited setting |
||||
* 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 |
||||
* 0 1 0 0 20 x 1 x150 x160 x120 x160 x120 |
||||
* 0 1 0 1 20 x 1 x150 x160 x120 x106 x120 |
||||
* 0 1 1 0 Prohibited setting |
||||
* 0 1 1 1 20 x 1 x150 x160 x120 x160 x120 |
||||
* 1 0 0 0 25 x 1 x120 x128 x96 x128 x96 |
||||
* 1 0 0 1 25 x 1 x120 x128 x96 x84 x96 |
||||
* 1 0 1 0 Prohibited setting |
||||
* 1 0 1 1 25 x 1 x120 x128 x96 x128 x96 |
||||
* 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144 |
||||
* 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144 |
||||
* 1 1 1 0 Prohibited setting |
||||
* 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144 |
||||
*/ |
||||
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \ |
||||
(((md) & BIT(13)) >> 11) | \
|
||||
(((md) & BIT(19)) >> 18) | \
|
||||
(((md) & BIT(17)) >> 17)) |
||||
|
||||
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = { |
||||
/* EXTAL div PLL1 mult PLL3 mult */ |
||||
{ 1, 192, 192, }, |
||||
{ 1, 192, 128, }, |
||||
{ 0, /* Prohibited setting */ }, |
||||
{ 1, 192, 192, }, |
||||
{ 1, 160, 160, }, |
||||
{ 1, 160, 106, }, |
||||
{ 0, /* Prohibited setting */ }, |
||||
{ 1, 160, 160, }, |
||||
{ 1, 128, 128, }, |
||||
{ 1, 128, 84, }, |
||||
{ 0, /* Prohibited setting */ }, |
||||
{ 1, 128, 128, }, |
||||
{ 2, 192, 192, }, |
||||
{ 2, 192, 128, }, |
||||
{ 0, /* Prohibited setting */ }, |
||||
{ 2, 192, 192, }, |
||||
}; |
||||
|
||||
/*
|
||||
* SDn Clock |
||||
*/ |
||||
#define CPG_SD_STP_HCK BIT(9) |
||||
#define CPG_SD_STP_CK BIT(8) |
||||
|
||||
#define CPG_SD_STP_MASK (CPG_SD_STP_HCK | CPG_SD_STP_CK) |
||||
#define CPG_SD_FC_MASK (0x7 << 2 | 0x3 << 0) |
||||
|
||||
#define CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) \ |
||||
{ \
|
||||
.val = ((stp_hck) ? CPG_SD_STP_HCK : 0) | \
|
||||
((stp_ck) ? CPG_SD_STP_CK : 0) | \
|
||||
((sd_srcfc) << 2) | \
|
||||
((sd_fc) << 0), \
|
||||
.div = (sd_div), \
|
||||
} |
||||
|
||||
struct sd_div_table { |
||||
u32 val; |
||||
unsigned int div; |
||||
}; |
||||
|
||||
/* SDn divider
|
||||
* sd_srcfc sd_fc div |
||||
* stp_hck stp_ck (div) (div) = sd_srcfc x sd_fc |
||||
*------------------------------------------------------------------- |
||||
* 0 0 0 (1) 1 (4) 4 |
||||
* 0 0 1 (2) 1 (4) 8 |
||||
* 1 0 2 (4) 1 (4) 16 |
||||
* 1 0 3 (8) 1 (4) 32 |
||||
* 1 0 4 (16) 1 (4) 64 |
||||
* 0 0 0 (1) 0 (2) 2 |
||||
* 0 0 1 (2) 0 (2) 4 |
||||
* 1 0 2 (4) 0 (2) 8 |
||||
* 1 0 3 (8) 0 (2) 16 |
||||
* 1 0 4 (16) 0 (2) 32 |
||||
*/ |
||||
static const struct sd_div_table cpg_sd_div_table[] = { |
||||
/* CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) */ |
||||
CPG_SD_DIV_TABLE_DATA(0, 0, 0, 1, 4), |
||||
CPG_SD_DIV_TABLE_DATA(0, 0, 1, 1, 8), |
||||
CPG_SD_DIV_TABLE_DATA(1, 0, 2, 1, 16), |
||||
CPG_SD_DIV_TABLE_DATA(1, 0, 3, 1, 32), |
||||
CPG_SD_DIV_TABLE_DATA(1, 0, 4, 1, 64), |
||||
CPG_SD_DIV_TABLE_DATA(0, 0, 0, 0, 2), |
||||
CPG_SD_DIV_TABLE_DATA(0, 0, 1, 0, 4), |
||||
CPG_SD_DIV_TABLE_DATA(1, 0, 2, 0, 8), |
||||
CPG_SD_DIV_TABLE_DATA(1, 0, 3, 0, 16), |
||||
CPG_SD_DIV_TABLE_DATA(1, 0, 4, 0, 32), |
||||
}; |
||||
|
||||
static bool gen3_clk_is_mod(struct clk *clk) |
||||
{ |
||||
return (clk->id >> 16) == CPG_MOD; |
||||
} |
||||
|
||||
static int gen3_clk_get_mod(struct clk *clk, const struct mssr_mod_clk **mssr) |
||||
{ |
||||
struct gen3_clk_priv *priv = dev_get_priv(clk->dev); |
||||
const unsigned long clkid = clk->id & 0xffff; |
||||
int i; |
||||
|
||||
if (!gen3_clk_is_mod(clk)) |
||||
return -EINVAL; |
||||
|
||||
for (i = 0; i < priv->mod_clk_size; i++) { |
||||
if (priv->mod_clk[i].id != MOD_CLK_ID(clkid)) |
||||
continue; |
||||
|
||||
*mssr = &priv->mod_clk[i]; |
||||
return 0; |
||||
} |
||||
|
||||
return -ENODEV; |
||||
} |
||||
|
||||
static int gen3_clk_get_core(struct clk *clk, const struct cpg_core_clk **core) |
||||
{ |
||||
const unsigned long clkid = clk->id & 0xffff; |
||||
int i; |
||||
|
||||
if (gen3_clk_is_mod(clk)) |
||||
return -EINVAL; |
||||
|
||||
for (i = 0; i < ARRAY_SIZE(gen3_core_clks); i++) { |
||||
if (gen3_core_clks[i].id != clkid) |
||||
continue; |
||||
|
||||
*core = &gen3_core_clks[i]; |
||||
return 0; |
||||
} |
||||
|
||||
return -ENODEV; |
||||
} |
||||
|
||||
static int gen3_clk_get_parent(struct clk *clk, struct clk *parent) |
||||
{ |
||||
const struct cpg_core_clk *core; |
||||
const struct mssr_mod_clk *mssr; |
||||
int ret; |
||||
|
||||
if (gen3_clk_is_mod(clk)) { |
||||
ret = gen3_clk_get_mod(clk, &mssr); |
||||
if (ret) |
||||
return ret; |
||||
|
||||
parent->id = mssr->parent; |
||||
} else { |
||||
ret = gen3_clk_get_core(clk, &core); |
||||
if (ret) |
||||
return ret; |
||||
|
||||
if (core->type == CLK_TYPE_IN) |
||||
parent->id = ~0; /* Top-level clock */ |
||||
else |
||||
parent->id = core->parent; |
||||
} |
||||
|
||||
parent->dev = clk->dev; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int gen3_clk_endisable(struct clk *clk, bool enable) |
||||
{ |
||||
struct gen3_clk_priv *priv = dev_get_priv(clk->dev); |
||||
const unsigned long clkid = clk->id & 0xffff; |
||||
const unsigned int reg = clkid / 100; |
||||
const unsigned int bit = clkid % 100; |
||||
const u32 bitmask = BIT(bit); |
||||
|
||||
if (!gen3_clk_is_mod(clk)) |
||||
return -EINVAL; |
||||
|
||||
debug("%s[%i] MSTP %lu=%02u/%02u %s\n", __func__, __LINE__, |
||||
clkid, reg, bit, enable ? "ON" : "OFF"); |
||||
|
||||
if (enable) { |
||||
clrbits_le32(priv->base + SMSTPCR(reg), bitmask); |
||||
return wait_for_bit("MSTP", priv->base + MSTPSR(reg), |
||||
bitmask, 0, 100, 0); |
||||
} else { |
||||
setbits_le32(priv->base + SMSTPCR(reg), bitmask); |
||||
return 0; |
||||
} |
||||
} |
||||
|
||||
static int gen3_clk_enable(struct clk *clk) |
||||
{ |
||||
return gen3_clk_endisable(clk, true); |
||||
} |
||||
|
||||
static int gen3_clk_disable(struct clk *clk) |
||||
{ |
||||
return gen3_clk_endisable(clk, false); |
||||
} |
||||
|
||||
static ulong gen3_clk_get_rate(struct clk *clk) |
||||
{ |
||||
struct gen3_clk_priv *priv = dev_get_priv(clk->dev); |
||||
struct clk parent; |
||||
const struct cpg_core_clk *core; |
||||
const struct rcar_gen3_cpg_pll_config *pll_config = |
||||
priv->cpg_pll_config; |
||||
u32 value, mult, rate = 0; |
||||
int i, ret; |
||||
|
||||
debug("%s[%i] Clock: id=%lu\n", __func__, __LINE__, clk->id); |
||||
|
||||
ret = gen3_clk_get_parent(clk, &parent); |
||||
if (ret) { |
||||
printf("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret); |
||||
return ret; |
||||
} |
||||
|
||||
if (gen3_clk_is_mod(clk)) { |
||||
rate = gen3_clk_get_rate(&parent); |
||||
debug("%s[%i] MOD clk: parent=%lu => rate=%u\n", |
||||
__func__, __LINE__, parent.id, rate); |
||||
return rate; |
||||
} |
||||
|
||||
ret = gen3_clk_get_core(clk, &core); |
||||
if (ret) |
||||
return ret; |
||||
|
||||
switch (core->type) { |
||||
case CLK_TYPE_IN: |
||||
if (core->id == CLK_EXTAL) { |
||||
rate = clk_get_rate(&priv->clk_extal); |
||||
debug("%s[%i] EXTAL clk: rate=%u\n", |
||||
__func__, __LINE__, rate); |
||||
return rate; |
||||
} |
||||
|
||||
if (core->id == CLK_EXTALR) { |
||||
rate = clk_get_rate(&priv->clk_extalr); |
||||
debug("%s[%i] EXTALR clk: rate=%u\n", |
||||
__func__, __LINE__, rate); |
||||
return rate; |
||||
} |
||||
|
||||
return -EINVAL; |
||||
|
||||
case CLK_TYPE_GEN3_MAIN: |
||||
rate = gen3_clk_get_rate(&parent) / pll_config->extal_div; |
||||
debug("%s[%i] MAIN clk: parent=%i extal_div=%i => rate=%u\n", |
||||
__func__, __LINE__, |
||||
core->parent, pll_config->extal_div, rate); |
||||
return rate; |
||||
|
||||
case CLK_TYPE_GEN3_PLL0: |
||||
value = readl(priv->base + CPG_PLL0CR); |
||||
mult = (((value >> 24) & 0x7f) + 1) * 2; |
||||
rate = gen3_clk_get_rate(&parent) * mult; |
||||
debug("%s[%i] PLL0 clk: parent=%i mult=%u => rate=%u\n", |
||||
__func__, __LINE__, core->parent, mult, rate); |
||||
return rate; |
||||
|
||||
case CLK_TYPE_GEN3_PLL1: |
||||
rate = gen3_clk_get_rate(&parent) * pll_config->pll1_mult; |
||||
debug("%s[%i] PLL1 clk: parent=%i mul=%i => rate=%u\n", |
||||
__func__, __LINE__, |
||||
core->parent, pll_config->pll1_mult, rate); |
||||
return rate; |
||||
|
||||
case CLK_TYPE_GEN3_PLL2: |
||||
value = readl(priv->base + CPG_PLL2CR); |
||||
mult = (((value >> 24) & 0x7f) + 1) * 2; |
||||
rate = gen3_clk_get_rate(&parent) * mult; |
||||
debug("%s[%i] PLL2 clk: parent=%i mult=%u => rate=%u\n", |
||||
__func__, __LINE__, core->parent, mult, rate); |
||||
return rate; |
||||
|
||||
case CLK_TYPE_GEN3_PLL3: |
||||
rate = gen3_clk_get_rate(&parent) * pll_config->pll3_mult; |
||||
debug("%s[%i] PLL3 clk: parent=%i mul=%i => rate=%u\n", |
||||
__func__, __LINE__, |
||||
core->parent, pll_config->pll3_mult, rate); |
||||
return rate; |
||||
|
||||
case CLK_TYPE_GEN3_PLL4: |
||||
value = readl(priv->base + CPG_PLL4CR); |
||||
mult = (((value >> 24) & 0x7f) + 1) * 2; |
||||
rate = gen3_clk_get_rate(&parent) * mult; |
||||
debug("%s[%i] PLL4 clk: parent=%i mult=%u => rate=%u\n", |
||||
__func__, __LINE__, core->parent, mult, rate); |
||||
return rate; |
||||
|
||||
case CLK_TYPE_FF: |
||||
rate = (gen3_clk_get_rate(&parent) * core->mult) / core->div; |
||||
debug("%s[%i] FIXED clk: parent=%i div=%i mul=%i => rate=%u\n", |
||||
__func__, __LINE__, |
||||
core->parent, core->mult, core->div, rate); |
||||
return rate; |
||||
|
||||
case CLK_TYPE_GEN3_SD: /* FIXME */ |
||||
value = readl(priv->base + core->offset); |
||||
value &= CPG_SD_STP_MASK | CPG_SD_FC_MASK; |
||||
|
||||
for (i = 0; i < ARRAY_SIZE(cpg_sd_div_table); i++) { |
||||
if (cpg_sd_div_table[i].val != value) |
||||
continue; |
||||
|
||||
rate = gen3_clk_get_rate(&parent) / |
||||
cpg_sd_div_table[i].div; |
||||
debug("%s[%i] SD clk: parent=%i div=%i => rate=%u\n", |
||||
__func__, __LINE__, |
||||
core->parent, cpg_sd_div_table[i].div, rate); |
||||
|
||||
return rate; |
||||
} |
||||
|
||||
return -EINVAL; |
||||
} |
||||
|
||||
printf("%s[%i] unknown fail\n", __func__, __LINE__); |
||||
|
||||
return -ENOENT; |
||||
} |
||||
|
||||
static ulong gen3_clk_set_rate(struct clk *clk, ulong rate) |
||||
{ |
||||
return gen3_clk_get_rate(clk); |
||||
} |
||||
|
||||
static int gen3_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args) |
||||
{ |
||||
if (args->args_count != 2) { |
||||
debug("Invaild args_count: %d\n", args->args_count); |
||||
return -EINVAL; |
||||
} |
||||
|
||||
clk->id = (args->args[0] << 16) | args->args[1]; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static const struct clk_ops gen3_clk_ops = { |
||||
.enable = gen3_clk_enable, |
||||
.disable = gen3_clk_disable, |
||||
.get_rate = gen3_clk_get_rate, |
||||
.set_rate = gen3_clk_set_rate, |
||||
.of_xlate = gen3_clk_of_xlate, |
||||
}; |
||||
|
||||
enum gen3_clk_model { |
||||
CLK_R8A7795, |
||||
CLK_R8A7796, |
||||
}; |
||||
|
||||
static int gen3_clk_probe(struct udevice *dev) |
||||
{ |
||||
struct gen3_clk_priv *priv = dev_get_priv(dev); |
||||
enum gen3_clk_model model = dev_get_driver_data(dev); |
||||
fdt_addr_t rst_base; |
||||
u32 cpg_mode; |
||||
int ret; |
||||
|
||||
priv->base = (struct gen3_base *)devfdt_get_addr(dev); |
||||
if (!priv->base) |
||||
return -EINVAL; |
||||
|
||||
switch (model) { |
||||
case CLK_R8A7795: |
||||
priv->mod_clk = r8a7795_mod_clks; |
||||
priv->mod_clk_size = ARRAY_SIZE(r8a7795_mod_clks); |
||||
ret = fdt_node_offset_by_compatible(gd->fdt_blob, -1, |
||||
"renesas,r8a7795-rst"); |
||||
if (ret < 0) |
||||
return ret; |
||||
break; |
||||
case CLK_R8A7796: |
||||
priv->mod_clk = r8a7796_mod_clks; |
||||
priv->mod_clk_size = ARRAY_SIZE(r8a7796_mod_clks); |
||||
ret = fdt_node_offset_by_compatible(gd->fdt_blob, -1, |
||||
"renesas,r8a7796-rst"); |
||||
if (ret < 0) |
||||
return ret; |
||||
break; |
||||
default: |
||||
return -EINVAL; |
||||
} |
||||
|
||||
rst_base = fdtdec_get_addr(gd->fdt_blob, ret, "reg"); |
||||
if (rst_base == FDT_ADDR_T_NONE) |
||||
return -EINVAL; |
||||
|
||||
cpg_mode = readl(rst_base + CPG_RST_MODEMR); |
||||
|
||||
priv->cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; |
||||
if (!priv->cpg_pll_config->extal_div) |
||||
return -EINVAL; |
||||
|
||||
ret = clk_get_by_name(dev, "extal", &priv->clk_extal); |
||||
if (ret < 0) |
||||
return ret; |
||||
|
||||
ret = clk_get_by_name(dev, "extalr", &priv->clk_extalr); |
||||
if (ret < 0) |
||||
return ret; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static const struct udevice_id gen3_clk_ids[] = { |
||||
{ .compatible = "renesas,r8a7795-cpg-mssr", .data = CLK_R8A7795 }, |
||||
{ .compatible = "renesas,r8a7796-cpg-mssr", .data = CLK_R8A7796 }, |
||||
{ } |
||||
}; |
||||
|
||||
U_BOOT_DRIVER(clk_gen3) = { |
||||
.name = "clk_gen3", |
||||
.id = UCLASS_CLK, |
||||
.of_match = gen3_clk_ids, |
||||
.priv_auto_alloc_size = sizeof(struct gen3_clk_priv), |
||||
.ops = &gen3_clk_ops, |
||||
.probe = gen3_clk_probe, |
||||
}; |
||||
@ -0,0 +1,109 @@ |
||||
/*
|
||||
* include/configs/ulcb.h |
||||
* This file is ULCB board configuration. |
||||
* |
||||
* Copyright (C) 2017 Renesas Electronics Corporation |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __ULCB_H |
||||
#define __ULCB_H |
||||
|
||||
#undef DEBUG |
||||
|
||||
#define CONFIG_RCAR_BOARD_STRING "ULCB" |
||||
|
||||
#include "rcar-gen3-common.h" |
||||
|
||||
/* M3 ULCB has 2 banks, each with 1 GiB of RAM */ |
||||
#if defined(CONFIG_R8A7796) |
||||
#undef PHYS_SDRAM_1_SIZE |
||||
#undef PHYS_SDRAM_2_SIZE |
||||
#define PHYS_SDRAM_1_SIZE (0x40000000u - DRAM_RSV_SIZE) |
||||
#define PHYS_SDRAM_2_SIZE 0x40000000u |
||||
#endif |
||||
|
||||
/* SCIF */ |
||||
#define CONFIG_CONS_SCIF2 |
||||
#define CONFIG_CONS_INDEX 2 |
||||
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_S3D4_CLK_FREQ |
||||
|
||||
/* [A] Hyper Flash */ |
||||
/* use to RPC(SPI Multi I/O Bus Controller) */ |
||||
|
||||
/* Ethernet RAVB */ |
||||
#define CONFIG_NET_MULTI |
||||
#define CONFIG_PHY_MICREL |
||||
#define CONFIG_BITBANGMII |
||||
#define CONFIG_BITBANGMII_MULTI |
||||
|
||||
/* Board Clock */ |
||||
/* XTAL_CLK : 33.33MHz */ |
||||
#define RCAR_XTAL_CLK 33333333u |
||||
#define CONFIG_SYS_CLK_FREQ RCAR_XTAL_CLK |
||||
/* ch0to2 CPclk, ch3to11 S3D2_PEREclk, ch12to14 S3D2_RTclk */ |
||||
/* CPclk 16.66MHz, S3D2 133.33MHz , S3D4 66.66MHz */ |
||||
#define CONFIG_CP_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) |
||||
#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 192 / 2) |
||||
#define CONFIG_S3D2_CLK_FREQ (266666666u/2) |
||||
#define CONFIG_S3D4_CLK_FREQ (266666666u/4) |
||||
|
||||
/* Generic Timer Definitions (use in assembler source) */ |
||||
#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */ |
||||
|
||||
/* Generic Interrupt Controller Definitions */ |
||||
#define CONFIG_GICV2 |
||||
#define GICD_BASE 0xF1010000 |
||||
#define GICC_BASE 0xF1020000 |
||||
|
||||
/* CPLD SPI */ |
||||
#define CONFIG_CMD_SPI |
||||
#define CONFIG_SOFT_SPI |
||||
#define SPI_DELAY udelay(0) |
||||
#define SPI_SDA(val) ulcb_softspi_sda(val) |
||||
#define SPI_SCL(val) ulcb_softspi_scl(val) |
||||
#define SPI_READ ulcb_softspi_read() |
||||
#ifndef __ASSEMBLY__ |
||||
void ulcb_softspi_sda(int); |
||||
void ulcb_softspi_scl(int); |
||||
unsigned char ulcb_softspi_read(void); |
||||
#endif |
||||
|
||||
/* i2c */ |
||||
#define CONFIG_SYS_I2C |
||||
#define CONFIG_SYS_I2C_SH |
||||
#define CONFIG_SYS_I2C_SLAVE 0x60 |
||||
#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 1 |
||||
#define CONFIG_SYS_I2C_SH_SPEED0 400000 |
||||
#define CONFIG_SH_I2C_DATA_HIGH 4 |
||||
#define CONFIG_SH_I2C_DATA_LOW 5 |
||||
#define CONFIG_SH_I2C_CLOCK 10000000 |
||||
|
||||
#define CONFIG_SYS_I2C_POWERIC_ADDR 0x30 |
||||
|
||||
/* USB */ |
||||
#ifdef CONFIG_R8A7795 |
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 |
||||
#else |
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
||||
#endif |
||||
|
||||
/* SDHI */ |
||||
#define CONFIG_SH_SDHI_FREQ 200000000 |
||||
|
||||
/* Environment in eMMC, at the end of 2nd "boot sector" */ |
||||
#define CONFIG_ENV_IS_IN_MMC |
||||
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) |
||||
#define CONFIG_SYS_MMC_ENV_DEV 1 |
||||
#define CONFIG_SYS_MMC_ENV_PART 2 |
||||
|
||||
/* Module stop status bits */ |
||||
/* MFIS, SCIF1 */ |
||||
#define CONFIG_SMSTP2_ENA 0x00002040 |
||||
/* SCIF2 */ |
||||
#define CONFIG_SMSTP3_ENA 0x00000400 |
||||
/* INTC-AP, IRQC */ |
||||
#define CONFIG_SMSTP4_ENA 0x00000180 |
||||
|
||||
#endif /* __ULCB_H */ |
||||
@ -0,0 +1,70 @@ |
||||
/*
|
||||
* Copyright (C) 2015 Renesas Electronics Corp. |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or |
||||
* (at your option) any later version. |
||||
*/ |
||||
#ifndef __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__ |
||||
#define __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__ |
||||
|
||||
#include <dt-bindings/clock/renesas-cpg-mssr.h> |
||||
|
||||
/* r8a7795 CPG Core Clocks */ |
||||
#define R8A7795_CLK_Z 0 |
||||
#define R8A7795_CLK_Z2 1 |
||||
#define R8A7795_CLK_ZR 2 |
||||
#define R8A7795_CLK_ZG 3 |
||||
#define R8A7795_CLK_ZTR 4 |
||||
#define R8A7795_CLK_ZTRD2 5 |
||||
#define R8A7795_CLK_ZT 6 |
||||
#define R8A7795_CLK_ZX 7 |
||||
#define R8A7795_CLK_S0D1 8 |
||||
#define R8A7795_CLK_S0D4 9 |
||||
#define R8A7795_CLK_S1D1 10 |
||||
#define R8A7795_CLK_S1D2 11 |
||||
#define R8A7795_CLK_S1D4 12 |
||||
#define R8A7795_CLK_S2D1 13 |
||||
#define R8A7795_CLK_S2D2 14 |
||||
#define R8A7795_CLK_S2D4 15 |
||||
#define R8A7795_CLK_S3D1 16 |
||||
#define R8A7795_CLK_S3D2 17 |
||||
#define R8A7795_CLK_S3D4 18 |
||||
#define R8A7795_CLK_LB 19 |
||||
#define R8A7795_CLK_CL 20 |
||||
#define R8A7795_CLK_ZB3 21 |
||||
#define R8A7795_CLK_ZB3D2 22 |
||||
#define R8A7795_CLK_CR 23 |
||||
#define R8A7795_CLK_CRD2 24 |
||||
#define R8A7795_CLK_SD0H 25 |
||||
#define R8A7795_CLK_SD0 26 |
||||
#define R8A7795_CLK_SD1H 27 |
||||
#define R8A7795_CLK_SD1 28 |
||||
#define R8A7795_CLK_SD2H 29 |
||||
#define R8A7795_CLK_SD2 30 |
||||
#define R8A7795_CLK_SD3H 31 |
||||
#define R8A7795_CLK_SD3 32 |
||||
#define R8A7795_CLK_SSP2 33 |
||||
#define R8A7795_CLK_SSP1 34 |
||||
#define R8A7795_CLK_SSPRS 35 |
||||
#define R8A7795_CLK_RPC 36 |
||||
#define R8A7795_CLK_RPCD2 37 |
||||
#define R8A7795_CLK_MSO 38 |
||||
#define R8A7795_CLK_CANFD 39 |
||||
#define R8A7795_CLK_HDMI 40 |
||||
#define R8A7795_CLK_CSI0 41 |
||||
#define R8A7795_CLK_CSIREF 42 |
||||
#define R8A7795_CLK_CP 43 |
||||
#define R8A7795_CLK_CPEX 44 |
||||
#define R8A7795_CLK_R 45 |
||||
#define R8A7795_CLK_OSC 46 |
||||
|
||||
/* r8a7795 ES2.0 CPG Core Clocks */ |
||||
#define R8A7795_CLK_S0D2 47 |
||||
#define R8A7795_CLK_S0D3 48 |
||||
#define R8A7795_CLK_S0D6 49 |
||||
#define R8A7795_CLK_S0D8 50 |
||||
#define R8A7795_CLK_S0D12 51 |
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__ */ |
||||
@ -0,0 +1,69 @@ |
||||
/*
|
||||
* Copyright (C) 2016 Renesas Electronics Corp. |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or |
||||
* (at your option) any later version. |
||||
*/ |
||||
#ifndef __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__ |
||||
#define __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__ |
||||
|
||||
#include <dt-bindings/clock/renesas-cpg-mssr.h> |
||||
|
||||
/* r8a7796 CPG Core Clocks */ |
||||
#define R8A7796_CLK_Z 0 |
||||
#define R8A7796_CLK_Z2 1 |
||||
#define R8A7796_CLK_ZR 2 |
||||
#define R8A7796_CLK_ZG 3 |
||||
#define R8A7796_CLK_ZTR 4 |
||||
#define R8A7796_CLK_ZTRD2 5 |
||||
#define R8A7796_CLK_ZT 6 |
||||
#define R8A7796_CLK_ZX 7 |
||||
#define R8A7796_CLK_S0D1 8 |
||||
#define R8A7796_CLK_S0D2 9 |
||||
#define R8A7796_CLK_S0D3 10 |
||||
#define R8A7796_CLK_S0D4 11 |
||||
#define R8A7796_CLK_S0D6 12 |
||||
#define R8A7796_CLK_S0D8 13 |
||||
#define R8A7796_CLK_S0D12 14 |
||||
#define R8A7796_CLK_S1D1 15 |
||||
#define R8A7796_CLK_S1D2 16 |
||||
#define R8A7796_CLK_S1D4 17 |
||||
#define R8A7796_CLK_S2D1 18 |
||||
#define R8A7796_CLK_S2D2 19 |
||||
#define R8A7796_CLK_S2D4 20 |
||||
#define R8A7796_CLK_S3D1 21 |
||||
#define R8A7796_CLK_S3D2 22 |
||||
#define R8A7796_CLK_S3D4 23 |
||||
#define R8A7796_CLK_LB 24 |
||||
#define R8A7796_CLK_CL 25 |
||||
#define R8A7796_CLK_ZB3 26 |
||||
#define R8A7796_CLK_ZB3D2 27 |
||||
#define R8A7796_CLK_ZB3D4 28 |
||||
#define R8A7796_CLK_CR 29 |
||||
#define R8A7796_CLK_CRD2 30 |
||||
#define R8A7796_CLK_SD0H 31 |
||||
#define R8A7796_CLK_SD0 32 |
||||
#define R8A7796_CLK_SD1H 33 |
||||
#define R8A7796_CLK_SD1 34 |
||||
#define R8A7796_CLK_SD2H 35 |
||||
#define R8A7796_CLK_SD2 36 |
||||
#define R8A7796_CLK_SD3H 37 |
||||
#define R8A7796_CLK_SD3 38 |
||||
#define R8A7796_CLK_SSP2 39 |
||||
#define R8A7796_CLK_SSP1 40 |
||||
#define R8A7796_CLK_SSPRS 41 |
||||
#define R8A7796_CLK_RPC 42 |
||||
#define R8A7796_CLK_RPCD2 43 |
||||
#define R8A7796_CLK_MSO 44 |
||||
#define R8A7796_CLK_CANFD 45 |
||||
#define R8A7796_CLK_HDMI 46 |
||||
#define R8A7796_CLK_CSI0 47 |
||||
#define R8A7796_CLK_CSIREF 48 |
||||
#define R8A7796_CLK_CP 49 |
||||
#define R8A7796_CLK_CPEX 50 |
||||
#define R8A7796_CLK_R 51 |
||||
#define R8A7796_CLK_OSC 52 |
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__ */ |
||||
@ -0,0 +1,15 @@ |
||||
/*
|
||||
* Copyright (C) 2015 Renesas Electronics Corp. |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or |
||||
* (at your option) any later version. |
||||
*/ |
||||
#ifndef __DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H__ |
||||
#define __DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H__ |
||||
|
||||
#define CPG_CORE 0 /* Core Clock */ |
||||
#define CPG_MOD 1 /* Module Clock */ |
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H__ */ |
||||
@ -0,0 +1,42 @@ |
||||
/*
|
||||
* Copyright (C) 2016 Glider bvba |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; version 2 of the License. |
||||
*/ |
||||
#ifndef __DT_BINDINGS_POWER_R8A7795_SYSC_H__ |
||||
#define __DT_BINDINGS_POWER_R8A7795_SYSC_H__ |
||||
|
||||
/*
|
||||
* These power domain indices match the numbers of the interrupt bits |
||||
* representing the power areas in the various Interrupt Registers |
||||
* (e.g. SYSCISR, Interrupt Status Register) |
||||
*/ |
||||
|
||||
#define R8A7795_PD_CA57_CPU0 0 |
||||
#define R8A7795_PD_CA57_CPU1 1 |
||||
#define R8A7795_PD_CA57_CPU2 2 |
||||
#define R8A7795_PD_CA57_CPU3 3 |
||||
#define R8A7795_PD_CA53_CPU0 5 |
||||
#define R8A7795_PD_CA53_CPU1 6 |
||||
#define R8A7795_PD_CA53_CPU2 7 |
||||
#define R8A7795_PD_CA53_CPU3 8 |
||||
#define R8A7795_PD_A3VP 9 |
||||
#define R8A7795_PD_CA57_SCU 12 |
||||
#define R8A7795_PD_CR7 13 |
||||
#define R8A7795_PD_A3VC 14 |
||||
#define R8A7795_PD_3DG_A 17 |
||||
#define R8A7795_PD_3DG_B 18 |
||||
#define R8A7795_PD_3DG_C 19 |
||||
#define R8A7795_PD_3DG_D 20 |
||||
#define R8A7795_PD_CA53_SCU 21 |
||||
#define R8A7795_PD_3DG_E 22 |
||||
#define R8A7795_PD_A3IR 24 |
||||
#define R8A7795_PD_A2VC0 25 /* ES1.x only */ |
||||
#define R8A7795_PD_A2VC1 26 |
||||
|
||||
/* Always-on power area */ |
||||
#define R8A7795_PD_ALWAYS_ON 32 |
||||
|
||||
#endif /* __DT_BINDINGS_POWER_R8A7795_SYSC_H__ */ |
||||
@ -0,0 +1,36 @@ |
||||
/*
|
||||
* Copyright (C) 2016 Glider bvba |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; version 2 of the License. |
||||
*/ |
||||
#ifndef __DT_BINDINGS_POWER_R8A7796_SYSC_H__ |
||||
#define __DT_BINDINGS_POWER_R8A7796_SYSC_H__ |
||||
|
||||
/*
|
||||
* These power domain indices match the numbers of the interrupt bits |
||||
* representing the power areas in the various Interrupt Registers |
||||
* (e.g. SYSCISR, Interrupt Status Register) |
||||
*/ |
||||
|
||||
#define R8A7796_PD_CA57_CPU0 0 |
||||
#define R8A7796_PD_CA57_CPU1 1 |
||||
#define R8A7796_PD_CA53_CPU0 5 |
||||
#define R8A7796_PD_CA53_CPU1 6 |
||||
#define R8A7796_PD_CA53_CPU2 7 |
||||
#define R8A7796_PD_CA53_CPU3 8 |
||||
#define R8A7796_PD_CA57_SCU 12 |
||||
#define R8A7796_PD_CR7 13 |
||||
#define R8A7796_PD_A3VC 14 |
||||
#define R8A7796_PD_3DG_A 17 |
||||
#define R8A7796_PD_3DG_B 18 |
||||
#define R8A7796_PD_CA53_SCU 21 |
||||
#define R8A7796_PD_A3IR 24 |
||||
#define R8A7796_PD_A2VC0 25 |
||||
#define R8A7796_PD_A2VC1 26 |
||||
|
||||
/* Always-on power area */ |
||||
#define R8A7796_PD_ALWAYS_ON 32 |
||||
|
||||
#endif /* __DT_BINDINGS_POWER_R8A7796_SYSC_H__ */ |
||||
Loading…
Reference in new issue