Add OMAP3, memory and function prototype header files for OMAP3. Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>master
Dirk Behme
16 years ago
committed by
Jean-Christophe PLAGNIOL-VILLARD
parent
2c803210a4
commit
a8b6450546
@ -0,0 +1,62 @@ |
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/*
|
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* (C) Copyright 2006-2008 |
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* Texas Instruments, <www.ti.com> |
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* Richard Woodruff <r-woodruff2@ti.com> |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#ifndef _CLOCKS_H_ |
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#define _CLOCKS_H_ |
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#define LDELAY 12000000 |
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#define S12M 12000000 |
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#define S13M 13000000 |
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#define S19_2M 19200000 |
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#define S24M 24000000 |
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#define S26M 26000000 |
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#define S38_4M 38400000 |
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#define FCK_IVA2_ON 0x00000001 |
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#define FCK_CORE1_ON 0x03fffe29 |
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#define ICK_CORE1_ON 0x3ffffffb |
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#define ICK_CORE2_ON 0x0000001f |
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#define FCK_WKUP_ON 0x000000e9 |
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#define ICK_WKUP_ON 0x0000003f |
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#define FCK_DSS_ON 0x00000005 |
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#define ICK_DSS_ON 0x00000001 |
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#define FCK_CAM_ON 0x00000001 |
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#define ICK_CAM_ON 0x00000001 |
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#define FCK_PER_ON 0x0003ffff |
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#define ICK_PER_ON 0x0003ffff |
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|
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/* Used to index into DPLL parameter tables */ |
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typedef struct { |
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unsigned int m; |
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unsigned int n; |
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unsigned int fsel; |
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unsigned int m2; |
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} dpll_param; |
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/* Following functions are exported from lowlevel_init.S */ |
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extern dpll_param *get_mpu_dpll_param(void); |
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extern dpll_param *get_iva_dpll_param(void); |
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extern dpll_param *get_core_dpll_param(void); |
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extern dpll_param *get_per_dpll_param(void); |
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extern void *_end_vect, *_start; |
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#endif |
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@ -0,0 +1,227 @@ |
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/*
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* (C) Copyright 2006-2008 |
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* Texas Instruments, <www.ti.com> |
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* Richard Woodruff <r-woodruff2@ti.com> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#ifndef _MEM_H_ |
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#define _MEM_H_ |
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#define CS0 0x0 |
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#define CS1 0x1 /* mirror CS1 regs appear offset 0x30 from CS0 */ |
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#ifndef __ASSEMBLY__ |
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typedef enum { |
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STACKED = 0, |
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IP_DDR = 1, |
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COMBO_DDR = 2, |
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IP_SDR = 3, |
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} mem_t; |
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#endif /* __ASSEMBLY__ */ |
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#define EARLY_INIT 1 |
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/* Slower full frequency range default timings for x32 operation*/ |
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#define SDP_SDRC_SHARING 0x00000100 |
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#define SDP_SDRC_MR_0_SDR 0x00000031 |
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/* optimized timings good for current shipping parts */ |
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#define SDP_3430_SDRC_RFR_CTRL_165MHz 0x0004e201 /* 7.8us/6ns - 50=0x4e2 */ |
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#define DLL_OFFSET 0 |
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#define DLL_WRITEDDRCLKX2DIS 1 |
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#define DLL_ENADLL 1 |
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#define DLL_LOCKDLL 0 |
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#define DLL_DLLPHASE_72 0 |
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#define DLL_DLLPHASE_90 1 |
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/* rkw - need to find of 90/72 degree recommendation for speed like before */ |
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#define SDP_SDRC_DLLAB_CTRL ((DLL_ENADLL << 3) | \ |
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(DLL_LOCKDLL << 2) | (DLL_DLLPHASE_90 << 1)) |
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/* Infineon part of 3430SDP (165MHz optimized) 6.06ns
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* ACTIMA |
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* TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6 |
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* TDPL (Twr) = 15/6 = 2.5 -> 3 |
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* TRRD = 12/6 = 2 |
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* TRCD = 18/6 = 3 |
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* TRP = 18/6 = 3 |
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* TRAS = 42/6 = 7 |
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* TRC = 60/6 = 10 |
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* TRFC = 72/6 = 12 |
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* ACTIMB |
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* TCKE = 2 |
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* XSR = 120/6 = 20 |
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*/ |
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#define TDAL_165 6 |
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#define TDPL_165 3 |
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#define TRRD_165 2 |
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#define TRCD_165 3 |
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#define TRP_165 3 |
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#define TRAS_165 7 |
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#define TRC_165 10 |
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#define TRFC_165 21 |
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#define V_ACTIMA_165 ((TRFC_165 << 27) | (TRC_165 << 22) | \ |
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(TRAS_165 << 18) | (TRP_165 << 15) | \
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(TRCD_165 << 12) | (TRRD_165 << 9) | \
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(TDPL_165 << 6) | (TDAL_165)) |
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#define TWTR_165 1 |
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#define TCKE_165 1 |
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#define TXP_165 5 |
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#define XSR_165 23 |
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#define V_ACTIMB_165 (((TCKE_165 << 12) | (XSR_165 << 0)) | \ |
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(TXP_165 << 8) | (TWTR_165 << 16)) |
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#define SDP_SDRC_ACTIM_CTRLA_0 V_ACTIMA_165 |
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#define SDP_SDRC_ACTIM_CTRLB_0 V_ACTIMB_165 |
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#define SDP_SDRC_RFR_CTRL SDP_3430_SDRC_RFR_CTRL_165MHz |
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/*
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* GPMC settings - |
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* Definitions is as per the following format |
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* #define <PART>_GPMC_CONFIG<x> <value> |
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* Where: |
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* PART is the part name e.g. STNOR - Intel Strata Flash |
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* x is GPMC config registers from 1 to 6 (there will be 6 macros) |
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* Value is corresponding value |
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* |
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* For every valid PRCM configuration there should be only one definition of |
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* the same. if values are independent of the board, this definition will be |
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* present in this file if values are dependent on the board, then this should |
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* go into corresponding mem-boardName.h file |
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* |
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* Currently valid part Names are (PART): |
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* STNOR - Intel Strata Flash |
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* SMNAND - Samsung NAND |
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* MPDB - H4 MPDB board |
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* SBNOR - Sibley NOR |
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* MNAND - Micron Large page x16 NAND |
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* ONNAND - Samsung One NAND |
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* |
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* include/configs/file.h contains the defn - for all CS we are interested |
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* #define OMAP34XX_GPMC_CSx PART |
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* #define OMAP34XX_GPMC_CSx_SIZE Size |
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* #define OMAP34XX_GPMC_CSx_MAP Map |
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* Where: |
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* x - CS number |
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* PART - Part Name as defined above |
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* SIZE - how big is the mapping to be |
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* GPMC_SIZE_128M - 0x8 |
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* GPMC_SIZE_64M - 0xC |
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* GPMC_SIZE_32M - 0xE |
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* GPMC_SIZE_16M - 0xF |
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* MAP - Map this CS to which address(GPMC address space)- Absolute address |
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* >>24 before being used. |
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*/ |
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#define GPMC_SIZE_128M 0x8 |
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#define GPMC_SIZE_64M 0xC |
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#define GPMC_SIZE_32M 0xE |
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#define GPMC_SIZE_16M 0xF |
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#define SMNAND_GPMC_CONFIG1 0x00000800 |
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#define SMNAND_GPMC_CONFIG2 0x00141400 |
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#define SMNAND_GPMC_CONFIG3 0x00141400 |
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#define SMNAND_GPMC_CONFIG4 0x0F010F01 |
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#define SMNAND_GPMC_CONFIG5 0x010C1414 |
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#define SMNAND_GPMC_CONFIG6 0x1F0F0A80 |
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#define SMNAND_GPMC_CONFIG7 0x00000C44 |
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#define M_NAND_GPMC_CONFIG1 0x00001800 |
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#define M_NAND_GPMC_CONFIG2 0x00141400 |
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#define M_NAND_GPMC_CONFIG3 0x00141400 |
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#define M_NAND_GPMC_CONFIG4 0x0F010F01 |
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#define M_NAND_GPMC_CONFIG5 0x010C1414 |
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#define M_NAND_GPMC_CONFIG6 0x1f0f0A80 |
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#define M_NAND_GPMC_CONFIG7 0x00000C44 |
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#define STNOR_GPMC_CONFIG1 0x3 |
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#define STNOR_GPMC_CONFIG2 0x00151501 |
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#define STNOR_GPMC_CONFIG3 0x00060602 |
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#define STNOR_GPMC_CONFIG4 0x11091109 |
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#define STNOR_GPMC_CONFIG5 0x01141F1F |
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#define STNOR_GPMC_CONFIG6 0x000004c4 |
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#define SIBNOR_GPMC_CONFIG1 0x1200 |
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#define SIBNOR_GPMC_CONFIG2 0x001f1f00 |
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#define SIBNOR_GPMC_CONFIG3 0x00080802 |
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#define SIBNOR_GPMC_CONFIG4 0x1C091C09 |
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#define SIBNOR_GPMC_CONFIG5 0x01131F1F |
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#define SIBNOR_GPMC_CONFIG6 0x1F0F03C2 |
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#define SDPV2_MPDB_GPMC_CONFIG1 0x00611200 |
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#define SDPV2_MPDB_GPMC_CONFIG2 0x001F1F01 |
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#define SDPV2_MPDB_GPMC_CONFIG3 0x00080803 |
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#define SDPV2_MPDB_GPMC_CONFIG4 0x1D091D09 |
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#define SDPV2_MPDB_GPMC_CONFIG5 0x041D1F1F |
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#define SDPV2_MPDB_GPMC_CONFIG6 0x1D0904C4 |
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#define MPDB_GPMC_CONFIG1 0x00011000 |
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#define MPDB_GPMC_CONFIG2 0x001f1f01 |
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#define MPDB_GPMC_CONFIG3 0x00080803 |
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#define MPDB_GPMC_CONFIG4 0x1c0b1c0a |
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#define MPDB_GPMC_CONFIG5 0x041f1F1F |
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#define MPDB_GPMC_CONFIG6 0x1F0F04C4 |
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#define P2_GPMC_CONFIG1 0x0 |
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#define P2_GPMC_CONFIG2 0x0 |
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#define P2_GPMC_CONFIG3 0x0 |
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#define P2_GPMC_CONFIG4 0x0 |
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#define P2_GPMC_CONFIG5 0x0 |
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#define P2_GPMC_CONFIG6 0x0 |
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#define ONENAND_GPMC_CONFIG1 0x00001200 |
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#define ONENAND_GPMC_CONFIG2 0x000F0F01 |
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#define ONENAND_GPMC_CONFIG3 0x00030301 |
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#define ONENAND_GPMC_CONFIG4 0x0F040F04 |
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#define ONENAND_GPMC_CONFIG5 0x010F1010 |
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#define ONENAND_GPMC_CONFIG6 0x1F060000 |
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#define NET_GPMC_CONFIG1 0x00001000 |
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#define NET_GPMC_CONFIG2 0x001e1e01 |
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#define NET_GPMC_CONFIG3 0x00080300 |
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#define NET_GPMC_CONFIG4 0x1c091c09 |
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#define NET_GPMC_CONFIG5 0x04181f1f |
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#define NET_GPMC_CONFIG6 0x00000FCF |
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#define NET_GPMC_CONFIG7 0x00000f6c |
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/* max number of GPMC Chip Selects */ |
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#define GPMC_MAX_CS 8 |
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/* max number of GPMC regs */ |
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#define GPMC_MAX_REG 7 |
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#define PISMO1_NOR 1 |
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#define PISMO1_NAND 2 |
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#define PISMO2_CS0 3 |
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#define PISMO2_CS1 4 |
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#define PISMO1_ONENAND 5 |
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#define DBG_MPDB 6 |
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#define PISMO2_NAND_CS0 7 |
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#define PISMO2_NAND_CS1 8 |
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/* make it readable for the gpmc_init */ |
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#define PISMO1_NOR_BASE FLASH_BASE |
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#define PISMO1_NAND_BASE NAND_BASE |
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#define PISMO2_CS0_BASE PISMO2_MAP1 |
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#define PISMO1_ONEN_BASE ONENAND_MAP |
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#define DBG_MPDB_BASE DEBUG_BASE |
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#endif /* endif _MEM_H_ */ |
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@ -0,0 +1,218 @@ |
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/*
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* (C) Copyright 2006-2008 |
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* Texas Instruments, <www.ti.com> |
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* Richard Woodruff <r-woodruff2@ti.com> |
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* Syed Mohammed Khasim <x0khasim@ti.com> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#ifndef _OMAP3_H_ |
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#define _OMAP3_H_ |
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/* Stuff on L3 Interconnect */ |
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#define SMX_APE_BASE 0x68000000 |
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/* GPMC */ |
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#define OMAP34XX_GPMC_BASE 0x6E000000 |
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/* SMS */ |
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#define OMAP34XX_SMS_BASE 0x6C000000 |
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/* SDRC */ |
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#define OMAP34XX_SDRC_BASE 0x6D000000 |
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/*
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* L4 Peripherals - L4 Wakeup and L4 Core now |
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*/ |
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#define OMAP34XX_CORE_L4_IO_BASE 0x48000000 |
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#define OMAP34XX_WAKEUP_L4_IO_BASE 0x48300000 |
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#define OMAP34XX_L4_PER 0x49000000 |
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#define OMAP34XX_L4_IO_BASE OMAP34XX_CORE_L4_IO_BASE |
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/* CONTROL */ |
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#define OMAP34XX_CTRL_BASE (OMAP34XX_L4_IO_BASE + 0x2000) |
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/* UART */ |
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#define OMAP34XX_UART1 (OMAP34XX_L4_IO_BASE + 0x6a000) |
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#define OMAP34XX_UART2 (OMAP34XX_L4_IO_BASE + 0x6c000) |
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#define OMAP34XX_UART3 (OMAP34XX_L4_PER + 0x20000) |
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/* General Purpose Timers */ |
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#define OMAP34XX_GPT1 0x48318000 |
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#define OMAP34XX_GPT2 0x49032000 |
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#define OMAP34XX_GPT3 0x49034000 |
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#define OMAP34XX_GPT4 0x49036000 |
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#define OMAP34XX_GPT5 0x49038000 |
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#define OMAP34XX_GPT6 0x4903A000 |
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#define OMAP34XX_GPT7 0x4903C000 |
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#define OMAP34XX_GPT8 0x4903E000 |
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#define OMAP34XX_GPT9 0x49040000 |
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#define OMAP34XX_GPT10 0x48086000 |
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#define OMAP34XX_GPT11 0x48088000 |
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#define OMAP34XX_GPT12 0x48304000 |
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/* WatchDog Timers (1 secure, 3 GP) */ |
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#define WD1_BASE 0x4830C000 |
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#define WD2_BASE 0x48314000 |
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#define WD3_BASE 0x49030000 |
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/* 32KTIMER */ |
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#define SYNC_32KTIMER_BASE 0x48320000 |
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#ifndef __ASSEMBLY__ |
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typedef struct s32ktimer { |
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unsigned char res[0x10]; |
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unsigned int s32k_cr; /* 0x10 */ |
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} s32ktimer_t; |
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#endif /* __ASSEMBLY__ */ |
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/* OMAP3 GPIO registers */ |
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#define OMAP34XX_GPIO1_BASE 0x48310000 |
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#define OMAP34XX_GPIO2_BASE 0x49050000 |
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#define OMAP34XX_GPIO3_BASE 0x49052000 |
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#define OMAP34XX_GPIO4_BASE 0x49054000 |
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#define OMAP34XX_GPIO5_BASE 0x49056000 |
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#define OMAP34XX_GPIO6_BASE 0x49058000 |
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#ifndef __ASSEMBLY__ |
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typedef struct gpio { |
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unsigned char res1[0x34]; |
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unsigned int oe; /* 0x34 */ |
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unsigned char res2[0x58]; |
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unsigned int cleardataout; /* 0x90 */ |
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unsigned int setdataout; /* 0x94 */ |
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} gpio_t; |
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#endif /* __ASSEMBLY__ */ |
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#define GPIO0 (0x1 << 0) |
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#define GPIO1 (0x1 << 1) |
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#define GPIO2 (0x1 << 2) |
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#define GPIO3 (0x1 << 3) |
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#define GPIO4 (0x1 << 4) |
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#define GPIO5 (0x1 << 5) |
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#define GPIO6 (0x1 << 6) |
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#define GPIO7 (0x1 << 7) |
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#define GPIO8 (0x1 << 8) |
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#define GPIO9 (0x1 << 9) |
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#define GPIO10 (0x1 << 10) |
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#define GPIO11 (0x1 << 11) |
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#define GPIO12 (0x1 << 12) |
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#define GPIO13 (0x1 << 13) |
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#define GPIO14 (0x1 << 14) |
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#define GPIO15 (0x1 << 15) |
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#define GPIO16 (0x1 << 16) |
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#define GPIO17 (0x1 << 17) |
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#define GPIO18 (0x1 << 18) |
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#define GPIO19 (0x1 << 19) |
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#define GPIO20 (0x1 << 20) |
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#define GPIO21 (0x1 << 21) |
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#define GPIO22 (0x1 << 22) |
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#define GPIO23 (0x1 << 23) |
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#define GPIO24 (0x1 << 24) |
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#define GPIO25 (0x1 << 25) |
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#define GPIO26 (0x1 << 26) |
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#define GPIO27 (0x1 << 27) |
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#define GPIO28 (0x1 << 28) |
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#define GPIO29 (0x1 << 29) |
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#define GPIO30 (0x1 << 30) |
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#define GPIO31 (0x1 << 31) |
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/* base address for indirect vectors (internal boot mode) */ |
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#define SRAM_OFFSET0 0x40000000 |
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#define SRAM_OFFSET1 0x00200000 |
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#define SRAM_OFFSET2 0x0000F800 |
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#define SRAM_VECT_CODE (SRAM_OFFSET0 | SRAM_OFFSET1 | \ |
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SRAM_OFFSET2) |
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#define LOW_LEVEL_SRAM_STACK 0x4020FFFC |
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#define DEBUG_LED1 149 /* gpio */ |
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#define DEBUG_LED2 150 /* gpio */ |
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#define XDR_POP 5 /* package on package part */ |
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#define SDR_DISCRETE 4 /* 128M memory SDR module */ |
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#define DDR_STACKED 3 /* stacked part on 2422 */ |
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#define DDR_COMBO 2 /* combo part on cpu daughter card */ |
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#define DDR_DISCRETE 1 /* 2x16 parts on daughter card */ |
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|
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#define DDR_100 100 /* type found on most mem d-boards */ |
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#define DDR_111 111 /* some combo parts */ |
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#define DDR_133 133 /* most combo, some mem d-boards */ |
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#define DDR_165 165 /* future parts */ |
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#define CPU_3430 0x3430 |
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/*
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* 343x real hardware: |
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* ES1 = rev 0 |
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* |
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* 343x code defines: |
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* ES1 = 0+1 = 1 |
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* ES1 = 1+1 = 1 |
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*/ |
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#define CPU_3430_ES1 1 |
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#define CPU_3430_ES2 2 |
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|
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#define WIDTH_8BIT 0x0000 |
||||
#define WIDTH_16BIT 0x1000 /* bit pos for 16 bit in gpmc */ |
||||
|
||||
/* SDP definitions according to FPGA Rev. Is this OK?? */ |
||||
#define SDP_3430_V1 0x1 |
||||
#define SDP_3430_V2 0x2 |
||||
|
||||
/* EVM definitions */ |
||||
#define OMAP3EVM_V1 0x1 |
||||
#define OMAP3EVM_V2 0x2 |
||||
|
||||
/* I2C power management companion definitions */ |
||||
#define PWRMGT_ADDR_ID1 0x48 |
||||
#define PWRMGT_ADDR_ID2 0x49 |
||||
#define PWRMGT_ADDR_ID3 0x4A |
||||
#define PWRMGT_ADDR_ID4 0x4B |
||||
|
||||
/* I2C ID3 (slave3) register */ |
||||
#define LEDEN 0xEE |
||||
|
||||
#define LEDAON (0x1 << 0) |
||||
#define LEDBON (0x1 << 1) |
||||
#define LEDAPWM (0x1 << 4) |
||||
#define LEDBPWM (0x1 << 5) |
||||
|
||||
/* I2C ID4 (slave4) register */ |
||||
#define VAUX2_DEV_GRP 0x76 |
||||
#define VAUX2_DEDICATED 0x79 |
||||
#define VAUX3_DEV_GRP 0x7A |
||||
#define VAUX3_DEDICATED 0x7D |
||||
#define VPLL2_DEV_GRP 0x8E |
||||
#define VPLL2_DEDICATED 0x91 |
||||
#define VDAC_DEV_GRP 0x96 |
||||
#define VDAC_DEDICATED 0x99 |
||||
|
||||
#define DEV_GRP_P1 0x20 |
||||
#define DEV_GRP_ALL 0xE0 |
||||
|
||||
#define VAUX2_VSEL_28 0x09 |
||||
#define VAUX3_VSEL_28 0x03 |
||||
#define VPLL2_VSEL_18 0x05 |
||||
#define VDAC_VSEL_18 0x03 |
||||
|
||||
#endif |
||||
@ -0,0 +1,84 @@ |
||||
/*
|
||||
* (C) Copyright 2004-2008 Texas Instruments, <www.ti.com> |
||||
* Rohit Choraria <rohitkc@ti.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
#ifndef __ASM_ARCH_OMAP_GPMC_H |
||||
#define __ASM_ARCH_OMAP_GPMC_H |
||||
|
||||
#define GPMC_BUF_EMPTY 0 |
||||
#define GPMC_BUF_FULL 1 |
||||
|
||||
#define ECCCLEAR (0x1 << 8) |
||||
#define ECCRESULTREG1 (0x1 << 0) |
||||
#define ECCSIZE512BYTE 0xFF |
||||
#define ECCSIZE1 (ECCSIZE512BYTE << 22) |
||||
#define ECCSIZE0 (ECCSIZE512BYTE << 12) |
||||
#define ECCSIZE0SEL (0x000 << 0) |
||||
|
||||
/* Generic ECC Layouts */ |
||||
/* Large Page x8 NAND device Layout */ |
||||
#ifdef GPMC_NAND_ECC_LP_x8_LAYOUT |
||||
#define GPMC_NAND_HW_ECC_LAYOUT {\ |
||||
.eccbytes = 12,\
|
||||
.eccpos = {1, 2, 3, 4, 5, 6, 7, 8,\
|
||||
9, 10, 11, 12},\
|
||||
.oobfree = {\
|
||||
{.offset = 13,\
|
||||
.length = 51 } } \
|
||||
} |
||||
#endif |
||||
|
||||
/* Large Page x16 NAND device Layout */ |
||||
#ifdef GPMC_NAND_ECC_LP_x16_LAYOUT |
||||
#define GPMC_NAND_HW_ECC_LAYOUT {\ |
||||
.eccbytes = 12,\
|
||||
.eccpos = {2, 3, 4, 5, 6, 7, 8, 9,\
|
||||
10, 11, 12, 13},\
|
||||
.oobfree = {\
|
||||
{.offset = 14,\
|
||||
.length = 50 } } \
|
||||
} |
||||
#endif |
||||
|
||||
/* Small Page x8 NAND device Layout */ |
||||
#ifdef GPMC_NAND_ECC_SP_x8_LAYOUT |
||||
#define GPMC_NAND_HW_ECC_LAYOUT {\ |
||||
.eccbytes = 3,\
|
||||
.eccpos = {1, 2, 3},\
|
||||
.oobfree = {\
|
||||
{.offset = 4,\
|
||||
.length = 12 } } \
|
||||
} |
||||
#endif |
||||
|
||||
/* Small Page x16 NAND device Layout */ |
||||
#ifdef GPMC_NAND_ECC_SP_x16_LAYOUT |
||||
#define GPMC_NAND_HW_ECC_LAYOUT {\ |
||||
.eccbytes = 3,\
|
||||
.eccpos = {2, 3, 4},\
|
||||
.oobfree = {\
|
||||
{.offset = 5,\
|
||||
.length = 11 } } \
|
||||
} |
||||
#endif |
||||
|
||||
#endif /* __ASM_ARCH_OMAP_GPMC_H */ |
||||
|
||||
@ -0,0 +1,71 @@ |
||||
/*
|
||||
* (C) Copyright 2004-2008 |
||||
* Texas Instruments, <www.ti.com> |
||||
* Richard Woodruff <r-woodruff2@ti.com> |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
#ifndef _SYS_PROTO_H_ |
||||
#define _SYS_PROTO_H_ |
||||
|
||||
typedef struct { |
||||
u32 board_type_v1; |
||||
u32 board_type_v2; |
||||
u32 mtype; |
||||
char *cpu_string; |
||||
char *board_string; |
||||
char *nand_string; |
||||
} omap3_sysinfo; |
||||
|
||||
void prcm_init(void); |
||||
void per_clocks_enable(void); |
||||
|
||||
void memif_init(void); |
||||
void sdrc_init(void); |
||||
void do_sdrc_init(u32, u32); |
||||
void gpmc_init(void); |
||||
|
||||
void watchdog_init(void); |
||||
void set_muxconf_regs(void); |
||||
|
||||
u32 get_cpu_rev(void); |
||||
u32 get_mem_type(void); |
||||
u32 get_sysboot_value(void); |
||||
u32 is_gpmc_muxed(void); |
||||
u32 get_gpmc0_type(void); |
||||
u32 get_gpmc0_width(void); |
||||
u32 get_board_type(void); |
||||
void display_board_info(u32); |
||||
u32 get_sdr_cs_size(u32); |
||||
u32 get_sdr_cs_offset(u32); |
||||
u32 is_running_in_sdram(void); |
||||
u32 is_running_in_sram(void); |
||||
u32 is_running_in_flash(void); |
||||
u32 get_device_type(void); |
||||
void l2cache_enable(void); |
||||
void secureworld_exit(void); |
||||
void setup_auxcr(void); |
||||
void try_unlock_memory(void); |
||||
u32 get_boot_type(void); |
||||
void v7_flush_dcache_all(u32); |
||||
void sr32(void *, u32, u32, u32); |
||||
u32 wait_on_value(u32, u32, void *, u32); |
||||
void sdelay(unsigned long); |
||||
void make_cs1_contiguous(void); |
||||
void omap_nand_switch_ecc(int); |
||||
void power_init_r(void); |
||||
|
||||
#endif |
||||
Loading…
Reference in new issue