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@ -13,6 +13,8 @@ |
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DECLARE_GLOBAL_DATA_PTR; |
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static bool i440fx; |
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void board_pci_setup_hose(struct pci_controller *hose) |
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{ |
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hose->first_busno = 0; |
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@ -61,7 +63,8 @@ int board_pci_post_scan(struct pci_controller *hose) |
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* PCI device ID. |
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*/ |
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device = x86_pci_read_config16(PCI_BDF(0, 0, 0), PCI_DEVICE_ID); |
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pam = (device == PCI_DEVICE_ID_INTEL_82441) ? I440FX_PAM : Q35_PAM; |
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i440fx = (device == PCI_DEVICE_ID_INTEL_82441); |
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pam = i440fx ? I440FX_PAM : Q35_PAM; |
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/*
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* Initialize Programmable Attribute Map (PAM) Registers |
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@ -71,7 +74,7 @@ int board_pci_post_scan(struct pci_controller *hose) |
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for (i = 0; i < PAM_NUM; i++) |
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x86_pci_write_config8(PCI_BDF(0, 0, 0), pam + i, PAM_RW); |
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if (device == PCI_DEVICE_ID_INTEL_82441) { |
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if (i440fx) { |
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/*
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* Enable legacy IDE I/O ports decode |
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* |
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@ -97,10 +100,35 @@ int board_pci_post_scan(struct pci_controller *hose) |
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* board, it shows as device 2, while for Q35 and ICH9 chipset board, |
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* it shows as device 1. |
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*/ |
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vga = (device == PCI_DEVICE_ID_INTEL_82441) ? I440FX_VGA : Q35_VGA; |
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vga = i440fx ? I440FX_VGA : Q35_VGA; |
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start = get_timer(0); |
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ret = pci_run_vga_bios(vga, NULL, PCI_ROM_USE_NATIVE); |
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debug("BIOS ran in %lums\n", get_timer(start)); |
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return ret; |
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} |
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#ifdef CONFIG_GENERATE_MP_TABLE |
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int mp_determine_pci_dstirq(int bus, int dev, int func, int pirq) |
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{ |
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u8 irq; |
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if (i440fx) { |
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/*
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* Not like most x86 platforms, the PIRQ[A-D] on PIIX3 are not |
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* connected to I/O APIC INTPIN#16-19. Instead they are routed |
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* to an irq number controled by the PIRQ routing register. |
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*/ |
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irq = x86_pci_read_config8(PCI_BDF(bus, dev, func), |
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PCI_INTERRUPT_LINE); |
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} else { |
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/*
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* ICH9's PIRQ[A-H] are not consecutive numbers from 0 to 7. |
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* PIRQ[A-D] still maps to [0-3] but PIRQ[E-H] maps to [8-11]. |
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*/ |
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irq = pirq < 8 ? pirq + 16 : pirq + 12; |
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} |
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return irq; |
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} |
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#endif |
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