@ -108,12 +108,6 @@ _TEXT_BASE:
_TEXT_PHY_BASE :
.word CONFIG_SYS_PHY_UBOOT_BASE
# if d e f i n e d ( C O N F I G _ S Y S _ A R M _ W I T H O U T _ R E L O C )
.globl _armboot_start
_armboot_start :
.word _start
# endif
/ *
* These a r e d e f i n e d i n t h e b o a r d - s p e c i f i c l i n k e r s c r i p t .
* Subtracting _ s t a r t f r o m t h e m l e t s t h e l i n k e r p u t t h e i r
@ -157,7 +151,6 @@ _rel_dyn_end_ofs:
_dynsym_start_ofs :
.word __dynsym_start - _ start
# if ! d e f i n e d ( C O N F I G _ S Y S _ A R M _ W I T H O U T _ R E L O C )
/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN :
@ -419,188 +412,6 @@ _board_init_r_ofs:
.word board_init_r - _ start
# endif
# else / * #i f ! d e f i n e d ( C O N F I G _ S Y S _ A R M _ W I T H O U T _ R E L O C ) * /
/ *
* the a c t u a l r e s e t c o d e
* /
reset :
/ *
* set t h e c p u t o S V C 3 2 m o d e
* /
mrs r0 , c p s r
bic r0 , r0 , #0x3f
orr r0 , r0 , #0xd3
msr c p s r , r0
/ *
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
*
* CPU_ i n i t _ c r i t i c a l r e g i s t e r s
*
* setup i m p o r t a n t r e g i s t e r s
* setup m e m o r y t i m i n g
*
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* /
/ *
* we d o s y s - c r i t i c a l i n i t s o n l y a t r e b o o t ,
* not w h e n b o o t i n g f r o m r a m !
* /
cpu_init_crit :
/ *
* When b o o t i n g f r o m N A N D - i t h a s d e f i n i t e l y b e e n a r e s e t , s o , n o n e e d
* to f l u s h c a c h e s a n d d i s a b l e t h e M M U
* /
# ifndef C O N F I G _ N A N D _ S P L
/ *
* flush v4 I / D c a c h e s
* /
mov r0 , #0
mcr p15 , 0 , r0 , c7 , c7 , 0 / * f l u s h v3 / v4 c a c h e * /
mcr p15 , 0 , r0 , c8 , c7 , 0 / * f l u s h v4 T L B * /
/ *
* disable M M U s t u f f a n d c a c h e s
* /
mrc p15 , 0 , r0 , c1 , c0 , 0
bic r0 , r0 , #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
bic r0 , r0 , #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
orr r0 , r0 , #0x00000002 @ set bit 2 (A) Align
orr r0 , r0 , #0x00001000 @ set bit 12 (I) I-Cache
/* Prepare to disable the MMU */
adr r2 , m m u _ d i s a b l e _ p h y s
sub r2 , r2 , #( C O N F I G _ S Y S _ P H Y _ U B O O T _ B A S E - C O N F I G _ S Y S _ T E X T _ B A S E )
b m m u _ d i s a b l e
.align 5
/* Run in a single cache-line */
mmu_disable :
mcr p15 , 0 , r0 , c1 , c0 , 0
nop
nop
mov p c , r2
mmu_disable_phys :
# ifdef C O N F I G _ D I S A B L E _ T C M
/ *
* Disable t h e T C M s
* /
mrc p15 , 0 , r0 , c0 , c0 , 2 / * R e t u r n T C M d e t a i l s * /
cmp r0 , #0
beq s k i p _ t c m d i s a b l e
mov r1 , #0
mov r2 , #1
tst r0 , r2
mcrne p15 , 0 , r1 , c9 , c1 , 1 / * D i s a b l e I n s t r u c t i o n T C M i f p r e s e n t * /
tst r0 , r2 , L S L #16
mcrne p15 , 0 , r1 , c9 , c1 , 0 / * D i s a b l e D a t a T C M i f p r e s e n t * /
skip_tcmdisable :
# endif
# endif
# ifdef C O N F I G _ P E R I P O R T _ R E M A P
/* Peri port setup */
ldr r0 , =CONFIG_PERIPORT_BASE
orr r0 , r0 , #C O N F I G _ P E R I P O R T _ S I Z E
mcr p15 ,0 ,r0 ,c15 ,c2 ,4
# endif
/ *
* Go s e t u p M e m o r y a n d b o a r d s p e c i f i c b i t s p r i o r t o r e l o c a t i o n .
* /
bl l o w l e v e l _ i n i t / * g o s e t u p p l l ,m u x ,m e m o r y * /
# ifndef C O N F I G _ S K I P _ R E L O C A T E _ U B O O T
relocate : /* relocate U-Boot to RAM */
adr r0 , _ s t a r t / * r0 < - c u r r e n t p o s i t i o n o f c o d e * /
ldr r1 , _ T E X T _ B A S E / * t e s t i f w e r u n f r o m f l a s h o r R A M * /
cmp r0 , r1 / * d o n ' t r e l o c d u r i n g d e b u g * /
beq s t a c k _ s e t u p
ldr r2 , _ a r m b o o t _ s t a r t
ldr r3 , _ b s s _ s t a r t
sub r2 , r3 , r2 / * r2 < - s i z e o f a r m b o o t * /
add r2 , r0 , r2 / * r2 < - s o u r c e e n d a d d r e s s * /
copy_loop :
ldmia r0 ! , { r3 - r10 } / * c o p y f r o m s o u r c e a d d r e s s [ r0 ] * /
stmia r1 ! , { r3 - r10 } / * c o p y t o t a r g e t a d d r e s s [ r1 ] * /
cmp r0 , r2 / * u n t i l s o u r c e e n d a d d r e s s [ r2 ] * /
blo c o p y _ l o o p
# endif / * C O N F I G _ S K I P _ R E L O C A T E _ U B O O T * /
# ifdef C O N F I G _ E N A B L E _ M M U
enable_mmu :
/* enable domain access */
ldr r5 , =0x0000ffff
mcr p15 , 0 , r5 , c3 , c0 , 0 / * l o a d d o m a i n a c c e s s r e g i s t e r * /
/* Set the TTB register */
ldr r0 , _ m m u _ t a b l e _ b a s e
ldr r1 , =CONFIG_SYS_PHY_UBOOT_BASE
ldr r2 , =0xfff00000
bic r0 , r0 , r2
orr r1 , r0 , r1
mcr p15 , 0 , r1 , c2 , c0 , 0
/* Enable the MMU */
mrc p15 , 0 , r0 , c1 , c0 , 0
orr r0 , r0 , #1 / * S e t C R _ M t o e n a b l e M M U * /
/* Prepare to enable the MMU */
adr r1 , s k i p _ h w _ i n i t
and r1 , r1 , #0x3fc
ldr r2 , _ T E X T _ B A S E
ldr r3 , =0xfff00000
and r2 , r2 , r3
orr r2 , r2 , r1
b m m u _ e n a b l e
.align 5
/* Run in a single cache-line */
mmu_enable :
mcr p15 , 0 , r0 , c1 , c0 , 0
nop
nop
mov p c , r2
skip_hw_init :
# endif
/* Set up the stack */
stack_setup :
ldr r0 , =CONFIG_SYS_UBOOT_BASE / * b a s e o f c o p y i n D R A M * /
sub r0 , r0 , #C O N F I G _ S Y S _ M A L L O C _ L E N / * m a l l o c a r e a * /
sub r0 , r0 , #G E N E R A T E D _ G B L _ D A T A _ S I Z E / * b d i n f o * /
sub s p , r0 , #12 / * l e a v e 3 w o r d s f o r a b o r t - s t a c k * /
bic s p , s p , #7 / * 8 - b y t e a l i g n m e n t f o r A B I c o m p l i a n c e * /
clear_bss :
ldr r0 , _ b s s _ s t a r t / * f i n d s t a r t o f b s s s e g m e n t * /
ldr r1 , _ b s s _ e n d / * s t o p h e r e * /
mov r2 , #0 / * c l e a r * /
clbss_l :
str r2 , [ r0 ] / * c l e a r l o o p . . . * /
add r0 , r0 , #4
cmp r0 , r1
blo c l b s s _ l
# ifndef C O N F I G _ N A N D _ S P L
ldr p c , _ s t a r t _ a r m b o o t
_start_armboot :
.word start_armboot
# else
b n a n d _ b o o t
/* .word nand_boot*/
# endif
# endif / * #i f ! d e f i n e d ( C O N F I G _ S Y S _ A R M _ W I T H O U T _ R E L O C ) * /
# ifdef C O N F I G _ E N A B L E _ M M U
_mmu_table_base :
.word mmu_table
@ -687,14 +498,7 @@ phy_last_jump:
/* Save user registers (now in svc mode) r0-r12 */
stmia s p , { r0 - r12 }
# if d e f i n e d ( C O N F I G _ S Y S _ A R M _ W I T H O U T _ R E L O C )
ldr r2 , _ a r m b o o t _ s t a r t
sub r2 , r2 , #( C O N F I G _ S Y S _ M A L L O C _ L E N )
/* set base 2 words into abort stack */
sub r2 , r2 , #( G E N E R A T E D _ G B L _ D A T A _ S I Z E + 8 )
# else
ldr r2 , I R Q _ S T A C K _ S T A R T _ I N
# endif
/* get values for "aborted" pc and cpsr (into parm regs) */
ldmia r2 , { r2 - r3 }
/* grab pointer to old stack */
@ -709,16 +513,7 @@ phy_last_jump:
.endm
.macro get_bad_stack
# if d e f i n e d ( C O N F I G _ S Y S _ A R M _ W I T H O U T _ R E L O C )
/* setup our mode stack (enter in banked mode) */
ldr r13 , _ a r m b o o t _ s t a r t
/* move past malloc pool */
sub r13 , r13 , #( C O N F I G _ S Y S _ M A L L O C _ L E N )
/* move to reserved a couple spots for abort stack */
sub r13 , r13 , #( G E N E R A T E D _ G B L _ D A T A _ S I Z E + 8 )
# else
ldr r13 , I R Q _ S T A C K _ S T A R T _ I N @ setup our mode stack
# endif
/* save caller lr in position 0 of saved stack */
str l r , [ r13 ]
@ -743,16 +538,7 @@ phy_last_jump:
sub r13 , r13 , #4
/* save R0's value. */
str r0 , [ r13 ]
# if d e f i n e d ( C O N F I G _ S Y S _ A R M _ W I T H O U T _ R E L O C )
/* get data regions start */
ldr r0 , _ a r m b o o t _ s t a r t
/* move past malloc pool */
sub r0 , r0 , #( C O N F I G _ S Y S _ M A L L O C _ L E N )
/* move past gbl and a couple spots for abort stack */
sub r0 , r0 , #( G E N E R A T E D _ G B L _ D A T A _ S I Z E + 8 )
# else
ldr r13 , I R Q _ S T A C K _ S T A R T _ I N @ setup our mode stack
# endif
/* save caller lr in position 0 of saved stack */
str l r , [ r0 ]
/* get the spsr */