Use available DM stm32_timer driver instead of dedicated mach-stm32/stm32fx/timer.c. Remove all defines or files previously used for timer usage in arch/arm/include/asm/arch-stm32fx and in arch/arm/mach-stm32/stm32fx Enable DM STM32_TIMER for STM32F4/F7 and H7. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>master
Patrice Chotard
7 years ago
committed by
Tom Rini
parent
cd389c03f2
commit
aa5e3e22f4
@ -1,15 +0,0 @@ |
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/*
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* Copyright (C) 2016, STMicroelectronics - All Rights Reserved |
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* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef __STM32_DEFS_H__ |
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#define __STM32_DEFS_H__ |
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#include <asm/arch/stm32_periph.h> |
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int clock_setup(enum periph_clock); |
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#endif |
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@ -1,53 +0,0 @@ |
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/*
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* Copyright (C) 2016, STMicroelectronics - All Rights Reserved |
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* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef _STM32_GPT_H |
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#define _STM32_GPT_H |
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#include <asm/arch/stm32.h> |
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struct gpt_regs { |
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u32 cr1; |
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u32 cr2; |
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u32 smcr; |
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u32 dier; |
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u32 sr; |
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u32 egr; |
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u32 ccmr1; |
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u32 ccmr2; |
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u32 ccer; |
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u32 cnt; |
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u32 psc; |
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u32 arr; |
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u32 reserved; |
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u32 ccr1; |
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u32 ccr2; |
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u32 ccr3; |
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u32 ccr4; |
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u32 reserved1; |
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u32 dcr; |
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u32 dmar; |
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u32 tim2_5_or; |
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}; |
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struct gpt_regs *const gpt1_regs_ptr = |
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(struct gpt_regs *)TIM2_BASE; |
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/* Timer control1 register */ |
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#define GPT_CR1_CEN BIT(0) |
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#define GPT_MODE_AUTO_RELOAD BIT(7) |
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/* Auto reload register for free running config */ |
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#define GPT_FREE_RUNNING 0xFFFFFFFF |
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/* Timer, HZ specific defines */ |
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#define CONFIG_STM32_HZ 1000 |
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/* Timer Event Generation registers */ |
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#define TIM_EGR_UG BIT(0) |
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#endif |
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@ -1,15 +0,0 @@ |
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/*
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* Copyright (C) 2016, STMicroelectronics - All Rights Reserved |
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* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef __STM32_DEFS_H__ |
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#define __STM32_DEFS_H__ |
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#include <asm/arch/stm32_periph.h> |
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int clock_setup(enum periph_clock); |
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#endif |
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@ -1,11 +0,0 @@ |
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# (C) Copyright 2015
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# Kamil Lulko, <kamil.lulko@gmail.com>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += timer.o
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@ -1,115 +0,0 @@ |
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/*
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* (C) Copyright 2015 |
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* Kamil Lulko, <kamil.lulko@gmail.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <stm32_rcc.h> |
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#include <asm/io.h> |
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#include <asm/armv7m.h> |
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#include <asm/arch/stm32.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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#define STM32_TIM2_BASE (STM32_APB1PERIPH_BASE + 0x0000) |
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#define RCC_APB1ENR_TIM2EN (1 << 0) |
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struct stm32_tim2_5 { |
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u32 cr1; |
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u32 cr2; |
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u32 smcr; |
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u32 dier; |
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u32 sr; |
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u32 egr; |
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u32 ccmr1; |
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u32 ccmr2; |
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u32 ccer; |
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u32 cnt; |
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u32 psc; |
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u32 arr; |
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u32 reserved1; |
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u32 ccr1; |
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u32 ccr2; |
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u32 ccr3; |
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u32 ccr4; |
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u32 reserved2; |
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u32 dcr; |
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u32 dmar; |
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u32 or; |
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}; |
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#define TIM_CR1_CEN (1 << 0) |
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#define TIM_EGR_UG (1 << 0) |
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int timer_init(void) |
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{ |
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struct stm32_tim2_5 *tim = (struct stm32_tim2_5 *)STM32_TIM2_BASE; |
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setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_TIM2EN); |
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writel(((CONFIG_SYS_CLK_FREQ / 2) / CONFIG_SYS_HZ_CLOCK) - 1, |
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&tim->psc); |
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writel(0xFFFFFFFF, &tim->arr); |
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writel(TIM_CR1_CEN, &tim->cr1); |
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setbits_le32(&tim->egr, TIM_EGR_UG); |
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gd->arch.tbl = 0; |
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gd->arch.tbu = 0; |
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gd->arch.lastinc = 0; |
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return 0; |
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} |
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ulong get_timer(ulong base) |
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{ |
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return (get_ticks() / (CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ)) - base; |
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} |
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unsigned long long get_ticks(void) |
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{ |
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struct stm32_tim2_5 *tim = (struct stm32_tim2_5 *)STM32_TIM2_BASE; |
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u32 now; |
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now = readl(&tim->cnt); |
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if (now >= gd->arch.lastinc) |
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gd->arch.tbl += (now - gd->arch.lastinc); |
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else |
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gd->arch.tbl += (0xFFFFFFFF - gd->arch.lastinc) + now; |
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gd->arch.lastinc = now; |
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return gd->arch.tbl; |
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} |
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void reset_timer(void) |
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{ |
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struct stm32_tim2_5 *tim = (struct stm32_tim2_5 *)STM32_TIM2_BASE; |
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gd->arch.lastinc = readl(&tim->cnt); |
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gd->arch.tbl = 0; |
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} |
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/* delay x useconds */ |
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void __udelay(ulong usec) |
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{ |
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unsigned long long start; |
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start = get_ticks(); /* get current timestamp */ |
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while ((get_ticks() - start) < usec) |
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; /* loop till time has passed */ |
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} |
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/*
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* This function is derived from PowerPC code (timebase clock frequency). |
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* On ARM it returns the number of timer ticks per second. |
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*/ |
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ulong get_tbclk(void) |
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{ |
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return CONFIG_SYS_HZ_CLOCK; |
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} |
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@ -1,8 +0,0 @@ |
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#
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# Copyright (C) 2016, STMicroelectronics - All Rights Reserved
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# Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += timer.o
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@ -1,113 +0,0 @@ |
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/*
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* Copyright (C) 2016, STMicroelectronics - All Rights Reserved |
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* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <stm32_rcc.h> |
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#include <asm/io.h> |
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#include <asm/arch/stm32.h> |
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#include <asm/arch/stm32_defs.h> |
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#include <asm/arch/gpt.h> |
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#define READ_TIMER() (readl(&gpt1_regs_ptr->cnt) & GPT_FREE_RUNNING) |
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#define GPT_RESOLUTION (CONFIG_SYS_HZ_CLOCK/CONFIG_STM32_HZ) |
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DECLARE_GLOBAL_DATA_PTR; |
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#define timestamp gd->arch.tbl |
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#define lastdec gd->arch.lastinc |
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int timer_init(void) |
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{ |
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/* Timer2 clock configuration */ |
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clock_setup(TIMER2_CLOCK_CFG); |
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/* Stop the timer */ |
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writel(readl(&gpt1_regs_ptr->cr1) & ~GPT_CR1_CEN, &gpt1_regs_ptr->cr1); |
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writel((CONFIG_SYS_CLK_FREQ / 2 / CONFIG_SYS_HZ_CLOCK) - 1, |
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&gpt1_regs_ptr->psc); |
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/* Configure timer for auto-reload */ |
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writel(readl(&gpt1_regs_ptr->cr1) | GPT_MODE_AUTO_RELOAD, |
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&gpt1_regs_ptr->cr1); |
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/* load value for free running */ |
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writel(GPT_FREE_RUNNING, &gpt1_regs_ptr->arr); |
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/* start timer */ |
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writel(readl(&gpt1_regs_ptr->cr1) | GPT_CR1_CEN, &gpt1_regs_ptr->cr1); |
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writel(readl(&gpt1_regs_ptr->egr) | TIM_EGR_UG, &gpt1_regs_ptr->egr); |
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/* Reset the timer */ |
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lastdec = READ_TIMER(); |
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timestamp = 0; |
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return 0; |
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} |
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/*
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* timer without interrupts |
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*/ |
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ulong get_timer(ulong base) |
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{ |
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return (get_timer_masked() / GPT_RESOLUTION) - base; |
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} |
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void __udelay(unsigned long usec) |
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{ |
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ulong tmo; |
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ulong start = get_timer_masked(); |
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ulong tenudelcnt = CONFIG_SYS_HZ_CLOCK / (1000 * 100); |
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ulong rndoff; |
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rndoff = (usec % 10) ? 1 : 0; |
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/* tenudelcnt timer tick gives 10 microsecconds delay */ |
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tmo = ((usec / 10) + rndoff) * tenudelcnt; |
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while ((ulong) (get_timer_masked() - start) < tmo) |
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; |
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} |
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ulong get_timer_masked(void) |
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{ |
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ulong now = READ_TIMER(); |
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if (now >= lastdec) { |
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/* normal mode */ |
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timestamp += now - lastdec; |
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} else { |
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/* we have an overflow ... */ |
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timestamp += now + GPT_FREE_RUNNING - lastdec; |
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} |
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lastdec = now; |
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return timestamp; |
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} |
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void udelay_masked(unsigned long usec) |
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{ |
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return udelay(usec); |
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} |
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/*
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* This function is derived from PowerPC code (read timebase as long long). |
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* On ARM it just returns the timer value. |
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*/ |
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unsigned long long get_ticks(void) |
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{ |
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return get_timer(0); |
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} |
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/*
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* This function is derived from PowerPC code (timebase clock frequency). |
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* On ARM it returns the number of timer ticks per second. |
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*/ |
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ulong get_tbclk(void) |
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{ |
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return CONFIG_STM32_HZ; |
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} |
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