commit
aa7077fcee
@ -0,0 +1,200 @@ |
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/*
|
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* TI PHY drivers |
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* |
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* SPDX-License-Identifier: GPL-2.0 |
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* |
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*/ |
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#include <common.h> |
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#include <phy.h> |
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|
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/* TI DP83867 */ |
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#define DP83867_DEVADDR 0x1f |
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|
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#define MII_DP83867_PHYCTRL 0x10 |
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#define MII_DP83867_MICR 0x12 |
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#define DP83867_CTRL 0x1f |
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|
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/* Extended Registers */ |
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#define DP83867_RGMIICTL 0x0032 |
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#define DP83867_RGMIIDCTL 0x0086 |
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|
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#define DP83867_SW_RESET BIT(15) |
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#define DP83867_SW_RESTART BIT(14) |
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|
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/* MICR Interrupt bits */ |
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#define MII_DP83867_MICR_AN_ERR_INT_EN BIT(15) |
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#define MII_DP83867_MICR_SPEED_CHNG_INT_EN BIT(14) |
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#define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN BIT(13) |
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#define MII_DP83867_MICR_PAGE_RXD_INT_EN BIT(12) |
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#define MII_DP83867_MICR_AUTONEG_COMP_INT_EN BIT(11) |
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#define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN BIT(10) |
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#define MII_DP83867_MICR_FALSE_CARRIER_INT_EN BIT(8) |
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#define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4) |
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#define MII_DP83867_MICR_WOL_INT_EN BIT(3) |
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#define MII_DP83867_MICR_XGMII_ERR_INT_EN BIT(2) |
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#define MII_DP83867_MICR_POL_CHNG_INT_EN BIT(1) |
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#define MII_DP83867_MICR_JABBER_INT_EN BIT(0) |
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|
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/* RGMIICTL bits */ |
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#define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1) |
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#define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0) |
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|
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/* PHY CTRL bits */ |
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#define DP83867_PHYCR_FIFO_DEPTH_SHIFT 14 |
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|
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/* RGMIIDCTL bits */ |
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#define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4 |
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|
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#define MII_MMD_CTRL 0x0d /* MMD Access Control Register */ |
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#define MII_MMD_DATA 0x0e /* MMD Access Data Register */ |
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|
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/* MMD Access Control register fields */ |
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#define MII_MMD_CTRL_DEVAD_MASK 0x1f /* Mask MMD DEVAD*/ |
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#define MII_MMD_CTRL_ADDR 0x0000 /* Address */ |
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#define MII_MMD_CTRL_NOINCR 0x4000 /* no post increment */ |
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#define MII_MMD_CTRL_INCR_RDWT 0x8000 /* post increment on reads & writes */ |
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#define MII_MMD_CTRL_INCR_ON_WT 0xC000 /* post increment on writes only */ |
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|
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/**
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* phy_read_mmd_indirect - reads data from the MMD registers |
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* @phydev: The PHY device bus |
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* @prtad: MMD Address |
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* @devad: MMD DEVAD |
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* @addr: PHY address on the MII bus |
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* |
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* Description: it reads data from the MMD registers (clause 22 to access to |
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* clause 45) of the specified phy address. |
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* To read these registers we have: |
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* 1) Write reg 13 // DEVAD
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* 2) Write reg 14 // MMD Address
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* 3) Write reg 13 // MMD Data Command for MMD DEVAD
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* 3) Read reg 14 // Read MMD data
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*/ |
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int phy_read_mmd_indirect(struct phy_device *phydev, int prtad, |
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int devad, int addr) |
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{ |
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int value = -1; |
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/* Write the desired MMD Devad */ |
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phy_write(phydev, addr, MII_MMD_CTRL, devad); |
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|
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/* Write the desired MMD register address */ |
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phy_write(phydev, addr, MII_MMD_DATA, prtad); |
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/* Select the Function : DATA with no post increment */ |
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phy_write(phydev, addr, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); |
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|
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/* Read the content of the MMD's selected register */ |
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value = phy_read(phydev, addr, MII_MMD_DATA); |
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return value; |
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} |
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|
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/**
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* phy_write_mmd_indirect - writes data to the MMD registers |
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* @phydev: The PHY device |
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* @prtad: MMD Address |
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* @devad: MMD DEVAD |
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* @addr: PHY address on the MII bus |
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* @data: data to write in the MMD register |
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* |
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* Description: Write data from the MMD registers of the specified |
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* phy address. |
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* To write these registers we have: |
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* 1) Write reg 13 // DEVAD
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* 2) Write reg 14 // MMD Address
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* 3) Write reg 13 // MMD Data Command for MMD DEVAD
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* 3) Write reg 14 // Write MMD data
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*/ |
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void phy_write_mmd_indirect(struct phy_device *phydev, int prtad, |
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int devad, int addr, u32 data) |
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{ |
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/* Write the desired MMD Devad */ |
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phy_write(phydev, addr, MII_MMD_CTRL, devad); |
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|
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/* Write the desired MMD register address */ |
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phy_write(phydev, addr, MII_MMD_DATA, prtad); |
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/* Select the Function : DATA with no post increment */ |
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phy_write(phydev, addr, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); |
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|
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/* Write the data into MMD's selected register */ |
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phy_write(phydev, addr, MII_MMD_DATA, data); |
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} |
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|
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/**
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* phy_interface_is_rgmii - Convenience function for testing if a PHY interface |
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* is RGMII (all variants) |
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* @phydev: the phy_device struct |
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*/ |
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static inline bool phy_interface_is_rgmii(struct phy_device *phydev) |
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{ |
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return phydev->interface >= PHY_INTERFACE_MODE_RGMII && |
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phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID; |
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} |
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/* User setting - can be taken from DTS */ |
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#define RX_ID_DELAY 8 |
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#define TX_ID_DELAY 0xa |
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#define FIFO_DEPTH 1 |
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static int dp83867_config(struct phy_device *phydev) |
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{ |
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unsigned int val, delay; |
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int ret; |
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/* Restart the PHY. */ |
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val = phy_read(phydev, MDIO_DEVAD_NONE, DP83867_CTRL); |
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phy_write(phydev, MDIO_DEVAD_NONE, DP83867_CTRL, |
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val | DP83867_SW_RESTART); |
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if (phy_interface_is_rgmii(phydev)) { |
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ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL, |
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(FIFO_DEPTH << DP83867_PHYCR_FIFO_DEPTH_SHIFT)); |
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if (ret) |
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return ret; |
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} |
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if ((phydev->interface >= PHY_INTERFACE_MODE_RGMII_ID) && |
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(phydev->interface <= PHY_INTERFACE_MODE_RGMII_RXID)) { |
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val = phy_read_mmd_indirect(phydev, DP83867_RGMIICTL, |
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DP83867_DEVADDR, phydev->addr); |
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) |
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val |= (DP83867_RGMII_TX_CLK_DELAY_EN | |
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DP83867_RGMII_RX_CLK_DELAY_EN); |
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) |
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val |= DP83867_RGMII_TX_CLK_DELAY_EN; |
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) |
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val |= DP83867_RGMII_RX_CLK_DELAY_EN; |
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phy_write_mmd_indirect(phydev, DP83867_RGMIICTL, |
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DP83867_DEVADDR, phydev->addr, val); |
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delay = (RX_ID_DELAY | |
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(TX_ID_DELAY << DP83867_RGMII_TX_CLK_DELAY_SHIFT)); |
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phy_write_mmd_indirect(phydev, DP83867_RGMIIDCTL, |
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DP83867_DEVADDR, phydev->addr, delay); |
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} |
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genphy_config_aneg(phydev); |
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return 0; |
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} |
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static struct phy_driver DP83867_driver = { |
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.name = "TI DP83867", |
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.uid = 0x2000a231, |
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.mask = 0xfffffff0, |
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.features = PHY_GBIT_FEATURES, |
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.config = &dp83867_config, |
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.startup = &genphy_startup, |
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.shutdown = &genphy_shutdown, |
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}; |
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int phy_ti_init(void) |
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{ |
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phy_register(&DP83867_driver); |
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return 0; |
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} |
@ -0,0 +1,257 @@ |
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/*
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* Copyright (C) 2015 Nathan Rossi <nathan@nathanrossi.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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* |
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* The following Boot Header format/structures and values are defined in the |
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* following documents: |
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* * Xilinx Zynq-7000 Technical Reference Manual (Section 6.3) |
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* * Xilinx Zynq-7000 Software Developers Guide (Appendix A.7 and A.8) |
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* |
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* Expected Header Size = 0x8C0 |
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* Forced as 'little' endian, 32-bit words |
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* |
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* 0x 0 - Interrupt Table (8 words) |
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* ... (Default value = 0xeafffffe) |
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* 0x 1f |
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* 0x 20 - Width Detection |
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* * DEFAULT_WIDTHDETECTION 0xaa995566 |
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* 0x 24 - Image Identifier |
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* * DEFAULT_IMAGEIDENTIFIER 0x584c4e58 |
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* 0x 28 - Encryption |
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* * 0x00000000 - None |
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* * 0xa5c3c5a3 - eFuse |
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* * 0x3a5c3c5a - bbRam |
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* 0x 2C - User Field |
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* 0x 30 - Image Offset |
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* 0x 34 - Image Size |
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* 0x 38 - Reserved (0x00000000) (according to spec) |
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* * FSBL defines this field for Image Destination Address. |
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* 0x 3C - Image Load |
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* 0x 40 - Image Stored Size |
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* 0x 44 - Reserved (0x00000000) (according to spec) |
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* * FSBL defines this field for QSPI configuration Data. |
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* 0x 48 - Checksum |
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* 0x 4c - Unused (21 words) |
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* ... |
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* 0x 9c |
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* 0x a0 - Register Initialization, 256 Address and Data word pairs |
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* * List is terminated with an address of 0xffffffff or |
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* ... * at the max number of entries |
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* 0x89c |
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* 0x8a0 - Unused (8 words) |
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* ... |
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* 0x8bf |
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* 0x8c0 - Data/Image starts here or above |
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*/ |
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#include "imagetool.h" |
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#include "mkimage.h" |
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#include <image.h> |
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#define HEADER_INTERRUPT_DEFAULT (cpu_to_le32(0xeafffffe)) |
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#define HEADER_REGINIT_NULL (cpu_to_le32(0xffffffff)) |
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#define HEADER_WIDTHDETECTION (cpu_to_le32(0xaa995566)) |
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#define HEADER_IMAGEIDENTIFIER (cpu_to_le32(0x584c4e58)) |
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enum { |
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ENCRYPTION_EFUSE = 0xa5c3c5a3, |
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ENCRYPTION_BBRAM = 0x3a5c3c5a, |
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ENCRYPTION_NONE = 0x0, |
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}; |
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|
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struct zynq_reginit { |
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uint32_t address; |
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uint32_t data; |
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}; |
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#define HEADER_INTERRUPT_VECTORS 8 |
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#define HEADER_REGINITS 256 |
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|
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struct zynq_header { |
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uint32_t interrupt_vectors[HEADER_INTERRUPT_VECTORS]; /* 0x0 */ |
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uint32_t width_detection; /* 0x20 */ |
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uint32_t image_identifier; /* 0x24 */ |
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uint32_t encryption; /* 0x28 */ |
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uint32_t user_field; /* 0x2c */ |
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uint32_t image_offset; /* 0x30 */ |
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uint32_t image_size; /* 0x34 */ |
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uint32_t __reserved1; /* 0x38 */ |
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uint32_t image_load; /* 0x3c */ |
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uint32_t image_stored_size; /* 0x40 */ |
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uint32_t __reserved2; /* 0x44 */ |
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uint32_t checksum; /* 0x48 */ |
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uint32_t __reserved3[21]; /* 0x4c */ |
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struct zynq_reginit register_init[HEADER_REGINITS]; /* 0xa0 */ |
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uint32_t __reserved4[8]; /* 0x8a0 */ |
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}; |
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|
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static struct zynq_header zynqimage_header; |
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|
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static uint32_t zynqimage_checksum(struct zynq_header *ptr) |
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{ |
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uint32_t checksum = 0; |
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|
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if (ptr == NULL) |
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return 0; |
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|
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checksum += le32_to_cpu(ptr->width_detection); |
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checksum += le32_to_cpu(ptr->image_identifier); |
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checksum += le32_to_cpu(ptr->encryption); |
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checksum += le32_to_cpu(ptr->user_field); |
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checksum += le32_to_cpu(ptr->image_offset); |
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checksum += le32_to_cpu(ptr->image_size); |
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checksum += le32_to_cpu(ptr->__reserved1); |
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checksum += le32_to_cpu(ptr->image_load); |
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checksum += le32_to_cpu(ptr->image_stored_size); |
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checksum += le32_to_cpu(ptr->__reserved2); |
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checksum = ~checksum; |
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|
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return cpu_to_le32(checksum); |
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} |
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|
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static void zynqimage_default_header(struct zynq_header *ptr) |
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{ |
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int i; |
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|
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if (ptr == NULL) |
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return; |
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|
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ptr->width_detection = HEADER_WIDTHDETECTION; |
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ptr->image_identifier = HEADER_IMAGEIDENTIFIER; |
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ptr->encryption = cpu_to_le32(ENCRYPTION_NONE); |
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|
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/* Setup not-supported/constant/reserved fields */ |
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for (i = 0; i < HEADER_INTERRUPT_VECTORS; i++) |
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ptr->interrupt_vectors[i] = HEADER_INTERRUPT_DEFAULT; |
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|
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for (i = 0; i < HEADER_REGINITS; i++) { |
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ptr->register_init[i].address = HEADER_REGINIT_NULL; |
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ptr->register_init[i].data = HEADER_REGINIT_NULL; |
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} |
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|
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/*
|
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* Certain reserved fields are required to be set to 0, ensure they are |
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* set as such. |
||||
*/ |
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ptr->__reserved1 = 0x0; |
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ptr->__reserved2 = 0x0; |
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} |
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|
||||
/* mkimage glue functions */ |
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static int zynqimage_verify_header(unsigned char *ptr, int image_size, |
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struct image_tool_params *params) |
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{ |
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struct zynq_header *zynqhdr = (struct zynq_header *)ptr; |
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|
||||
if (image_size < sizeof(struct zynq_header)) |
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return -1; |
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|
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if (zynqhdr->width_detection != HEADER_WIDTHDETECTION) |
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return -1; |
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if (zynqhdr->image_identifier != HEADER_IMAGEIDENTIFIER) |
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return -1; |
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|
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if (zynqimage_checksum(zynqhdr) != zynqhdr->checksum) |
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return -1; |
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|
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return 0; |
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} |
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|
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static void zynqimage_print_header(const void *ptr) |
||||
{ |
||||
struct zynq_header *zynqhdr = (struct zynq_header *)ptr; |
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int i; |
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|
||||
printf("Image Type : Xilinx Zynq Boot Image support\n"); |
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printf("Image Offset : 0x%08x\n", le32_to_cpu(zynqhdr->image_offset)); |
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printf("Image Size : %lu bytes (%lu bytes packed)\n", |
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(unsigned long)le32_to_cpu(zynqhdr->image_size), |
||||
(unsigned long)le32_to_cpu(zynqhdr->image_stored_size)); |
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printf("Image Load : 0x%08x\n", le32_to_cpu(zynqhdr->image_load)); |
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printf("User Field : 0x%08x\n", le32_to_cpu(zynqhdr->user_field)); |
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printf("Checksum : 0x%08x\n", le32_to_cpu(zynqhdr->checksum)); |
||||
|
||||
for (i = 0; i < HEADER_INTERRUPT_VECTORS; i++) { |
||||
if (zynqhdr->interrupt_vectors[i] == HEADER_INTERRUPT_DEFAULT) |
||||
continue; |
||||
|
||||
printf("Modified Interrupt Vector Address [%d]: 0x%08x\n", i, |
||||
le32_to_cpu(zynqhdr->interrupt_vectors[i])); |
||||
} |
||||
|
||||
for (i = 0; i < HEADER_REGINITS; i++) { |
||||
if (zynqhdr->register_init[i].address == HEADER_REGINIT_NULL) |
||||
break; |
||||
|
||||
if (i == 0) |
||||
printf("Custom Register Initialization:\n"); |
||||
|
||||
printf(" @ 0x%08x -> 0x%08x\n", |
||||
le32_to_cpu(zynqhdr->register_init[i].address), |
||||
le32_to_cpu(zynqhdr->register_init[i].data)); |
||||
} |
||||
} |
||||
|
||||
static int zynqimage_check_params(struct image_tool_params *params) |
||||
{ |
||||
if (!params) |
||||
return 0; |
||||
|
||||
if (params->addr != 0x0) { |
||||
fprintf(stderr, "Error: Load Address cannot be specified.\n"); |
||||
return -1; |
||||
} |
||||
|
||||
/*
|
||||
* If the entry point is specified ensure it is 64 byte aligned. |
||||
*/ |
||||
if (params->eflag && (params->ep % 64 != 0)) { |
||||
fprintf(stderr, |
||||
"Error: Entry Point must be aligned to a 64-byte boundary.\n"); |
||||
return -1; |
||||
} |
||||
|
||||
return !((params->lflag || params->dflag) || |
||||
(params->dflag && params->eflag)); |
||||
} |
||||
|
||||
static int zynqimage_check_image_types(uint8_t type) |
||||
{ |
||||
if (type == IH_TYPE_ZYNQIMAGE) |
||||
return EXIT_SUCCESS; |
||||
return EXIT_FAILURE; |
||||
} |
||||
|
||||
static void zynqimage_set_header(void *ptr, struct stat *sbuf, int ifd, |
||||
struct image_tool_params *params) |
||||
{ |
||||
struct zynq_header *zynqhdr = (struct zynq_header *)ptr; |
||||
zynqimage_default_header(zynqhdr); |
||||
|
||||
/* place image directly after header */ |
||||
zynqhdr->image_offset = |
||||
cpu_to_le32((uint32_t)sizeof(struct zynq_header)); |
||||
zynqhdr->image_size = cpu_to_le32((uint32_t)sbuf->st_size); |
||||
zynqhdr->image_stored_size = zynqhdr->image_size; |
||||
zynqhdr->image_load = 0x0; |
||||
if (params->eflag) |
||||
zynqhdr->image_load = cpu_to_le32((uint32_t)params->ep); |
||||
|
||||
zynqhdr->checksum = zynqimage_checksum(zynqhdr); |
||||
} |
||||
|
||||
U_BOOT_IMAGE_TYPE( |
||||
zynqimage, |
||||
"Xilinx Zynq Boot Image support", |
||||
sizeof(struct zynq_header), |
||||
(void *)&zynqimage_header, |
||||
zynqimage_check_params, |
||||
zynqimage_verify_header, |
||||
zynqimage_print_header, |
||||
zynqimage_set_header, |
||||
NULL, |
||||
zynqimage_check_image_types, |
||||
NULL, |
||||
NULL |
||||
); |
Loading…
Reference in new issue