master
Wolfgang Denk
19 years ago
committed by
Wolfgang Denk
commit
ab07b6c221
@ -0,0 +1,48 @@ |
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#
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# Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
|
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#
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# See file CREDITS for list of people who contributed to this
|
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# project.
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#
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# This program is free software; you can redistribute it and/or
|
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
|
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#
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
|
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#
|
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# You should have received a copy of the GNU General Public License
|
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# along with this program; if not, write to the Free Software
|
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(BOARD).a
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COBJS := $(BOARD).o pci.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) |
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$(AR) crv $@ $(OBJS)
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clean: |
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rm -f $(SOBJS) $(OBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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@ -0,0 +1,33 @@ |
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#
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# Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
|
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#
|
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# See file CREDITS for list of people who contributed to this
|
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# project.
|
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#
|
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# This program is free software; you can redistribute it and/or
|
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
|
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#
|
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
|
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#
|
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# You should have received a copy of the GNU General Public License
|
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# along with this program; if not, write to the Free Software
|
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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#
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# MPC8349ITX
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#
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TEXT_BASE = 0xFEF00000
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ifneq ($(OBJTREE),$(SRCTREE)) |
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# We are building u-boot in a separate directory, use generated
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# .lds script from OBJTREE directory.
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LDSCRIPT := $(OBJTREE)/board/$(BOARDDIR)/u-boot.lds
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endif |
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@ -0,0 +1,477 @@ |
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/*
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* Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <ioports.h> |
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#include <mpc83xx.h> |
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#include <i2c.h> |
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#include <spd.h> |
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#include <miiphy.h> |
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#ifdef CONFIG_PCI |
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#include <asm/mpc8349_pci.h> |
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#include <pci.h> |
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#endif |
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#ifdef CONFIG_SPD_EEPROM |
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#include <spd_sdram.h> |
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#else |
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#include <asm/mmu.h> |
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#endif |
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#if defined(CONFIG_OF_FLAT_TREE) |
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#include <ft_build.h> |
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#endif |
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|
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#ifndef CONFIG_SPD_EEPROM |
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/*************************************************************************
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* fixed sdram init -- doesn't use serial presence detect. |
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************************************************************************/ |
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int fixed_sdram(void) |
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{ |
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volatile immap_t *im = (immap_t *) CFG_IMMR; |
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u32 ddr_size; /* The size of RAM, in bytes */ |
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u32 ddr_size_log2 = 0; |
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for (ddr_size = CFG_DDR_SIZE * 0x100000; ddr_size > 1; ddr_size >>= 1) { |
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if (ddr_size & 1) { |
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return -1; |
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} |
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ddr_size_log2++; |
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} |
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im->sysconf.ddrlaw[0].ar = |
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LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); |
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im->sysconf.ddrlaw[0].bar = (CFG_DDR_SDRAM_BASE >> 12) & 0xfffff; |
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|
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/* Only one CS0 for DDR */ |
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im->ddr.csbnds[0].csbnds = 0x0000000f; |
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im->ddr.cs_config[0] = CFG_DDR_CONFIG; |
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debug("cs0_bnds = 0x%08x\n", im->ddr.csbnds[0].csbnds); |
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debug("cs0_config = 0x%08x\n", im->ddr.cs_config[0]); |
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debug("DDR:bar=0x%08x\n", im->sysconf.ddrlaw[0].bar); |
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debug("DDR:ar=0x%08x\n", im->sysconf.ddrlaw[0].ar); |
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im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; |
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im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;/* Was "2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT" */ |
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im->ddr.sdram_cfg = SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR; |
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im->ddr.sdram_mode = |
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(0x0000 << SDRAM_MODE_ESD_SHIFT) | (0x0032 << SDRAM_MODE_SD_SHIFT); |
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im->ddr.sdram_interval = |
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(0x0410 << SDRAM_INTERVAL_REFINT_SHIFT) | (0x0100 << |
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SDRAM_INTERVAL_BSTOPRE_SHIFT); |
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im->ddr.sdram_clk_cntl = |
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DDR_SDRAM_CLK_CNTL_SS_EN | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05; |
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udelay(200); |
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im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; |
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debug("DDR:timing_cfg_1=0x%08x\n", im->ddr.timing_cfg_1); |
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debug("DDR:timing_cfg_2=0x%08x\n", im->ddr.timing_cfg_2); |
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debug("DDR:sdram_mode=0x%08x\n", im->ddr.sdram_mode); |
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debug("DDR:sdram_interval=0x%08x\n", im->ddr.sdram_interval); |
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debug("DDR:sdram_cfg=0x%08x\n", im->ddr.sdram_cfg); |
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return CFG_DDR_SIZE; |
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} |
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#endif |
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#ifdef CONFIG_PCI |
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/*
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* Initialize PCI Devices, report devices found |
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*/ |
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#ifndef CONFIG_PCI_PNP |
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static struct pci_config_table pci_mpc83xxmitx_config_table[] = { |
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{ |
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PCI_ANY_ID, |
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PCI_ANY_ID, |
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PCI_ANY_ID, |
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PCI_ANY_ID, |
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0x0f, |
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PCI_ANY_ID, |
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pci_cfgfunc_config_device, |
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{ |
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PCI_ENET0_IOADDR, |
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PCI_ENET0_MEMADDR, |
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PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} |
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}, |
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{} |
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} |
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#endif |
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volatile static struct pci_controller hose[] = { |
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{ |
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#ifndef CONFIG_PCI_PNP |
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config_table:pci_mpc83xxmitx_config_table, |
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#endif |
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}, |
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{ |
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#ifndef CONFIG_PCI_PNP |
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config_table:pci_mpc83xxmitx_config_table, |
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#endif |
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} |
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}; |
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#endif /* CONFIG_PCI */ |
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/* If MPC8349E-mITX is soldered with SDRAM, then initialize it. */ |
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void sdram_init(void) |
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{ |
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volatile immap_t *immap = (immap_t *) CFG_IMMR; |
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volatile lbus83xx_t *lbc = &immap->lbus; |
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#if defined(CFG_BR2_PRELIM) \ |
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&& defined(CFG_OR2_PRELIM) \
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&& defined(CFG_LBLAWBAR2_PRELIM) \
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&& defined(CFG_LBLAWAR2_PRELIM) \
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&& !defined(CONFIG_COMPACT_FLASH) |
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uint *sdram_addr = (uint *) CFG_LBC_SDRAM_BASE; |
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puts("\n SDRAM on Local Bus: "); |
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print_size(CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); |
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/*
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* Setup SDRAM Base and Option Registers, already done in cpu_init.c |
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*/ |
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/*setup mtrpt, lsrt and lbcr for LB bus */ |
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lbc->lbcr = CFG_LBC_LBCR; |
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lbc->mrtpr = CFG_LBC_MRTPR; |
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lbc->lsrt = CFG_LBC_LSRT; |
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asm("sync"); |
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/*
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* Configure the SDRAM controller Machine Mode register. |
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*/ |
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lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */ |
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lbc->lsdmr = CFG_LBC_LSDMR_1; /*0x68636733; precharge all the banks */ |
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asm("sync"); |
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*sdram_addr = 0xff; |
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udelay(100); |
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lbc->lsdmr = CFG_LBC_LSDMR_2; /*0x48636733; auto refresh */ |
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asm("sync"); |
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*sdram_addr = 0xff; /*1 time*/ |
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udelay(100); |
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*sdram_addr = 0xff; /*2 times*/ |
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udelay(100); |
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*sdram_addr = 0xff; /*3 times*/ |
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udelay(100); |
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*sdram_addr = 0xff; /*4 times*/ |
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udelay(100); |
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*sdram_addr = 0xff; /*5 times*/ |
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udelay(100); |
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*sdram_addr = 0xff; /*6 times*/ |
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udelay(100); |
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*sdram_addr = 0xff; /*7 times*/ |
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udelay(100); |
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*sdram_addr = 0xff; /*8 times*/ |
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udelay(100); |
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lbc->lsdmr = CFG_LBC_LSDMR_4; /*0x58636733;mode register write operation */ |
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asm("sync"); |
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*sdram_addr = 0xff; |
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udelay(100); |
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lbc->lsdmr = CFG_LBC_LSDMR_5; /*0x40636733;normal operation */ |
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asm("sync"); |
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*sdram_addr = 0xff; |
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udelay(100); |
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#else |
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puts("SDRAM on Local Bus is NOT available!\n"); |
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#ifdef CFG_BR2_PRELIM |
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lbc->bank[2].br = CFG_BR2_PRELIM; |
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lbc->bank[2].or = CFG_OR2_PRELIM; |
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#endif |
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#ifdef CFG_BR3_PRELIM |
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lbc->bank[3].br = CFG_BR3_PRELIM; |
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lbc->bank[3].or = CFG_OR3_PRELIM; |
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#endif |
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#endif |
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} |
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long int initdram(int board_type) |
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{ |
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volatile immap_t *im = (immap_t *) CFG_IMMR; |
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u32 msize = 0; |
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#ifdef CONFIG_DDR_ECC |
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volatile ddr83xx_t *ddr = &im->ddr; |
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#endif |
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if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) |
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return -1; |
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/* DDR SDRAM - Main SODIMM */ |
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im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; |
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#ifdef CONFIG_SPD_EEPROM |
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msize = spd_sdram(); |
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#else |
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msize = fixed_sdram(); |
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#endif |
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|
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#ifdef CONFIG_DDR_ECC |
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if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) |
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/* Unlike every other board, on the 83xx spd_sdram() returns
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megabytes instead of just bytes. That's why we need to |
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multiple by 1MB when calling ddr_enable_ecc(). */ |
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ddr_enable_ecc(msize * 1048576); |
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#endif |
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/*
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* Initialize SDRAM if it is on local bus. |
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*/ |
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sdram_init(); |
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puts(" DDR RAM: "); |
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/* return total bus SDRAM size(bytes) -- DDR */ |
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return msize * 1024 * 1024; |
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} |
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int checkboard(void) |
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{ |
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puts("Board: Freescale MPC8349E-mITX\n"); |
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return 0; |
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} |
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|
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/*
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* Implement a work-around for a hardware problem with compact |
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* flash. |
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* |
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* Program the UPM if compact flash is enabled. |
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*/ |
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int misc_init_f(void) |
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{ |
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volatile u32 *vsc7385_cpuctrl; |
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|
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/* 0x1c0c0 is the VSC7385 CPU Control (CPUCTRL) Register. The power up
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default of VSC7385 L1_IRQ and L2_IRQ requests are active high. That |
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means it is 0 when the IRQ is not active. This makes the wire-AND |
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logic always assert IRQ7 to CPU even if there is no request from the |
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switch. Since the compact flash and the switch share the same IRQ, |
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the Linux kernel will think that the compact flash is requesting irq |
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and get stuck when it tries to clear the IRQ. Thus we need to set |
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the L2_IRQ0 and L2_IRQ1 to active low. |
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|
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The following code sets the L1_IRQ and L2_IRQ polarity to active low. |
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Without this code, compact flash will not work in Linux because |
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unlike U-Boot, Linux uses the IRQ, so this code is necessary if we |
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don't enable compact flash for U-Boot. |
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*/ |
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|
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vsc7385_cpuctrl = (volatile u32 *)(CFG_VSC7385_BASE + 0x1c0c0); |
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*vsc7385_cpuctrl |= 0x0c; |
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|
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#ifdef CONFIG_COMPACT_FLASH |
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/* UPM Table Configuration Code */ |
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static uint UPMATable[] = { |
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0xcffffc00, 0x0fffff00, 0x0fafff00, 0x0fafff00, |
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0x0faffd00, 0x0faffc04, 0x0ffffc00, 0x3ffffc01, |
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfff7fc00, |
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, |
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0xcffffc00, 0x0fffff00, 0x0ff3ff00, 0x0ff3ff00, |
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0x0ff3fe00, 0x0ffffc00, 0x3ffffc05, 0xfffffc00, |
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, |
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, |
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01 |
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}; |
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volatile immap_t *immap = (immap_t *) CFG_IMMR; |
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volatile lbus83xx_t *lbus = &immap->lbus; |
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|
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lbus->bank[3].br = CFG_BR3_PRELIM; |
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lbus->bank[3].or = CFG_OR3_PRELIM; |
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|
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/* Program the MAMR. RFEN=0, OP=00, UWPL=1, AM=000, DS=01, G0CL=000,
|
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GPL4=0, RLF=0001, WLF=0001, TLF=0001, MAD=000000 |
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*/ |
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lbus->mamr = 0x08404440; |
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|
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upmconfig(0, UPMATable, sizeof(UPMATable) / sizeof(UPMATable[0])); |
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|
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puts("UPMA: Configured for compact flash\n"); |
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#endif |
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|
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return 0; |
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} |
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|
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/*
|
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* Make sure the EEPROM has the HRCW correctly programmed. |
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* Make sure the RTC is correctly programmed. |
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* |
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* The MPC8349E-mITX can be configured to load the HRCW from |
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* EEPROM instead of flash. This is controlled via jumpers |
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* LGPL0, 1, and 3. Normally, these jumpers are set to 000 (all |
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* jumpered), but if they're set to 001 or 010, then the HRCW is |
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* read from the "I2C EEPROM". |
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* |
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* This function makes sure that the I2C EEPROM is programmed |
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* correctly. |
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*/ |
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int misc_init_r(void) |
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{ |
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int rc = 0; |
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|
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#ifdef CONFIG_HARD_I2C |
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|
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unsigned int orig_bus = i2c_get_bus_num();; |
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u8 i2c_data; |
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|
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#ifdef CFG_I2C_RTC_ADDR |
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u8 ds1339_data[17]; |
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#endif |
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|
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#ifdef CFG_I2C_EEPROM_ADDR |
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static u8 eeprom_data[] = /* HRCW data */ |
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{ |
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0xaa, 0x55, 0xaa, |
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0x7c, 0x02, 0x40, 0x05, 0x04, 0x00, 0x00, |
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0x7c, 0x02, 0x41, 0xb4, 0x60, 0xa0, 0x00, |
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}; |
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|
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u8 data[sizeof(eeprom_data)]; |
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#endif |
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|
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printf("Board revision: "); |
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i2c_set_bus_num(1); |
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if (i2c_read(CFG_I2C_8574A_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0) |
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printf("%u.%u (PCF8475A)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01); |
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else if (i2c_read(CFG_I2C_8574_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0) |
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printf("%u.%u (PCF8475)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01); |
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else { |
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printf("Unknown\n"); |
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rc = 1; |
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} |
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|
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#ifdef CFG_I2C_EEPROM_ADDR |
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i2c_set_bus_num(0); |
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|
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if (i2c_read(CFG_I2C_EEPROM_ADDR, 0, 2, data, sizeof(data)) == 0) { |
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if (memcmp(data, eeprom_data, sizeof(data)) != 0) { |
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if (i2c_write |
||||
(CFG_I2C_EEPROM_ADDR, 0, 2, eeprom_data, |
||||
sizeof(eeprom_data)) != 0) { |
||||
puts("Failure writing the HRCW to EEPROM via I2C.\n"); |
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rc = 1; |
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} |
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} |
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} else { |
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puts("Failure reading the HRCW from EEPROM via I2C.\n"); |
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rc = 1; |
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} |
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#endif |
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|
||||
#ifdef CFG_I2C_RTC_ADDR |
||||
i2c_set_bus_num(1); |
||||
|
||||
if (i2c_read(CFG_I2C_RTC_ADDR, 0, 1, ds1339_data, sizeof(ds1339_data)) |
||||
== 0) { |
||||
|
||||
/* Work-around for MPC8349E-mITX bug #13601.
|
||||
If the RTC does not contain valid register values, the DS1339 |
||||
Linux driver will not work. |
||||
*/ |
||||
|
||||
/* Make sure status register bits 6-2 are zero */ |
||||
ds1339_data[0x0f] &= ~0x7c; |
||||
|
||||
/* Check for a valid day register value */ |
||||
ds1339_data[0x03] &= ~0xf8; |
||||
if (ds1339_data[0x03] == 0) { |
||||
ds1339_data[0x03] = 1; |
||||
} |
||||
|
||||
/* Check for a valid date register value */ |
||||
ds1339_data[0x04] &= ~0xc0; |
||||
if ((ds1339_data[0x04] == 0) || |
||||
((ds1339_data[0x04] & 0x0f) > 9) || |
||||
(ds1339_data[0x04] >= 0x32)) { |
||||
ds1339_data[0x04] = 1; |
||||
} |
||||
|
||||
/* Check for a valid month register value */ |
||||
ds1339_data[0x05] &= ~0x60; |
||||
|
||||
if ((ds1339_data[0x05] == 0) || |
||||
((ds1339_data[0x05] & 0x0f) > 9) || |
||||
((ds1339_data[0x05] >= 0x13) |
||||
&& (ds1339_data[0x05] <= 0x19))) { |
||||
ds1339_data[0x05] = 1; |
||||
} |
||||
|
||||
/* Enable Oscillator and rate select */ |
||||
ds1339_data[0x0e] = 0x1c; |
||||
|
||||
/* Work-around for MPC8349E-mITX bug #13330.
|
||||
Ensure that the RTC control register contains the value 0x1c. |
||||
This affects SATA performance. |
||||
*/ |
||||
|
||||
if (i2c_write |
||||
(CFG_I2C_RTC_ADDR, 0, 1, ds1339_data, |
||||
sizeof(ds1339_data))) { |
||||
puts("Failure writing to the RTC via I2C.\n"); |
||||
rc = 1; |
||||
} |
||||
} else { |
||||
puts("Failure reading from the RTC via I2C.\n"); |
||||
rc = 1; |
||||
} |
||||
#endif |
||||
|
||||
i2c_set_bus_num(orig_bus); |
||||
#endif |
||||
|
||||
return rc; |
||||
} |
||||
|
||||
#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) |
||||
void |
||||
ft_board_setup(void *blob, bd_t *bd) |
||||
{ |
||||
u32 *p; |
||||
int len; |
||||
|
||||
#ifdef CONFIG_PCI |
||||
ft_pci_setup(blob, bd); |
||||
#endif |
||||
ft_cpu_setup(blob, bd); |
||||
|
||||
p = ft_get_prop(blob, "/memory/reg", &len); |
||||
if (p != NULL) { |
||||
*p++ = cpu_to_be32(bd->bi_memstart); |
||||
*p = cpu_to_be32(bd->bi_memsize); |
||||
} |
||||
} |
||||
#endif |
||||
@ -0,0 +1,357 @@ |
||||
/*
|
||||
* Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
|
||||
#ifdef CONFIG_PCI |
||||
|
||||
#include <asm/mmu.h> |
||||
#include <asm/global_data.h> |
||||
#include <pci.h> |
||||
#include <asm/mpc8349_pci.h> |
||||
#include <i2c.h> |
||||
#if defined(CONFIG_OF_FLAT_TREE) |
||||
#include <ft_build.h> |
||||
#endif |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
/* System RAM mapped to PCI space */ |
||||
#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE |
||||
#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE |
||||
|
||||
#ifndef CONFIG_PCI_PNP |
||||
static struct pci_config_table pci_mpc8349itx_config_table[] = { |
||||
{ |
||||
PCI_ANY_ID, |
||||
PCI_ANY_ID, |
||||
PCI_ANY_ID, |
||||
PCI_ANY_ID, |
||||
PCI_IDSEL_NUMBER, |
||||
PCI_ANY_ID, |
||||
pci_cfgfunc_config_device, |
||||
{ |
||||
PCI_ENET0_IOADDR, |
||||
PCI_ENET0_MEMADDR, |
||||
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} |
||||
}, |
||||
{} |
||||
}; |
||||
#endif |
||||
|
||||
static struct pci_controller pci_hose[] = { |
||||
{ |
||||
#ifndef CONFIG_PCI_PNP |
||||
config_table:pci_mpc8349itx_config_table, |
||||
#endif |
||||
}, |
||||
{ |
||||
#ifndef CONFIG_PCI_PNP |
||||
config_table:pci_mpc8349itx_config_table, |
||||
#endif |
||||
} |
||||
}; |
||||
|
||||
/**************************************************************************
|
||||
* pci_init_board() |
||||
* |
||||
* NOTICE: PCI2 is not currently supported |
||||
* |
||||
*/ |
||||
void pci_init_board(void) |
||||
{ |
||||
volatile immap_t *immr; |
||||
volatile clk83xx_t *clk; |
||||
volatile law83xx_t *pci_law; |
||||
volatile pot83xx_t *pci_pot; |
||||
volatile pcictrl83xx_t *pci_ctrl; |
||||
volatile pciconf83xx_t *pci_conf; |
||||
u8 reg8; |
||||
u16 reg16; |
||||
u32 reg32; |
||||
u32 dev; |
||||
struct pci_controller *hose; |
||||
|
||||
immr = (immap_t *) CFG_IMMR; |
||||
clk = (clk83xx_t *) & immr->clk; |
||||
pci_law = immr->sysconf.pcilaw; |
||||
pci_pot = immr->ios.pot; |
||||
pci_ctrl = immr->pci_ctrl; |
||||
pci_conf = immr->pci_conf; |
||||
|
||||
hose = &pci_hose[0]; |
||||
|
||||
/*
|
||||
* Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode |
||||
*/ |
||||
|
||||
reg32 = clk->occr; |
||||
udelay(2000); |
||||
|
||||
#ifdef CONFIG_HARD_I2C |
||||
i2c_set_bus_num(1); |
||||
/* Read the PCI_M66EN jumper setting */ |
||||
if ((i2c_read(CFG_I2C_8574_ADDR2, 0, 0, ®8, sizeof(reg8)) == 0) || |
||||
(i2c_read(CFG_I2C_8574A_ADDR2, 0, 0, ®8, sizeof(reg8)) == 0)) { |
||||
if (reg8 & I2C_8574_PCI66) |
||||
clk->occr = 0xff000000; /* 66 MHz PCI */ |
||||
else |
||||
clk->occr = 0xff600001; /* 33 MHz PCI */ |
||||
} else { |
||||
clk->occr = 0xff600001; /* 33 MHz PCI */ |
||||
} |
||||
#else |
||||
clk->occr = 0xff000000; /* 66 MHz PCI */ |
||||
#endif |
||||
|
||||
udelay(2000); |
||||
|
||||
/*
|
||||
* Release PCI RST Output signal |
||||
*/ |
||||
pci_ctrl[0].gcr = 0; |
||||
udelay(2000); |
||||
pci_ctrl[0].gcr = 1; |
||||
|
||||
#ifdef CONFIG_MPC83XX_PCI2 |
||||
pci_ctrl[1].gcr = 0; |
||||
udelay(2000); |
||||
pci_ctrl[1].gcr = 1; |
||||
#endif |
||||
|
||||
/* We need to wait at least a 1sec based on PCI specs */ |
||||
{ |
||||
int i; |
||||
|
||||
for (i = 0; i < 1000; i++) |
||||
udelay(1000); |
||||
} |
||||
|
||||
/*
|
||||
* Configure PCI Local Access Windows |
||||
*/ |
||||
pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR; |
||||
pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G; |
||||
|
||||
pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR; |
||||
pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_32M; |
||||
|
||||
/*
|
||||
* Configure PCI Outbound Translation Windows |
||||
*/ |
||||
|
||||
/* PCI1 mem space - prefetch */ |
||||
pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK; |
||||
pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK; |
||||
pci_pot[0].pocmr = POCMR_EN | POCMR_PREFETCH_EN | POCMR_CM_256M; |
||||
|
||||
/* PCI1 IO space */ |
||||
pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK; |
||||
pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK; |
||||
pci_pot[1].pocmr = POCMR_EN | POCMR_IO | POCMR_CM_16M; |
||||
|
||||
/* PCI1 mmio - non-prefetch mem space */ |
||||
pci_pot[2].potar = (CFG_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK; |
||||
pci_pot[2].pobar = (CFG_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK; |
||||
pci_pot[2].pocmr = POCMR_EN | POCMR_CM_256M; |
||||
|
||||
/*
|
||||
* Configure PCI Inbound Translation Windows |
||||
*/ |
||||
|
||||
/* we need RAM mapped to PCI space for the devices to
|
||||
* access main memory */ |
||||
pci_ctrl[0].pitar1 = 0x0; |
||||
pci_ctrl[0].pibar1 = 0x0; |
||||
pci_ctrl[0].piebar1 = 0x0; |
||||
pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | |
||||
PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1); |
||||
|
||||
hose->first_busno = 0; |
||||
hose->last_busno = 0xff; |
||||
|
||||
/* PCI memory prefetch space */ |
||||
pci_set_region(hose->regions + 0, |
||||
CFG_PCI1_MEM_BASE, |
||||
CFG_PCI1_MEM_PHYS, |
||||
CFG_PCI1_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH); |
||||
|
||||
/* PCI memory space */ |
||||
pci_set_region(hose->regions + 1, |
||||
CFG_PCI1_MMIO_BASE, |
||||
CFG_PCI1_MMIO_PHYS, CFG_PCI1_MMIO_SIZE, PCI_REGION_MEM); |
||||
|
||||
/* PCI IO space */ |
||||
pci_set_region(hose->regions + 2, |
||||
CFG_PCI1_IO_BASE, |
||||
CFG_PCI1_IO_PHYS, CFG_PCI1_IO_SIZE, PCI_REGION_IO); |
||||
|
||||
/* System memory space */ |
||||
pci_set_region(hose->regions + 3, |
||||
CONFIG_PCI_SYS_MEM_BUS, |
||||
CONFIG_PCI_SYS_MEM_PHYS, |
||||
gd->ram_size, PCI_REGION_MEM | PCI_REGION_MEMORY); |
||||
|
||||
hose->region_count = 4; |
||||
|
||||
pci_setup_indirect(hose, |
||||
(CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304)); |
||||
|
||||
pci_register_hose(hose); |
||||
|
||||
/*
|
||||
* Write to Command register |
||||
*/ |
||||
reg16 = 0xff; |
||||
dev = PCI_BDF(hose->first_busno, 0, 0); |
||||
pci_hose_read_config_word(hose, dev, PCI_COMMAND, ®16); |
||||
reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; |
||||
pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16); |
||||
|
||||
/*
|
||||
* Clear non-reserved bits in status register. |
||||
*/ |
||||
pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); |
||||
pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); |
||||
pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); |
||||
|
||||
#ifdef CONFIG_PCI_SCAN_SHOW |
||||
printf("PCI: Bus Dev VenId DevId Class Int\n"); |
||||
#endif |
||||
/*
|
||||
* Hose scan. |
||||
*/ |
||||
hose->last_busno = pci_hose_scan(hose); |
||||
|
||||
#ifdef CONFIG_MPC83XX_PCI2 |
||||
hose = &pci_hose[1]; |
||||
|
||||
/*
|
||||
* Configure PCI Outbound Translation Windows |
||||
*/ |
||||
|
||||
/* PCI2 mem space - prefetch */ |
||||
pci_pot[3].potar = (CFG_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK; |
||||
pci_pot[3].pobar = (CFG_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK; |
||||
pci_pot[3].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_PREFETCH_EN | POCMR_CM_256M; |
||||
|
||||
/* PCI2 IO space */ |
||||
pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK; |
||||
pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK; |
||||
pci_pot[4].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_IO | POCMR_CM_16M; |
||||
|
||||
/* PCI2 mmio - non-prefetch mem space */ |
||||
pci_pot[5].potar = (CFG_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK; |
||||
pci_pot[5].pobar = (CFG_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK; |
||||
pci_pot[5].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_CM_256M; |
||||
|
||||
/*
|
||||
* Configure PCI Inbound Translation Windows |
||||
*/ |
||||
|
||||
/* we need RAM mapped to PCI space for the devices to
|
||||
* access main memory */ |
||||
pci_ctrl[1].pitar1 = 0x0; |
||||
pci_ctrl[1].pibar1 = 0x0; |
||||
pci_ctrl[1].piebar1 = 0x0; |
||||
pci_ctrl[1].piwar1 = |
||||
PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | |
||||
(__ilog2(gd->ram_size) - 1); |
||||
|
||||
hose->first_busno = pci_hose[0].last_busno + 1; |
||||
hose->last_busno = 0xff; |
||||
|
||||
/* PCI memory prefetch space */ |
||||
pci_set_region(hose->regions + 0, |
||||
CFG_PCI2_MEM_BASE, |
||||
CFG_PCI2_MEM_PHYS, |
||||
CFG_PCI2_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH); |
||||
|
||||
/* PCI memory space */ |
||||
pci_set_region(hose->regions + 1, |
||||
CFG_PCI2_MMIO_BASE, |
||||
CFG_PCI2_MMIO_PHYS, CFG_PCI2_MMIO_SIZE, PCI_REGION_MEM); |
||||
|
||||
/* PCI IO space */ |
||||
pci_set_region(hose->regions + 2, |
||||
CFG_PCI2_IO_BASE, |
||||
CFG_PCI2_IO_PHYS, CFG_PCI2_IO_SIZE, PCI_REGION_IO); |
||||
|
||||
/* System memory space */ |
||||
pci_set_region(hose->regions + 3, |
||||
CONFIG_PCI_SYS_MEM_BUS, |
||||
CONFIG_PCI_SYS_MEM_PHYS, |
||||
gd->ram_size, PCI_REGION_MEM | PCI_REGION_MEMORY); |
||||
|
||||
hose->region_count = 4; |
||||
|
||||
pci_setup_indirect(hose, |
||||
(CFG_IMMR + 0x8380), (CFG_IMMR + 0x8384)); |
||||
|
||||
pci_register_hose(hose); |
||||
|
||||
/*
|
||||
* Write to Command register |
||||
*/ |
||||
reg16 = 0xff; |
||||
dev = PCI_BDF(hose->first_busno, 0, 0); |
||||
pci_hose_read_config_word(hose, dev, PCI_COMMAND, ®16); |
||||
reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; |
||||
pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16); |
||||
|
||||
/*
|
||||
* Clear non-reserved bits in status register. |
||||
*/ |
||||
pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); |
||||
pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); |
||||
pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); |
||||
|
||||
/*
|
||||
* Hose scan. |
||||
*/ |
||||
hose->last_busno = pci_hose_scan(hose); |
||||
#endif |
||||
} |
||||
|
||||
#endif /* CONFIG_PCI */ |
||||
#ifdef CONFIG_OF_FLAT_TREE |
||||
void |
||||
ft_pci_setup(void *blob, bd_t *bd) |
||||
{ |
||||
u32 *p; |
||||
int len; |
||||
|
||||
p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len); |
||||
if (p != NULL) { |
||||
p[0] = pci_hose[0].first_busno; |
||||
p[1] = pci_hose[0].last_busno; |
||||
} |
||||
|
||||
#ifdef CONFIG_MPC83XX_PCI2 |
||||
p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8600/bus-range", &len); |
||||
if (p != NULL) { |
||||
p[0] = pci_hose[1].first_busno; |
||||
p[1] = pci_hose[1].last_busno; |
||||
} |
||||
#endif |
||||
} |
||||
#endif /* CONFIG_OF_FLAT_TREE */ |
||||
@ -0,0 +1,120 @@ |
||||
/* |
||||
* Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
SECTIONS |
||||
{ |
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
cpu/mpc83xx/start.o (.text) |
||||
*(.text) |
||||
*(.fixup) |
||||
*(.got1) |
||||
. = ALIGN(16); |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
*(.rodata.str1.4) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x0FFF) & 0xFFFFF000; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_) >> 2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
. = .; |
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
. = .; |
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(4096); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(4096); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
} |
||||
_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
||||
ENTRY(_start) |
||||
@ -0,0 +1,50 @@ |
||||
#
|
||||
# (C) Copyright 2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk |
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS := $(BOARD).o pci.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS) |
||||
$(AR) $(ARFLAGS) $@ $(OBJS)
|
||||
|
||||
clean: |
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
||||
distclean: clean |
||||
rm -f $(LIB) core *.bak .depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk |
||||
|
||||
sinclude $(obj).depend |
||||
|
||||
#########################################################################
|
||||
@ -0,0 +1,28 @@ |
||||
#
|
||||
# (C) Copyright 2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
#
|
||||
# MPC8360EMDS
|
||||
#
|
||||
|
||||
TEXT_BASE = 0xFE000000
|
||||
@ -0,0 +1,657 @@ |
||||
/*
|
||||
* Copyright (C) 2006 Freescale Semiconductor, Inc. |
||||
* |
||||
* Dave Liu <daveliu@freescale.com> |
||||
* based on board/mpc8349emds/mpc8349emds.c |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <ioports.h> |
||||
#include <mpc83xx.h> |
||||
#include <i2c.h> |
||||
#include <spd.h> |
||||
#include <miiphy.h> |
||||
#include <command.h> |
||||
#if defined(CONFIG_PCI) |
||||
#include <pci.h> |
||||
#endif |
||||
#if defined(CONFIG_SPD_EEPROM) |
||||
#include <spd_sdram.h> |
||||
#else |
||||
#include <asm/mmu.h> |
||||
#endif |
||||
#if defined(CONFIG_OF_FLAT_TREE) |
||||
#include <ft_build.h> |
||||
#endif |
||||
|
||||
const qe_iop_conf_t qe_iop_conf_tab[] = { |
||||
/* GETH1 */ |
||||
{0, 3, 1, 0, 1}, /* TxD0 */ |
||||
{0, 4, 1, 0, 1}, /* TxD1 */ |
||||
{0, 5, 1, 0, 1}, /* TxD2 */ |
||||
{0, 6, 1, 0, 1}, /* TxD3 */ |
||||
{1, 6, 1, 0, 3}, /* TxD4 */ |
||||
{1, 7, 1, 0, 1}, /* TxD5 */ |
||||
{1, 9, 1, 0, 2}, /* TxD6 */ |
||||
{1, 10, 1, 0, 2}, /* TxD7 */ |
||||
{0, 9, 2, 0, 1}, /* RxD0 */ |
||||
{0, 10, 2, 0, 1}, /* RxD1 */ |
||||
{0, 11, 2, 0, 1}, /* RxD2 */ |
||||
{0, 12, 2, 0, 1}, /* RxD3 */ |
||||
{0, 13, 2, 0, 1}, /* RxD4 */ |
||||
{1, 1, 2, 0, 2}, /* RxD5 */ |
||||
{1, 0, 2, 0, 2}, /* RxD6 */ |
||||
{1, 4, 2, 0, 2}, /* RxD7 */ |
||||
{0, 7, 1, 0, 1}, /* TX_EN */ |
||||
{0, 8, 1, 0, 1}, /* TX_ER */ |
||||
{0, 15, 2, 0, 1}, /* RX_DV */ |
||||
{0, 16, 2, 0, 1}, /* RX_ER */ |
||||
{0, 0, 2, 0, 1}, /* RX_CLK */ |
||||
{2, 9, 1, 0, 3}, /* GTX_CLK - CLK10 */ |
||||
{2, 8, 2, 0, 1}, /* GTX125 - CLK9 */ |
||||
/* GETH2 */ |
||||
{0, 17, 1, 0, 1}, /* TxD0 */ |
||||
{0, 18, 1, 0, 1}, /* TxD1 */ |
||||
{0, 19, 1, 0, 1}, /* TxD2 */ |
||||
{0, 20, 1, 0, 1}, /* TxD3 */ |
||||
{1, 2, 1, 0, 1}, /* TxD4 */ |
||||
{1, 3, 1, 0, 2}, /* TxD5 */ |
||||
{1, 5, 1, 0, 3}, /* TxD6 */ |
||||
{1, 8, 1, 0, 3}, /* TxD7 */ |
||||
{0, 23, 2, 0, 1}, /* RxD0 */ |
||||
{0, 24, 2, 0, 1}, /* RxD1 */ |
||||
{0, 25, 2, 0, 1}, /* RxD2 */ |
||||
{0, 26, 2, 0, 1}, /* RxD3 */ |
||||
{0, 27, 2, 0, 1}, /* RxD4 */ |
||||
{1, 12, 2, 0, 2}, /* RxD5 */ |
||||
{1, 13, 2, 0, 3}, /* RxD6 */ |
||||
{1, 11, 2, 0, 2}, /* RxD7 */ |
||||
{0, 21, 1, 0, 1}, /* TX_EN */ |
||||
{0, 22, 1, 0, 1}, /* TX_ER */ |
||||
{0, 29, 2, 0, 1}, /* RX_DV */ |
||||
{0, 30, 2, 0, 1}, /* RX_ER */ |
||||
{0, 31, 2, 0, 1}, /* RX_CLK */ |
||||
{2, 2, 1, 0, 2}, /* GTX_CLK = CLK10 */ |
||||
{2, 3, 2, 0, 1}, /* GTX125 - CLK4 */ |
||||
|
||||
{0, 1, 3, 0, 2}, /* MDIO */ |
||||
{0, 2, 1, 0, 1}, /* MDC */ |
||||
|
||||
{0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */ |
||||
}; |
||||
|
||||
int board_early_init_f(void) |
||||
{ |
||||
volatile u8 *bcsr = (volatile u8 *)CFG_BCSR; |
||||
|
||||
/* Enable flash write */ |
||||
bcsr[0xa] &= ~0x04; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) |
||||
extern void ddr_enable_ecc(unsigned int dram_size); |
||||
#endif |
||||
int fixed_sdram(void); |
||||
void sdram_init(void); |
||||
|
||||
long int initdram(int board_type) |
||||
{ |
||||
volatile immap_t *im = (immap_t *) CFG_IMMR; |
||||
u32 msize = 0; |
||||
|
||||
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) |
||||
return -1; |
||||
|
||||
/* DDR SDRAM - Main SODIMM */ |
||||
im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; |
||||
#if defined(CONFIG_SPD_EEPROM) |
||||
msize = spd_sdram(); |
||||
#else |
||||
msize = fixed_sdram(); |
||||
#endif |
||||
|
||||
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) |
||||
/*
|
||||
* Initialize DDR ECC byte |
||||
*/ |
||||
ddr_enable_ecc(msize * 1024 * 1024); |
||||
#endif |
||||
/*
|
||||
* Initialize SDRAM if it is on local bus. |
||||
*/ |
||||
sdram_init(); |
||||
puts(" DDR RAM: "); |
||||
/* return total bus SDRAM size(bytes) -- DDR */ |
||||
return (msize * 1024 * 1024); |
||||
} |
||||
|
||||
#if !defined(CONFIG_SPD_EEPROM) |
||||
/*************************************************************************
|
||||
* fixed sdram init -- doesn't use serial presence detect. |
||||
************************************************************************/ |
||||
int fixed_sdram(void) |
||||
{ |
||||
volatile immap_t *im = (immap_t *) CFG_IMMR; |
||||
u32 msize = 0; |
||||
u32 ddr_size; |
||||
u32 ddr_size_log2; |
||||
|
||||
msize = CFG_DDR_SIZE; |
||||
for (ddr_size = msize << 20, ddr_size_log2 = 0; |
||||
(ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) { |
||||
if (ddr_size & 1) { |
||||
return -1; |
||||
} |
||||
} |
||||
im->sysconf.ddrlaw[0].ar = |
||||
LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); |
||||
#if (CFG_DDR_SIZE != 256) |
||||
#warning Currenly any ddr size other than 256 is not supported |
||||
#endif |
||||
im->ddr.csbnds[0].csbnds = 0x00000007; |
||||
im->ddr.csbnds[1].csbnds = 0x0008000f; |
||||
|
||||
im->ddr.cs_config[0] = CFG_DDR_CONFIG; |
||||
im->ddr.cs_config[1] = CFG_DDR_CONFIG; |
||||
|
||||
im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; |
||||
im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; |
||||
im->ddr.sdram_cfg = CFG_DDR_CONTROL; |
||||
|
||||
im->ddr.sdram_mode = CFG_DDR_MODE; |
||||
im->ddr.sdram_interval = CFG_DDR_INTERVAL; |
||||
udelay(200); |
||||
im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; |
||||
|
||||
return msize; |
||||
} |
||||
#endif /*!CFG_SPD_EEPROM */ |
||||
|
||||
int checkboard(void) |
||||
{ |
||||
puts("Board: Freescale MPC8360EMDS\n"); |
||||
return 0; |
||||
} |
||||
|
||||
/*
|
||||
* if MPC8360EMDS is soldered with SDRAM |
||||
*/ |
||||
#if defined(CFG_BR2_PRELIM) \ |
||||
&& defined(CFG_OR2_PRELIM) \
|
||||
&& defined(CFG_LBLAWBAR2_PRELIM) \
|
||||
&& defined(CFG_LBLAWAR2_PRELIM) |
||||
/*
|
||||
* Initialize SDRAM memory on the Local Bus. |
||||
*/ |
||||
|
||||
void sdram_init(void) |
||||
{ |
||||
volatile immap_t *immap = (immap_t *) CFG_IMMR; |
||||
volatile lbus83xx_t *lbc = &immap->lbus; |
||||
uint *sdram_addr = (uint *) CFG_LBC_SDRAM_BASE; |
||||
|
||||
puts("\n SDRAM on Local Bus: "); |
||||
print_size(CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); |
||||
/*
|
||||
* Setup SDRAM Base and Option Registers, already done in cpu_init.c |
||||
*/ |
||||
/*setup mtrpt, lsrt and lbcr for LB bus */ |
||||
lbc->lbcr = CFG_LBC_LBCR; |
||||
lbc->mrtpr = CFG_LBC_MRTPR; |
||||
lbc->lsrt = CFG_LBC_LSRT; |
||||
asm("sync"); |
||||
|
||||
/*
|
||||
* Configure the SDRAM controller Machine Mode Register. |
||||
*/ |
||||
lbc->lsdmr = CFG_LBC_LSDMR_5; /* Normal Operation */ |
||||
lbc->lsdmr = CFG_LBC_LSDMR_1; /* Precharge All Banks */ |
||||
asm("sync"); |
||||
*sdram_addr = 0xff; |
||||
udelay(100); |
||||
|
||||
/*
|
||||
* We need do 8 times auto refresh operation. |
||||
*/ |
||||
lbc->lsdmr = CFG_LBC_LSDMR_2; |
||||
asm("sync"); |
||||
*sdram_addr = 0xff; /* 1 times */ |
||||
udelay(100); |
||||
*sdram_addr = 0xff; /* 2 times */ |
||||
udelay(100); |
||||
*sdram_addr = 0xff; /* 3 times */ |
||||
udelay(100); |
||||
*sdram_addr = 0xff; /* 4 times */ |
||||
udelay(100); |
||||
*sdram_addr = 0xff; /* 5 times */ |
||||
udelay(100); |
||||
*sdram_addr = 0xff; /* 6 times */ |
||||
udelay(100); |
||||
*sdram_addr = 0xff; /* 7 times */ |
||||
udelay(100); |
||||
*sdram_addr = 0xff; /* 8 times */ |
||||
udelay(100); |
||||
|
||||
/* Mode register write operation */ |
||||
lbc->lsdmr = CFG_LBC_LSDMR_4; |
||||
asm("sync"); |
||||
*(sdram_addr + 0xcc) = 0xff; |
||||
udelay(100); |
||||
|
||||
/* Normal operation */ |
||||
lbc->lsdmr = CFG_LBC_LSDMR_5 | 0x40000000; |
||||
asm("sync"); |
||||
*sdram_addr = 0xff; |
||||
udelay(100); |
||||
} |
||||
#else |
||||
void sdram_init(void) |
||||
{ |
||||
puts("SDRAM on Local Bus is NOT available!\n"); |
||||
} |
||||
#endif |
||||
|
||||
#if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) |
||||
/*
|
||||
* ECC user commands |
||||
*/ |
||||
void ecc_print_status(void) |
||||
{ |
||||
volatile immap_t *immap = (immap_t *) CFG_IMMR; |
||||
volatile ddr83xx_t *ddr = &immap->ddr; |
||||
|
||||
printf("\nECC mode: %s\n\n", |
||||
(ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ? "ON" : "OFF"); |
||||
|
||||
/* Interrupts */ |
||||
printf("Memory Error Interrupt Enable:\n"); |
||||
printf(" Multiple-Bit Error Interrupt Enable: %d\n", |
||||
(ddr->err_int_en & ECC_ERR_INT_EN_MBEE) ? 1 : 0); |
||||
printf(" Single-Bit Error Interrupt Enable: %d\n", |
||||
(ddr->err_int_en & ECC_ERR_INT_EN_SBEE) ? 1 : 0); |
||||
printf(" Memory Select Error Interrupt Enable: %d\n\n", |
||||
(ddr->err_int_en & ECC_ERR_INT_EN_MSEE) ? 1 : 0); |
||||
|
||||
/* Error disable */ |
||||
printf("Memory Error Disable:\n"); |
||||
printf(" Multiple-Bit Error Disable: %d\n", |
||||
(ddr->err_disable & ECC_ERROR_DISABLE_MBED) ? 1 : 0); |
||||
printf(" Sinle-Bit Error Disable: %d\n", |
||||
(ddr->err_disable & ECC_ERROR_DISABLE_SBED) ? 1 : 0); |
||||
printf(" Memory Select Error Disable: %d\n\n", |
||||
(ddr->err_disable & ECC_ERROR_DISABLE_MSED) ? 1 : 0); |
||||
|
||||
/* Error injection */ |
||||
printf("Memory Data Path Error Injection Mask High/Low: %08lx %08lx\n", |
||||
ddr->data_err_inject_hi, ddr->data_err_inject_lo); |
||||
|
||||
printf("Memory Data Path Error Injection Mask ECC:\n"); |
||||
printf(" ECC Mirror Byte: %d\n", |
||||
(ddr->ecc_err_inject & ECC_ERR_INJECT_EMB) ? 1 : 0); |
||||
printf(" ECC Injection Enable: %d\n", |
||||
(ddr->ecc_err_inject & ECC_ERR_INJECT_EIEN) ? 1 : 0); |
||||
printf(" ECC Error Injection Mask: 0x%02x\n\n", |
||||
ddr->ecc_err_inject & ECC_ERR_INJECT_EEIM); |
||||
|
||||
/* SBE counter/threshold */ |
||||
printf("Memory Single-Bit Error Management (0..255):\n"); |
||||
printf(" Single-Bit Error Threshold: %d\n", |
||||
(ddr->err_sbe & ECC_ERROR_MAN_SBET) >> ECC_ERROR_MAN_SBET_SHIFT); |
||||
printf(" Single-Bit Error Counter: %d\n\n", |
||||
(ddr->err_sbe & ECC_ERROR_MAN_SBEC) >> ECC_ERROR_MAN_SBEC_SHIFT); |
||||
|
||||
/* Error detect */ |
||||
printf("Memory Error Detect:\n"); |
||||
printf(" Multiple Memory Errors: %d\n", |
||||
(ddr->err_detect & ECC_ERROR_DETECT_MME) ? 1 : 0); |
||||
printf(" Multiple-Bit Error: %d\n", |
||||
(ddr->err_detect & ECC_ERROR_DETECT_MBE) ? 1 : 0); |
||||
printf(" Single-Bit Error: %d\n", |
||||
(ddr->err_detect & ECC_ERROR_DETECT_SBE) ? 1 : 0); |
||||
printf(" Memory Select Error: %d\n\n", |
||||
(ddr->err_detect & ECC_ERROR_DETECT_MSE) ? 1 : 0); |
||||
|
||||
/* Capture data */ |
||||
printf("Memory Error Address Capture: 0x%08lx\n", ddr->capture_address); |
||||
printf("Memory Data Path Read Capture High/Low: %08lx %08lx\n", |
||||
ddr->capture_data_hi, ddr->capture_data_lo); |
||||
printf("Memory Data Path Read Capture ECC: 0x%02x\n\n", |
||||
ddr->capture_ecc & CAPTURE_ECC_ECE); |
||||
|
||||
printf("Memory Error Attributes Capture:\n"); |
||||
printf(" Data Beat Number: %d\n", |
||||
(ddr->capture_attributes & ECC_CAPT_ATTR_BNUM) >> |
||||
ECC_CAPT_ATTR_BNUM_SHIFT); |
||||
printf(" Transaction Size: %d\n", |
||||
(ddr->capture_attributes & ECC_CAPT_ATTR_TSIZ) >> |
||||
ECC_CAPT_ATTR_TSIZ_SHIFT); |
||||
printf(" Transaction Source: %d\n", |
||||
(ddr->capture_attributes & ECC_CAPT_ATTR_TSRC) >> |
||||
ECC_CAPT_ATTR_TSRC_SHIFT); |
||||
printf(" Transaction Type: %d\n", |
||||
(ddr->capture_attributes & ECC_CAPT_ATTR_TTYP) >> |
||||
ECC_CAPT_ATTR_TTYP_SHIFT); |
||||
printf(" Error Information Valid: %d\n\n", |
||||
ddr->capture_attributes & ECC_CAPT_ATTR_VLD); |
||||
} |
||||
|
||||
int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) |
||||
{ |
||||
volatile immap_t *immap = (immap_t *) CFG_IMMR; |
||||
volatile ddr83xx_t *ddr = &immap->ddr; |
||||
volatile u32 val; |
||||
u64 *addr; |
||||
u32 count; |
||||
register u64 *i; |
||||
u32 ret[2]; |
||||
u32 pattern[2]; |
||||
u32 writeback[2]; |
||||
|
||||
/* The pattern is written into memory to generate error */ |
||||
pattern[0] = 0xfedcba98UL; |
||||
pattern[1] = 0x76543210UL; |
||||
|
||||
/* After injecting error, re-initialize the memory with the value */ |
||||
writeback[0] = 0x01234567UL; |
||||
writeback[1] = 0x89abcdefUL; |
||||
|
||||
if (argc > 4) { |
||||
printf("Usage:\n%s\n", cmdtp->usage); |
||||
return 1; |
||||
} |
||||
|
||||
if (argc == 2) { |
||||
if (strcmp(argv[1], "status") == 0) { |
||||
ecc_print_status(); |
||||
return 0; |
||||
} else if (strcmp(argv[1], "captureclear") == 0) { |
||||
ddr->capture_address = 0; |
||||
ddr->capture_data_hi = 0; |
||||
ddr->capture_data_lo = 0; |
||||
ddr->capture_ecc = 0; |
||||
ddr->capture_attributes = 0; |
||||
return 0; |
||||
} |
||||
} |
||||
if (argc == 3) { |
||||
if (strcmp(argv[1], "sbecnt") == 0) { |
||||
val = simple_strtoul(argv[2], NULL, 10); |
||||
if (val > 255) { |
||||
printf("Incorrect Counter value, " |
||||
"should be 0..255\n"); |
||||
return 1; |
||||
} |
||||
|
||||
val = (val << ECC_ERROR_MAN_SBEC_SHIFT); |
||||
val |= (ddr->err_sbe & ECC_ERROR_MAN_SBET); |
||||
|
||||
ddr->err_sbe = val; |
||||
return 0; |
||||
} else if (strcmp(argv[1], "sbethr") == 0) { |
||||
val = simple_strtoul(argv[2], NULL, 10); |
||||
if (val > 255) { |
||||
printf("Incorrect Counter value, " |
||||
"should be 0..255\n"); |
||||
return 1; |
||||
} |
||||
|
||||
val = (val << ECC_ERROR_MAN_SBET_SHIFT); |
||||
val |= (ddr->err_sbe & ECC_ERROR_MAN_SBEC); |
||||
|
||||
ddr->err_sbe = val; |
||||
return 0; |
||||
} else if (strcmp(argv[1], "errdisable") == 0) { |
||||
val = ddr->err_disable; |
||||
|
||||
if (strcmp(argv[2], "+sbe") == 0) { |
||||
val |= ECC_ERROR_DISABLE_SBED; |
||||
} else if (strcmp(argv[2], "+mbe") == 0) { |
||||
val |= ECC_ERROR_DISABLE_MBED; |
||||
} else if (strcmp(argv[2], "+mse") == 0) { |
||||
val |= ECC_ERROR_DISABLE_MSED; |
||||
} else if (strcmp(argv[2], "+all") == 0) { |
||||
val |= (ECC_ERROR_DISABLE_SBED | |
||||
ECC_ERROR_DISABLE_MBED | |
||||
ECC_ERROR_DISABLE_MSED); |
||||
} else if (strcmp(argv[2], "-sbe") == 0) { |
||||
val &= ~ECC_ERROR_DISABLE_SBED; |
||||
} else if (strcmp(argv[2], "-mbe") == 0) { |
||||
val &= ~ECC_ERROR_DISABLE_MBED; |
||||
} else if (strcmp(argv[2], "-mse") == 0) { |
||||
val &= ~ECC_ERROR_DISABLE_MSED; |
||||
} else if (strcmp(argv[2], "-all") == 0) { |
||||
val &= ~(ECC_ERROR_DISABLE_SBED | |
||||
ECC_ERROR_DISABLE_MBED | |
||||
ECC_ERROR_DISABLE_MSED); |
||||
} else { |
||||
printf("Incorrect err_disable field\n"); |
||||
return 1; |
||||
} |
||||
|
||||
ddr->err_disable = val; |
||||
__asm__ __volatile__("sync"); |
||||
__asm__ __volatile__("isync"); |
||||
return 0; |
||||
} else if (strcmp(argv[1], "errdetectclr") == 0) { |
||||
val = ddr->err_detect; |
||||
|
||||
if (strcmp(argv[2], "mme") == 0) { |
||||
val |= ECC_ERROR_DETECT_MME; |
||||
} else if (strcmp(argv[2], "sbe") == 0) { |
||||
val |= ECC_ERROR_DETECT_SBE; |
||||
} else if (strcmp(argv[2], "mbe") == 0) { |
||||
val |= ECC_ERROR_DETECT_MBE; |
||||
} else if (strcmp(argv[2], "mse") == 0) { |
||||
val |= ECC_ERROR_DETECT_MSE; |
||||
} else if (strcmp(argv[2], "all") == 0) { |
||||
val |= (ECC_ERROR_DETECT_MME | |
||||
ECC_ERROR_DETECT_MBE | |
||||
ECC_ERROR_DETECT_SBE | |
||||
ECC_ERROR_DETECT_MSE); |
||||
} else { |
||||
printf("Incorrect err_detect field\n"); |
||||
return 1; |
||||
} |
||||
|
||||
ddr->err_detect = val; |
||||
return 0; |
||||
} else if (strcmp(argv[1], "injectdatahi") == 0) { |
||||
val = simple_strtoul(argv[2], NULL, 16); |
||||
|
||||
ddr->data_err_inject_hi = val; |
||||
return 0; |
||||
} else if (strcmp(argv[1], "injectdatalo") == 0) { |
||||
val = simple_strtoul(argv[2], NULL, 16); |
||||
|
||||
ddr->data_err_inject_lo = val; |
||||
return 0; |
||||
} else if (strcmp(argv[1], "injectecc") == 0) { |
||||
val = simple_strtoul(argv[2], NULL, 16); |
||||
if (val > 0xff) { |
||||
printf("Incorrect ECC inject mask, " |
||||
"should be 0x00..0xff\n"); |
||||
return 1; |
||||
} |
||||
val |= (ddr->ecc_err_inject & ~ECC_ERR_INJECT_EEIM); |
||||
|
||||
ddr->ecc_err_inject = val; |
||||
return 0; |
||||
} else if (strcmp(argv[1], "inject") == 0) { |
||||
val = ddr->ecc_err_inject; |
||||
|
||||
if (strcmp(argv[2], "en") == 0) |
||||
val |= ECC_ERR_INJECT_EIEN; |
||||
else if (strcmp(argv[2], "dis") == 0) |
||||
val &= ~ECC_ERR_INJECT_EIEN; |
||||
else |
||||
printf("Incorrect command\n"); |
||||
|
||||
ddr->ecc_err_inject = val; |
||||
__asm__ __volatile__("sync"); |
||||
__asm__ __volatile__("isync"); |
||||
return 0; |
||||
} else if (strcmp(argv[1], "mirror") == 0) { |
||||
val = ddr->ecc_err_inject; |
||||
|
||||
if (strcmp(argv[2], "en") == 0) |
||||
val |= ECC_ERR_INJECT_EMB; |
||||
else if (strcmp(argv[2], "dis") == 0) |
||||
val &= ~ECC_ERR_INJECT_EMB; |
||||
else |
||||
printf("Incorrect command\n"); |
||||
|
||||
ddr->ecc_err_inject = val; |
||||
return 0; |
||||
} |
||||
} |
||||
if (argc == 4) { |
||||
if (strcmp(argv[1], "testdw") == 0) { |
||||
addr = (u64 *) simple_strtoul(argv[2], NULL, 16); |
||||
count = simple_strtoul(argv[3], NULL, 16); |
||||
|
||||
if ((u32) addr % 8) { |
||||
printf("Address not alligned on " |
||||
"double word boundary\n"); |
||||
return 1; |
||||
} |
||||
disable_interrupts(); |
||||
|
||||
for (i = addr; i < addr + count; i++) { |
||||
|
||||
/* enable injects */ |
||||
ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN; |
||||
__asm__ __volatile__("sync"); |
||||
__asm__ __volatile__("isync"); |
||||
|
||||
/* write memory location injecting errors */ |
||||
ppcDWstore((u32 *) i, pattern); |
||||
__asm__ __volatile__("sync"); |
||||
|
||||
/* disable injects */ |
||||
ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN; |
||||
__asm__ __volatile__("sync"); |
||||
__asm__ __volatile__("isync"); |
||||
|
||||
/* read data, this generates ECC error */ |
||||
ppcDWload((u32 *) i, ret); |
||||
__asm__ __volatile__("sync"); |
||||
|
||||
/* re-initialize memory, double word write the location again,
|
||||
* generates new ECC code this time */ |
||||
ppcDWstore((u32 *) i, writeback); |
||||
__asm__ __volatile__("sync"); |
||||
} |
||||
enable_interrupts(); |
||||
return 0; |
||||
} |
||||
if (strcmp(argv[1], "testword") == 0) { |
||||
addr = (u64 *) simple_strtoul(argv[2], NULL, 16); |
||||
count = simple_strtoul(argv[3], NULL, 16); |
||||
|
||||
if ((u32) addr % 8) { |
||||
printf("Address not alligned on " |
||||
"double word boundary\n"); |
||||
return 1; |
||||
} |
||||
disable_interrupts(); |
||||
|
||||
for (i = addr; i < addr + count; i++) { |
||||
|
||||
/* enable injects */ |
||||
ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN; |
||||
__asm__ __volatile__("sync"); |
||||
__asm__ __volatile__("isync"); |
||||
|
||||
/* write memory location injecting errors */ |
||||
*(u32 *) i = 0xfedcba98UL; |
||||
__asm__ __volatile__("sync"); |
||||
|
||||
/* sub double word write,
|
||||
* bus will read-modify-write, |
||||
* generates ECC error */ |
||||
*((u32 *) i + 1) = 0x76543210UL; |
||||
__asm__ __volatile__("sync"); |
||||
|
||||
/* disable injects */ |
||||
ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN; |
||||
__asm__ __volatile__("sync"); |
||||
__asm__ __volatile__("isync"); |
||||
|
||||
/* re-initialize memory,
|
||||
* double word write the location again, |
||||
* generates new ECC code this time */ |
||||
ppcDWstore((u32 *) i, writeback); |
||||
__asm__ __volatile__("sync"); |
||||
} |
||||
enable_interrupts(); |
||||
return 0; |
||||
} |
||||
} |
||||
printf("Usage:\n%s\n", cmdtp->usage); |
||||
return 1; |
||||
} |
||||
|
||||
U_BOOT_CMD(ecc, 4, 0, do_ecc, |
||||
"ecc - support for DDR ECC features\n", |
||||
"status - print out status info\n" |
||||
"ecc captureclear - clear capture regs data\n" |
||||
"ecc sbecnt <val> - set Single-Bit Error counter\n" |
||||
"ecc sbethr <val> - set Single-Bit Threshold\n" |
||||
"ecc errdisable <flag> - clear/set disable Memory Error Disable, flag:\n" |
||||
" [-|+]sbe - Single-Bit Error\n" |
||||
" [-|+]mbe - Multiple-Bit Error\n" |
||||
" [-|+]mse - Memory Select Error\n" |
||||
" [-|+]all - all errors\n" |
||||
"ecc errdetectclr <flag> - clear Memory Error Detect, flag:\n" |
||||
" mme - Multiple Memory Errors\n" |
||||
" sbe - Single-Bit Error\n" |
||||
" mbe - Multiple-Bit Error\n" |
||||
" mse - Memory Select Error\n" |
||||
" all - all errors\n" |
||||
"ecc injectdatahi <hi> - set Memory Data Path Error Injection Mask High\n" |
||||
"ecc injectdatalo <lo> - set Memory Data Path Error Injection Mask Low\n" |
||||
"ecc injectecc <ecc> - set ECC Error Injection Mask\n" |
||||
"ecc inject <en|dis> - enable/disable error injection\n" |
||||
"ecc mirror <en|dis> - enable/disable mirror byte\n" |
||||
"ecc testdw <addr> <cnt> - test mem region with double word access:\n" |
||||
" - enables injects\n" |
||||
" - writes pattern injecting errors with double word access\n" |
||||
" - disables injects\n" |
||||
" - reads pattern back with double word access, generates error\n" |
||||
" - re-inits memory\n" |
||||
"ecc testword <addr> <cnt> - test mem region with word access:\n" |
||||
" - enables injects\n" |
||||
" - writes pattern injecting errors with word access\n" |
||||
" - writes pattern with word access, generates error\n" |
||||
" - disables injects\n" " - re-inits memory"); |
||||
#endif /* if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) */ |
||||
|
||||
#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) |
||||
void |
||||
ft_board_setup(void *blob, bd_t *bd) |
||||
{ |
||||
u32 *p; |
||||
int len; |
||||
|
||||
#ifdef CONFIG_PCI |
||||
ft_pci_setup(blob, bd); |
||||
#endif |
||||
ft_cpu_setup(blob, bd); |
||||
|
||||
p = ft_get_prop(blob, "/memory/reg", &len); |
||||
if (p != NULL) { |
||||
*p++ = cpu_to_be32(bd->bi_memstart); |
||||
*p = cpu_to_be32(bd->bi_memsize); |
||||
} |
||||
} |
||||
#endif |
||||
@ -0,0 +1,313 @@ |
||||
/*
|
||||
* Copyright (C) 2006 Freescale Semiconductor, Inc. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
*/ |
||||
|
||||
/*
|
||||
* PCI Configuration space access support for MPC83xx PCI Bridge |
||||
*/ |
||||
#include <asm/mmu.h> |
||||
#include <asm/io.h> |
||||
#include <common.h> |
||||
#include <pci.h> |
||||
#include <i2c.h> |
||||
|
||||
#include <asm/fsl_i2c.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
#if defined(CONFIG_PCI) |
||||
#define PCI_FUNCTION_CONFIG 0x44 |
||||
#define PCI_FUNCTION_CFG_LOCK 0x20 |
||||
|
||||
/*
|
||||
* Initialize PCI Devices, report devices found |
||||
*/ |
||||
#ifndef CONFIG_PCI_PNP |
||||
static struct pci_config_table pci_mpc83xxemds_config_table[] = { |
||||
{ |
||||
PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, |
||||
pci_cfgfunc_config_device, |
||||
{PCI_ENET0_IOADDR, |
||||
PCI_ENET0_MEMADDR, |
||||
PCI_COMMON_MEMORY | PCI_COMMAND_MASTER} |
||||
}, |
||||
{} |
||||
} |
||||
#endif |
||||
static struct pci_controller hose[] = { |
||||
{ |
||||
#ifndef CONFIG_PCI_PNP |
||||
config_table:pci_mpc83xxemds_config_table, |
||||
#endif |
||||
}, |
||||
}; |
||||
|
||||
/**********************************************************************
|
||||
* pci_init_board() |
||||
*********************************************************************/ |
||||
void pci_init_board(void) |
||||
#ifdef CONFIG_PCISLAVE |
||||
{ |
||||
u16 reg16; |
||||
volatile immap_t *immr; |
||||
volatile law83xx_t *pci_law; |
||||
volatile pot83xx_t *pci_pot; |
||||
volatile pcictrl83xx_t *pci_ctrl; |
||||
volatile pciconf83xx_t *pci_conf; |
||||
|
||||
immr = (immap_t *) CFG_IMMR; |
||||
pci_law = immr->sysconf.pcilaw; |
||||
pci_pot = immr->ios.pot; |
||||
pci_ctrl = immr->pci_ctrl; |
||||
pci_conf = immr->pci_conf; |
||||
/*
|
||||
* Configure PCI Inbound Translation Windows |
||||
*/ |
||||
pci_ctrl[0].pitar0 = 0x0; |
||||
pci_ctrl[0].pibar0 = 0x0; |
||||
pci_ctrl[0].piwar0 = PIWAR_EN | PIWAR_RTT_SNOOP | |
||||
PIWAR_WTT_SNOOP | PIWAR_IWS_4K; |
||||
|
||||
pci_ctrl[0].pitar1 = 0x0; |
||||
pci_ctrl[0].pibar1 = 0x0; |
||||
pci_ctrl[0].piebar1 = 0x0; |
||||
pci_ctrl[0].piwar1 &= ~PIWAR_EN; |
||||
|
||||
pci_ctrl[0].pitar2 = 0x0; |
||||
pci_ctrl[0].pibar2 = 0x0; |
||||
pci_ctrl[0].piebar2 = 0x0; |
||||
pci_ctrl[0].piwar2 &= ~PIWAR_EN; |
||||
|
||||
hose[0].first_busno = 0; |
||||
hose[0].last_busno = 0xff; |
||||
pci_setup_indirect(&hose[0], |
||||
(CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304)); |
||||
reg16 = 0xff; |
||||
|
||||
pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0), |
||||
PCI_COMMAND, ®16); |
||||
reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MEMORY; |
||||
pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0), |
||||
PCI_COMMAND, reg16); |
||||
|
||||
/*
|
||||
* Clear non-reserved bits in status register. |
||||
*/ |
||||
pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0), |
||||
PCI_STATUS, 0xffff); |
||||
pci_hose_write_config_byte(&hose[0], PCI_BDF(0, 0, 0), |
||||
PCI_LATENCY_TIMER, 0x80); |
||||
|
||||
/*
|
||||
* Unlock configuration lock in PCI function configuration register. |
||||
*/ |
||||
pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0), |
||||
PCI_FUNCTION_CONFIG, ®16); |
||||
reg16 &= ~(PCI_FUNCTION_CFG_LOCK); |
||||
pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0), |
||||
PCI_FUNCTION_CONFIG, reg16); |
||||
|
||||
printf("Enabled PCI 32bit Agent Mode\n"); |
||||
} |
||||
#else |
||||
{ |
||||
volatile immap_t *immr; |
||||
volatile clk83xx_t *clk; |
||||
volatile law83xx_t *pci_law; |
||||
volatile pot83xx_t *pci_pot; |
||||
volatile pcictrl83xx_t *pci_ctrl; |
||||
volatile pciconf83xx_t *pci_conf; |
||||
|
||||
u8 val8, orig_i2c_bus; |
||||
u16 reg16; |
||||
u32 val32; |
||||
u32 dev; |
||||
|
||||
immr = (immap_t *) CFG_IMMR; |
||||
clk = (clk83xx_t *) & immr->clk; |
||||
pci_law = immr->sysconf.pcilaw; |
||||
pci_pot = immr->ios.pot; |
||||
pci_ctrl = immr->pci_ctrl; |
||||
pci_conf = immr->pci_conf; |
||||
/*
|
||||
* Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode |
||||
*/ |
||||
val32 = clk->occr; |
||||
udelay(2000); |
||||
#if defined(PCI_66M) |
||||
clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2; |
||||
printf("PCI clock is 66MHz\n"); |
||||
#elif defined(PCI_33M) |
||||
clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 | |
||||
OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR; |
||||
printf("PCI clock is 33MHz\n"); |
||||
#else |
||||
clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2; |
||||
printf("PCI clock is 66MHz\n"); |
||||
#endif |
||||
udelay(2000); |
||||
|
||||
/*
|
||||
* Configure PCI Local Access Windows |
||||
*/ |
||||
pci_law[0].bar = CFG_PCI_MEM_PHYS & LAWBAR_BAR; |
||||
pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M; |
||||
|
||||
pci_law[1].bar = CFG_PCI_IO_PHYS & LAWBAR_BAR; |
||||
pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M; |
||||
|
||||
/*
|
||||
* Configure PCI Outbound Translation Windows |
||||
*/ |
||||
|
||||
/* PCI mem space - prefetch */ |
||||
pci_pot[0].potar = (CFG_PCI_MEM_BASE >> 12) & POTAR_TA_MASK; |
||||
pci_pot[0].pobar = (CFG_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK; |
||||
pci_pot[0].pocmr = |
||||
POCMR_EN | POCMR_SE | (POCMR_CM_256M & POCMR_CM_MASK); |
||||
|
||||
/* PCI mmio - non-prefetch mem space */ |
||||
pci_pot[1].potar = (CFG_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK; |
||||
pci_pot[1].pobar = (CFG_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK; |
||||
pci_pot[1].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK); |
||||
|
||||
/* PCI IO space */ |
||||
pci_pot[2].potar = (CFG_PCI_IO_BASE >> 12) & POTAR_TA_MASK; |
||||
pci_pot[2].pobar = (CFG_PCI_IO_PHYS >> 12) & POBAR_BA_MASK; |
||||
pci_pot[2].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK); |
||||
|
||||
/*
|
||||
* Configure PCI Inbound Translation Windows |
||||
*/ |
||||
pci_ctrl[0].pitar1 = (CFG_PCI_SLV_MEM_LOCAL >> 12) & PITAR_TA_MASK; |
||||
pci_ctrl[0].pibar1 = (CFG_PCI_SLV_MEM_BUS >> 12) & PIBAR_MASK; |
||||
pci_ctrl[0].piebar1 = 0x0; |
||||
pci_ctrl[0].piwar1 = |
||||
PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | |
||||
PIWAR_IWS_2G; |
||||
|
||||
/*
|
||||
* Assign PIB PMC slot to desired PCI bus |
||||
*/ |
||||
|
||||
/* Switch temporarily to I2C bus #2 */ |
||||
orig_i2c_bus = i2c_get_bus_num(); |
||||
i2c_set_bus_num(1); |
||||
|
||||
val8 = 0; |
||||
i2c_write(0x23, 0x6, 1, &val8, 1); |
||||
i2c_write(0x23, 0x7, 1, &val8, 1); |
||||
val8 = 0xff; |
||||
i2c_write(0x23, 0x2, 1, &val8, 1); |
||||
i2c_write(0x23, 0x3, 1, &val8, 1); |
||||
|
||||
val8 = 0; |
||||
i2c_write(0x26, 0x6, 1, &val8, 1); |
||||
val8 = 0x34; |
||||
i2c_write(0x26, 0x7, 1, &val8, 1); |
||||
|
||||
val8 = 0xf3; /*PMC1, PMC2, PMC3 slot to PCI bus */ |
||||
i2c_write(0x26, 0x2, 1, &val8, 1); |
||||
val8 = 0xff; |
||||
i2c_write(0x26, 0x3, 1, &val8, 1); |
||||
|
||||
val8 = 0; |
||||
i2c_write(0x27, 0x6, 1, &val8, 1); |
||||
i2c_write(0x27, 0x7, 1, &val8, 1); |
||||
val8 = 0xff; |
||||
i2c_write(0x27, 0x2, 1, &val8, 1); |
||||
val8 = 0xef; |
||||
i2c_write(0x27, 0x3, 1, &val8, 1); |
||||
asm("eieio"); |
||||
|
||||
/* Reset to original I2C bus */ |
||||
i2c_set_bus_num(orig_i2c_bus); |
||||
|
||||
/*
|
||||
* Release PCI RST Output signal |
||||
*/ |
||||
udelay(2000); |
||||
pci_ctrl[0].gcr = 1; |
||||
udelay(2000); |
||||
|
||||
hose[0].first_busno = 0; |
||||
hose[0].last_busno = 0xff; |
||||
|
||||
/* PCI memory prefetch space */ |
||||
pci_set_region(hose[0].regions + 0, |
||||
CFG_PCI_MEM_BASE, |
||||
CFG_PCI_MEM_PHYS, |
||||
CFG_PCI_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH); |
||||
|
||||
/* PCI memory space */ |
||||
pci_set_region(hose[0].regions + 1, |
||||
CFG_PCI_MMIO_BASE, |
||||
CFG_PCI_MMIO_PHYS, CFG_PCI_MMIO_SIZE, PCI_REGION_MEM); |
||||
|
||||
/* PCI IO space */ |
||||
pci_set_region(hose[0].regions + 2, |
||||
CFG_PCI_IO_BASE, |
||||
CFG_PCI_IO_PHYS, CFG_PCI_IO_SIZE, PCI_REGION_IO); |
||||
|
||||
/* System memory space */ |
||||
pci_set_region(hose[0].regions + 3, |
||||
CFG_PCI_SLV_MEM_LOCAL, |
||||
CFG_PCI_SLV_MEM_BUS, |
||||
CFG_PCI_SLV_MEM_SIZE, |
||||
PCI_REGION_MEM | PCI_REGION_MEMORY); |
||||
|
||||
hose[0].region_count = 4; |
||||
|
||||
pci_setup_indirect(&hose[0], |
||||
(CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304)); |
||||
|
||||
pci_register_hose(hose); |
||||
|
||||
/*
|
||||
* Write command register |
||||
*/ |
||||
reg16 = 0xff; |
||||
dev = PCI_BDF(0, 0, 0); |
||||
pci_hose_read_config_word(&hose[0], dev, PCI_COMMAND, ®16); |
||||
reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; |
||||
pci_hose_write_config_word(&hose[0], dev, PCI_COMMAND, reg16); |
||||
|
||||
/*
|
||||
* Clear non-reserved bits in status register. |
||||
*/ |
||||
pci_hose_write_config_word(&hose[0], dev, PCI_STATUS, 0xffff); |
||||
pci_hose_write_config_byte(&hose[0], dev, PCI_LATENCY_TIMER, 0x80); |
||||
pci_hose_write_config_byte(&hose[0], dev, PCI_CACHE_LINE_SIZE, 0x08); |
||||
|
||||
printf("PCI 32bit bus on PMC1 & PMC2 & PMC3\n"); |
||||
|
||||
/*
|
||||
* Hose scan. |
||||
*/ |
||||
hose->last_busno = pci_hose_scan(hose); |
||||
} |
||||
#endif /* CONFIG_PCISLAVE */ |
||||
|
||||
#ifdef CONFIG_OF_FLAT_TREE |
||||
void |
||||
ft_pci_setup(void *blob, bd_t *bd) |
||||
{ |
||||
u32 *p; |
||||
int len; |
||||
|
||||
p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len); |
||||
if (p != NULL) { |
||||
p[0] = hose[0].first_busno; |
||||
p[1] = hose[0].last_busno; |
||||
} |
||||
} |
||||
#endif /* CONFIG_OF_FLAT_TREE */ |
||||
#endif /* CONFIG_PCI */ |
||||
@ -0,0 +1,123 @@ |
||||
/* |
||||
* (C) Copyright 2006 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
SECTIONS |
||||
{ |
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
cpu/mpc83xx/start.o (.text) |
||||
*(.text) |
||||
*(.fixup) |
||||
*(.got1) |
||||
. = ALIGN(16); |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
*(.rodata.str1.4) |
||||
*(.eh_frame) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x0FFF) & 0xFFFFF000; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_) >> 2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
. = .; |
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
|
||||
. = .; |
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(4096); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(4096); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
} |
||||
_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
||||
ENTRY(_start) |
||||
@ -1,253 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2003,Motorola Inc. |
||||
* Xianghua Xiao <x.xiao@motorola.com> |
||||
* Adapted for Motorola 85xx chip. |
||||
* |
||||
* (C) Copyright 2003 |
||||
* Gleb Natapov <gnatapov@mrv.com> |
||||
* Some bits are taken from linux driver writen by adrian@humboldt.co.uk |
||||
* |
||||
* Hardware I2C driver for MPC107 PCI bridge. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
* |
||||
* Change log: |
||||
* |
||||
* 20050101: Eran Liberty (liberty@freescale.com) |
||||
* Initial file creating (porting from 85XX & 8260) |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <command.h> |
||||
#include <asm/io.h> |
||||
|
||||
#ifdef CONFIG_HARD_I2C |
||||
#include <i2c.h> |
||||
#include <asm/i2c.h> |
||||
|
||||
#if defined(CONFIG_MPC8349EMDS) || defined(CONFIG_TQM834X) |
||||
i2c_t * mpc8349_i2c = (i2c_t*)(CFG_IMMRBAR + CFG_I2C_OFFSET); |
||||
#endif |
||||
|
||||
void |
||||
i2c_init(int speed, int slaveadd) |
||||
{ |
||||
/* stop I2C controller */ |
||||
writeb(0x00 , &I2C->cr); |
||||
|
||||
/* set clock */ |
||||
writeb(0x3f, &I2C->fdr); |
||||
|
||||
/* set default filter */ |
||||
writeb(0x10,&I2C->dfsrr); |
||||
|
||||
/* write slave address */ |
||||
writeb(slaveadd, &I2C->adr); |
||||
|
||||
/* clear status register */ |
||||
writeb(0x00, &I2C->sr); |
||||
|
||||
/* start I2C controller */ |
||||
writeb(I2C_CR_MEN, &I2C->cr); |
||||
} |
||||
|
||||
static __inline__ int |
||||
i2c_wait4bus (void) |
||||
{ |
||||
ulong timeval = get_timer (0); |
||||
while (readb(&I2C->sr) & I2C_SR_MBB) { |
||||
if (get_timer (timeval) > I2C_TIMEOUT) { |
||||
return -1; |
||||
} |
||||
} |
||||
return 0; |
||||
} |
||||
|
||||
static __inline__ int |
||||
i2c_wait (int write) |
||||
{ |
||||
u32 csr; |
||||
ulong timeval = get_timer(0); |
||||
do { |
||||
csr = readb(&I2C->sr); |
||||
|
||||
if (!(csr & I2C_SR_MIF)) |
||||
continue; |
||||
|
||||
writeb(0x0, &I2C->sr); |
||||
|
||||
if (csr & I2C_SR_MAL) { |
||||
debug("i2c_wait: MAL\n"); |
||||
return -1; |
||||
} |
||||
|
||||
if (!(csr & I2C_SR_MCF)) { |
||||
debug("i2c_wait: unfinished\n"); |
||||
return -1; |
||||
} |
||||
|
||||
if (write == I2C_WRITE && (csr & I2C_SR_RXAK)) { |
||||
debug("i2c_wait: No RXACK\n"); |
||||
return -1; |
||||
} |
||||
|
||||
return 0; |
||||
} while (get_timer (timeval) < I2C_TIMEOUT); |
||||
|
||||
debug("i2c_wait: timed out\n"); |
||||
return -1; |
||||
} |
||||
|
||||
static __inline__ int |
||||
i2c_write_addr (u8 dev, u8 dir, int rsta) |
||||
{ |
||||
writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX | |
||||
(rsta?I2C_CR_RSTA:0), |
||||
&I2C->cr); |
||||
|
||||
writeb((dev << 1) | dir, &I2C->dr); |
||||
|
||||
if (i2c_wait (I2C_WRITE) < 0) |
||||
return 0; |
||||
return 1; |
||||
} |
||||
|
||||
static __inline__ int |
||||
__i2c_write (u8 *data, int length) |
||||
{ |
||||
int i; |
||||
|
||||
writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX, |
||||
&I2C->cr); |
||||
|
||||
for (i=0; i < length; i++) { |
||||
writeb(data[i], &I2C->dr); |
||||
|
||||
if (i2c_wait (I2C_WRITE) < 0) |
||||
break; |
||||
} |
||||
return i; |
||||
} |
||||
|
||||
static __inline__ int |
||||
__i2c_read (u8 *data, int length) |
||||
{ |
||||
int i; |
||||
|
||||
writeb(I2C_CR_MEN | I2C_CR_MSTA | |
||||
((length == 1) ? I2C_CR_TXAK : 0), |
||||
&I2C->cr); |
||||
|
||||
/* dummy read */ |
||||
readb(&I2C->dr); |
||||
|
||||
for (i=0; i < length; i++) { |
||||
if (i2c_wait (I2C_READ) < 0) |
||||
break; |
||||
|
||||
/* Generate ack on last next to last byte */ |
||||
if (i == length - 2) |
||||
writeb(I2C_CR_MEN | I2C_CR_MSTA | |
||||
I2C_CR_TXAK, |
||||
&I2C->cr); |
||||
|
||||
/* Generate stop on last byte */ |
||||
if (i == length - 1) |
||||
writeb(I2C_CR_MEN | I2C_CR_TXAK, &I2C->cr); |
||||
|
||||
data[i] = readb(&I2C->dr); |
||||
} |
||||
return i; |
||||
} |
||||
|
||||
int |
||||
i2c_read (u8 dev, uint addr, int alen, u8 *data, int length) |
||||
{ |
||||
int i = 0; |
||||
u8 *a = (u8*)&addr; |
||||
|
||||
if (i2c_wait4bus () < 0) |
||||
goto exit; |
||||
|
||||
if (i2c_write_addr (dev, I2C_WRITE, 0) == 0) |
||||
goto exit; |
||||
|
||||
if (__i2c_write (&a[4 - alen], alen) != alen) |
||||
goto exit; |
||||
|
||||
if (i2c_write_addr (dev, I2C_READ, 1) == 0) |
||||
goto exit; |
||||
|
||||
i = __i2c_read (data, length); |
||||
|
||||
exit: |
||||
writeb(I2C_CR_MEN, &I2C->cr); |
||||
return !(i == length); |
||||
} |
||||
|
||||
int |
||||
i2c_write (u8 dev, uint addr, int alen, u8 *data, int length) |
||||
{ |
||||
int i = 0; |
||||
u8 *a = (u8*)&addr; |
||||
|
||||
if (i2c_wait4bus () < 0) |
||||
goto exit; |
||||
|
||||
if (i2c_write_addr (dev, I2C_WRITE, 0) == 0) |
||||
goto exit; |
||||
|
||||
if (__i2c_write (&a[4 - alen], alen) != alen) |
||||
goto exit; |
||||
|
||||
i = __i2c_write (data, length); |
||||
|
||||
exit: |
||||
writeb(I2C_CR_MEN, &I2C->cr); |
||||
return !(i == length); |
||||
} |
||||
|
||||
int i2c_probe (uchar chip) |
||||
{ |
||||
int tmp; |
||||
|
||||
/*
|
||||
* Try to read the first location of the chip. The underlying |
||||
* driver doesn't appear to support sending just the chip address |
||||
* and looking for an <ACK> back. |
||||
*/ |
||||
udelay(10000); |
||||
return i2c_read (chip, 0, 1, (uchar *)&tmp, 1); |
||||
} |
||||
|
||||
uchar i2c_reg_read (uchar i2c_addr, uchar reg) |
||||
{ |
||||
uchar buf[1]; |
||||
|
||||
i2c_read (i2c_addr, reg, 1, buf, 1); |
||||
|
||||
return (buf[0]); |
||||
} |
||||
|
||||
void i2c_reg_write (uchar i2c_addr, uchar reg, uchar val) |
||||
{ |
||||
i2c_write (i2c_addr, reg, 1, &val, 1); |
||||
} |
||||
|
||||
#endif /* CONFIG_HARD_I2C */ |
||||
@ -0,0 +1,85 @@ |
||||
/*
|
||||
* Copyright (C) 2006 Freescale Semiconductor, Inc. |
||||
* |
||||
* Dave Liu <daveliu@freescale.com> |
||||
* based on source code of Shlomi Gridish |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include "common.h" |
||||
#include "asm/errno.h" |
||||
#include "asm/io.h" |
||||
#include "asm/immap_83xx.h" |
||||
|
||||
#if defined(CONFIG_QE) |
||||
#define NUM_OF_PINS 32 |
||||
void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign) |
||||
{ |
||||
u32 pin_2bit_mask; |
||||
u32 pin_2bit_dir; |
||||
u32 pin_2bit_assign; |
||||
u32 pin_1bit_mask; |
||||
u32 tmp_val; |
||||
volatile immap_t *im = (volatile immap_t *)CFG_IMMR; |
||||
volatile gpio83xx_t *par_io =(volatile gpio83xx_t *)&im->gpio; |
||||
|
||||
/* Caculate pin location and 2bit mask and dir */ |
||||
pin_2bit_mask = (u32)(0x3 << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2)); |
||||
pin_2bit_dir = (u32)(dir << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2)); |
||||
|
||||
/* Setup the direction */ |
||||
tmp_val = (pin > (NUM_OF_PINS/2) - 1) ? \
|
||||
in_be32(&par_io->ioport[port].dir2) : |
||||
in_be32(&par_io->ioport[port].dir1); |
||||
|
||||
if (pin > (NUM_OF_PINS/2) -1) { |
||||
out_be32(&par_io->ioport[port].dir2, ~pin_2bit_mask & tmp_val); |
||||
out_be32(&par_io->ioport[port].dir2, pin_2bit_dir | tmp_val); |
||||
} else { |
||||
out_be32(&par_io->ioport[port].dir1, ~pin_2bit_mask & tmp_val); |
||||
out_be32(&par_io->ioport[port].dir1, pin_2bit_dir | tmp_val); |
||||
} |
||||
|
||||
/* Calculate pin location for 1bit mask */ |
||||
pin_1bit_mask = (u32)(1 << (NUM_OF_PINS - (pin+1))); |
||||
|
||||
/* Setup the open drain */ |
||||
tmp_val = in_be32(&par_io->ioport[port].podr); |
||||
if (open_drain) { |
||||
out_be32(&par_io->ioport[port].podr, pin_1bit_mask | tmp_val); |
||||
} else { |
||||
out_be32(&par_io->ioport[port].podr, ~pin_1bit_mask & tmp_val); |
||||
} |
||||
|
||||
/* Setup the assignment */ |
||||
tmp_val = (pin > (NUM_OF_PINS/2) - 1) ? |
||||
in_be32(&par_io->ioport[port].ppar2): |
||||
in_be32(&par_io->ioport[port].ppar1); |
||||
pin_2bit_assign = (u32)(assign |
||||
<< (NUM_OF_PINS - (pin%(NUM_OF_PINS/2)+1)*2)); |
||||
|
||||
/* Clear and set 2 bits mask */ |
||||
if (pin > (NUM_OF_PINS/2) - 1) { |
||||
out_be32(&par_io->ioport[port].ppar2, ~pin_2bit_mask & tmp_val); |
||||
out_be32(&par_io->ioport[port].ppar2, pin_2bit_assign | tmp_val); |
||||
} else { |
||||
out_be32(&par_io->ioport[port].ppar1, ~pin_2bit_mask & tmp_val); |
||||
out_be32(&par_io->ioport[port].ppar1, pin_2bit_assign | tmp_val); |
||||
} |
||||
} |
||||
|
||||
#endif /* CONFIG_QE */ |
||||
@ -1,6 +0,0 @@ |
||||
.section .resetvec,"ax" |
||||
#ifndef FIXME |
||||
#if 0 |
||||
b _start_e500 |
||||
#endif |
||||
#endif |
||||
@ -0,0 +1,126 @@ |
||||
Freescale MPC8360EMDS Board |
||||
----------------------------------------- |
||||
1. Board Switches and Jumpers |
||||
1.0 There are four Dual-In-Line Packages(DIP) Switches on MPC8360EMDS board |
||||
For some reason, the HW designers describe the switch settings |
||||
in terms of 0 and 1, and then map that to physical switches where |
||||
the label "On" refers to logic 0 and "Off" is logic 1. |
||||
|
||||
Switch bits are numbered 1 through, like, 4 6 8 or 10, but the |
||||
bits may contribute to signals that are numbered based at 0, |
||||
and some of those signals may be high-bit-number-0 too. Heed |
||||
well the names and labels and do not get confused. |
||||
|
||||
"Off" == 1 |
||||
"On" == 0 |
||||
|
||||
SW18 is switch 18 as silk-screened onto the board. |
||||
SW4[8] is the bit labled 8 on Switch 4. |
||||
SW2[1:6] refers to bits labeled 1 through 6 in order on switch 2. |
||||
SW3[7:1] refers to bits labeled 7 through 1 in order on switch 3. |
||||
SW3[1:8]= 0000_0001 refers to bits labeled 1 through 6 is set as "On" |
||||
and bits labeled 8 is set as "Off". |
||||
|
||||
1.1 For the MPC8360E PB PROTO Board |
||||
|
||||
First, make sure the board default setting is consistent with the |
||||
document shipped with your board. Then apply the following setting: |
||||
SW3[1-8]= 0000_0100 (HRCW setting value is performed on local bus) |
||||
SW4[1-8]= 0011_0000 (Flash boot on local bus) |
||||
SW9[1-8]= 0110_0110 (PCI Mode enabled. HRCW is read from FLASH) |
||||
SW10[1-8]= 0000_1000 (core PLL setting) |
||||
SW11[1-8]= 0000_0100 (SW11 is on the another side of the board) |
||||
JP6 1-2 |
||||
on board Oscillator: 66M |
||||
|
||||
|
||||
2. Memory Map |
||||
|
||||
2.1. The memory map should look pretty much like this: |
||||
|
||||
0x0000_0000 0x7fff_ffff DDR 2G |
||||
0x8000_0000 0x8fff_ffff PCI MEM prefetch 256M |
||||
0x9000_0000 0x9fff_ffff PCI MEM non-prefetch 256M |
||||
0xc000_0000 0xdfff_ffff Empty 512M |
||||
0xe000_0000 0xe01f_ffff Int Mem Reg Space 2M |
||||
0xe020_0000 0xe02f_ffff Empty 1M |
||||
0xe030_0000 0xe03f_ffff PCI IO 1M |
||||
0xe040_0000 0xefff_ffff Empty 252M |
||||
0xf000_0000 0xf3ff_ffff Local Bus SDRAM 64M |
||||
0xf400_0000 0xf7ff_ffff Empty 64M |
||||
0xf800_0000 0xf800_7fff BCSR on CS1 32K |
||||
0xf800_8000 0xf800_ffff PIB CS4 32K |
||||
0xf801_0000 0xf801_7fff PIB CS5 32K |
||||
0xfe00_0000 0xfeff_ffff FLASH on CS0 16M |
||||
|
||||
|
||||
3. Definitions |
||||
|
||||
3.1 Explanation of NEW definitions in: |
||||
|
||||
include/configs/MPC8360EMDS.h |
||||
|
||||
CONFIG_MPC83XX MPC83xx family for both MPC8349 and MPC8360 |
||||
CONFIG_MPC8360 MPC8360 specific |
||||
CONFIG_MPC8360EMDS MPC8360EMDS board specific |
||||
|
||||
4. Compilation |
||||
|
||||
Assuming you're using BASH shell: |
||||
|
||||
export CROSS_COMPILE=your-cross-compile-prefix |
||||
cd u-boot |
||||
make distclean |
||||
make MPC8360EMDS_config |
||||
make |
||||
|
||||
MPC8360 support PCI in host and slave mode. |
||||
|
||||
To make u-boot support PCI host 66M : |
||||
1) DIP SW support PCI mode as described in Section 1.1. |
||||
2) Make MPC8360EMDS_HOST_66_config |
||||
|
||||
To make u-boot support PCI host 33M : |
||||
1) DIP SW setting is similar as Section 1.1, except for SW3[4] is 1 |
||||
2) Make MPC8360EMDS_HOST_33_config |
||||
|
||||
To make u-boot support PCI slave 66M : |
||||
1) DIP SW setting is similar as Section 1.1, except for SW9[3] is 1 |
||||
2) Make MPC8360EMDS_SLAVE_config |
||||
|
||||
|
||||
5. Downloading and Flashing Images |
||||
|
||||
5.0 Download over serial line using Kermit: |
||||
|
||||
loadb |
||||
[Drop to kermit: |
||||
^\c |
||||
send <u-boot-bin-image> |
||||
c |
||||
] |
||||
|
||||
|
||||
Or via tftp: |
||||
|
||||
tftp 10000 u-boot.bin |
||||
|
||||
5.1 Reflash U-boot Image using U-boot |
||||
|
||||
tftp 20000 u-boot.bin |
||||
protect off fef00000 fef3ffff |
||||
erase fef00000 fef3ffff |
||||
|
||||
cp.b 20000 fef00000 xxxx |
||||
|
||||
or |
||||
|
||||
cp.b 20000 fef00000 3ffff |
||||
|
||||
|
||||
You have to supply the correct byte count with 'xxxx' from the TFTP result log. |
||||
Maybe 3ffff will work too, that corresponds to the erased sectors. |
||||
|
||||
|
||||
6. Notes |
||||
1) The console baudrate for MPC8360EMDS is 115200bps. |
||||
@ -0,0 +1,43 @@ |
||||
#
|
||||
# Copyright (C) 2006 Freescale Semiconductor, Inc.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk |
||||
|
||||
LIB := $(obj)qe.a
|
||||
|
||||
COBJS := qe.o uccf.o uec.o uec_phy.o
|
||||
|
||||
SRCS := $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
||||
all: $(LIB) |
||||
|
||||
$(LIB): $(obj).depend $(OBJS) |
||||
$(AR) $(ARFLAGS) $@ $(OBJS)
|
||||
|
||||
#########################################################################
|
||||
|
||||
include $(SRCTREE)/rules.mk |
||||
|
||||
sinclude $(obj).depend |
||||
|
||||
#########################################################################
|
||||
@ -0,0 +1,254 @@ |
||||
/*
|
||||
* Copyright (C) 2006 Freescale Semiconductor, Inc. |
||||
* |
||||
* Dave Liu <daveliu@freescale.com> |
||||
* based on source code of Shlomi Gridish |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include "common.h" |
||||
#include "asm/errno.h" |
||||
#include "asm/io.h" |
||||
#include "asm/immap_qe.h" |
||||
#include "qe.h" |
||||
|
||||
#if defined(CONFIG_QE) |
||||
qe_map_t *qe_immr = NULL; |
||||
static qe_snum_t snums[QE_NUM_OF_SNUM]; |
||||
|
||||
void qe_issue_cmd(uint cmd, uint sbc, u8 mcn, u32 cmd_data) |
||||
{ |
||||
u32 cecr; |
||||
|
||||
if (cmd == QE_RESET) { |
||||
out_be32(&qe_immr->cp.cecr,(u32) (cmd | QE_CR_FLG)); |
||||
} else { |
||||
out_be32(&qe_immr->cp.cecdr, cmd_data); |
||||
out_be32(&qe_immr->cp.cecr, (sbc | QE_CR_FLG | |
||||
((u32) mcn<<QE_CR_PROTOCOL_SHIFT) | cmd)); |
||||
} |
||||
/* Wait for the QE_CR_FLG to clear */ |
||||
do { |
||||
cecr = in_be32(&qe_immr->cp.cecr); |
||||
} while (cecr & QE_CR_FLG); |
||||
|
||||
return; |
||||
} |
||||
|
||||
uint qe_muram_alloc(uint size, uint align) |
||||
{ |
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
uint retloc; |
||||
uint align_mask, off; |
||||
uint savebase; |
||||
|
||||
align_mask = align - 1; |
||||
savebase = gd->mp_alloc_base; |
||||
|
||||
if ((off = (gd->mp_alloc_base & align_mask)) != 0) |
||||
gd->mp_alloc_base += (align - off); |
||||
|
||||
if ((off = size & align_mask) != 0) |
||||
size += (align - off); |
||||
|
||||
if ((gd->mp_alloc_base + size) >= gd->mp_alloc_top) { |
||||
gd->mp_alloc_base = savebase; |
||||
printf("%s: ran out of ram.\n", __FUNCTION__); |
||||
} |
||||
|
||||
retloc = gd->mp_alloc_base; |
||||
gd->mp_alloc_base += size; |
||||
|
||||
memset((void *)&qe_immr->muram[retloc], 0, size); |
||||
|
||||
__asm__ __volatile__("sync"); |
||||
|
||||
return retloc; |
||||
} |
||||
|
||||
void *qe_muram_addr(uint offset) |
||||
{ |
||||
return (void *)&qe_immr->muram[offset]; |
||||
} |
||||
|
||||
static void qe_sdma_init(void) |
||||
{ |
||||
volatile sdma_t *p; |
||||
uint sdma_buffer_base; |
||||
|
||||
p = (volatile sdma_t *)&qe_immr->sdma; |
||||
|
||||
/* All of DMA transaction in bus 1 */ |
||||
out_be32(&p->sdaqr, 0); |
||||
out_be32(&p->sdaqmr, 0); |
||||
|
||||
/* Allocate 2KB temporary buffer for sdma */ |
||||
sdma_buffer_base = qe_muram_alloc(2048, 64); |
||||
out_be32(&p->sdwbcr, sdma_buffer_base & QE_SDEBCR_BA_MASK); |
||||
|
||||
/* Clear sdma status */ |
||||
out_be32(&p->sdsr, 0x03000000); |
||||
|
||||
/* Enable global mode on bus 1, and 2KB buffer size */ |
||||
out_be32(&p->sdmr, QE_SDMR_GLB_1_MSK | (0x3 << QE_SDMR_CEN_SHIFT)); |
||||
} |
||||
|
||||
static u8 thread_snum[QE_NUM_OF_SNUM] = { |
||||
0x04, 0x05, 0x0c, 0x0d, |
||||
0x14, 0x15, 0x1c, 0x1d, |
||||
0x24, 0x25, 0x2c, 0x2d, |
||||
0x34, 0x35, 0x88, 0x89, |
||||
0x98, 0x99, 0xa8, 0xa9, |
||||
0xb8, 0xb9, 0xc8, 0xc9, |
||||
0xd8, 0xd9, 0xe8, 0xe9 |
||||
}; |
||||
|
||||
static void qe_snums_init(void) |
||||
{ |
||||
int i; |
||||
|
||||
for (i = 0; i < QE_NUM_OF_SNUM; i++) { |
||||
snums[i].state = QE_SNUM_STATE_FREE; |
||||
snums[i].num = thread_snum[i]; |
||||
} |
||||
} |
||||
|
||||
int qe_get_snum(void) |
||||
{ |
||||
int snum = -EBUSY; |
||||
int i; |
||||
|
||||
for (i = 0; i < QE_NUM_OF_SNUM; i++) { |
||||
if (snums[i].state == QE_SNUM_STATE_FREE) { |
||||
snums[i].state = QE_SNUM_STATE_USED; |
||||
snum = snums[i].num; |
||||
break; |
||||
} |
||||
} |
||||
|
||||
return snum; |
||||
} |
||||
|
||||
void qe_put_snum(u8 snum) |
||||
{ |
||||
int i; |
||||
|
||||
for (i = 0; i < QE_NUM_OF_SNUM; i++) { |
||||
if (snums[i].num == snum) { |
||||
snums[i].state = QE_SNUM_STATE_FREE; |
||||
break; |
||||
} |
||||
} |
||||
} |
||||
|
||||
void qe_init(uint qe_base) |
||||
{ |
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
/* Init the QE IMMR base */ |
||||
qe_immr = (qe_map_t *)qe_base; |
||||
|
||||
gd->mp_alloc_base = QE_DATAONLY_BASE; |
||||
gd->mp_alloc_top = gd->mp_alloc_base + QE_DATAONLY_SIZE; |
||||
|
||||
qe_sdma_init(); |
||||
qe_snums_init(); |
||||
} |
||||
|
||||
void qe_reset(void) |
||||
{ |
||||
qe_issue_cmd(QE_RESET, QE_CR_SUBBLOCK_INVALID, |
||||
(u8) QE_CR_PROTOCOL_UNSPECIFIED, 0); |
||||
} |
||||
|
||||
void qe_assign_page(uint snum, uint para_ram_base) |
||||
{ |
||||
u32 cecr; |
||||
|
||||
out_be32(&qe_immr->cp.cecdr, para_ram_base); |
||||
out_be32(&qe_immr->cp.cecr, ((u32) snum<<QE_CR_ASSIGN_PAGE_SNUM_SHIFT) |
||||
| QE_CR_FLG | QE_ASSIGN_PAGE); |
||||
|
||||
/* Wait for the QE_CR_FLG to clear */ |
||||
do { |
||||
cecr = in_be32(&qe_immr->cp.cecr); |
||||
} while (cecr & QE_CR_FLG ); |
||||
|
||||
return; |
||||
} |
||||
|
||||
/*
|
||||
* brg: 0~15 as BRG1~BRG16 |
||||
rate: baud rate |
||||
* BRG input clock comes from the BRGCLK (internal clock generated from |
||||
the QE clock, it is one-half of the QE clock), If need the clock source |
||||
from CLKn pin, we have te change the function. |
||||
*/ |
||||
|
||||
#define BRG_CLK (gd->brg_clk) |
||||
|
||||
int qe_set_brg(uint brg, uint rate) |
||||
{ |
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
volatile uint *bp; |
||||
u32 divisor; |
||||
int div16 = 0; |
||||
|
||||
if (brg >= QE_NUM_OF_BRGS) |
||||
return -EINVAL; |
||||
bp = (uint *)&qe_immr->brg.brgc1; |
||||
bp += brg; |
||||
|
||||
divisor = (BRG_CLK / rate); |
||||
if (divisor > QE_BRGC_DIVISOR_MAX + 1) { |
||||
div16 = 1; |
||||
divisor /= 16; |
||||
} |
||||
|
||||
*bp = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) | QE_BRGC_ENABLE; |
||||
__asm__ __volatile__("sync"); |
||||
|
||||
if (div16) { |
||||
*bp |= QE_BRGC_DIV16; |
||||
__asm__ __volatile__("sync"); |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/* Set ethernet MII clock master
|
||||
*/ |
||||
int qe_set_mii_clk_src(int ucc_num) |
||||
{ |
||||
u32 cmxgcr; |
||||
|
||||
/* check if the UCC number is in range. */ |
||||
if ((ucc_num > UCC_MAX_NUM - 1) || (ucc_num < 0)) { |
||||
printf("%s: ucc num not in ranges\n", __FUNCTION__); |
||||
return -EINVAL; |
||||
} |
||||
|
||||
cmxgcr = in_be32(&qe_immr->qmx.cmxgcr); |
||||
cmxgcr &= ~QE_CMXGCR_MII_ENET_MNG_MASK; |
||||
cmxgcr |= (ucc_num <<QE_CMXGCR_MII_ENET_MNG_SHIFT); |
||||
out_be32(&qe_immr->qmx.cmxgcr, cmxgcr); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
#endif /* CONFIG_QE */ |
||||
@ -0,0 +1,237 @@ |
||||
/*
|
||||
* Copyright (C) 2006 Freescale Semiconductor, Inc. |
||||
* |
||||
* Dave Liu <daveliu@freescale.com> |
||||
* based on source code of Shlomi Gridish |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __QE_H__ |
||||
#define __QE_H__ |
||||
|
||||
#include "common.h" |
||||
|
||||
#define QE_NUM_OF_SNUM 28 |
||||
#define QE_NUM_OF_BRGS 16 |
||||
#define UCC_MAX_NUM 8 |
||||
|
||||
#define QE_DATAONLY_BASE (uint)(128) |
||||
#define QE_DATAONLY_SIZE ((uint)(0xc000) - QE_DATAONLY_BASE) |
||||
|
||||
/* QE threads SNUM
|
||||
*/ |
||||
typedef enum qe_snum_state { |
||||
QE_SNUM_STATE_USED, /* used */ |
||||
QE_SNUM_STATE_FREE /* free */ |
||||
} qe_snum_state_e; |
||||
|
||||
typedef struct qe_snum { |
||||
u8 num; /* snum */ |
||||
qe_snum_state_e state; /* state */ |
||||
} qe_snum_t; |
||||
|
||||
/* QE RISC allocation
|
||||
*/ |
||||
typedef enum qe_risc_allocation { |
||||
QE_RISC_ALLOCATION_RISC1 = 1, /* RISC 1 */ |
||||
QE_RISC_ALLOCATION_RISC2 = 2, /* RISC 2 */ |
||||
QE_RISC_ALLOCATION_RISC1_AND_RISC2 = 3 /* RISC 1 or RISC 2 */ |
||||
} qe_risc_allocation_e; |
||||
|
||||
/* QE CECR commands for UCC fast.
|
||||
*/ |
||||
#define QE_CR_FLG 0x00010000 |
||||
#define QE_RESET 0x80000000 |
||||
#define QE_INIT_TX_RX 0x00000000 |
||||
#define QE_INIT_RX 0x00000001 |
||||
#define QE_INIT_TX 0x00000002 |
||||
#define QE_ENTER_HUNT_MODE 0x00000003 |
||||
#define QE_STOP_TX 0x00000004 |
||||
#define QE_GRACEFUL_STOP_TX 0x00000005 |
||||
#define QE_RESTART_TX 0x00000006 |
||||
#define QE_SWITCH_COMMAND 0x00000007 |
||||
#define QE_SET_GROUP_ADDRESS 0x00000008 |
||||
#define QE_INSERT_CELL 0x00000009 |
||||
#define QE_ATM_TRANSMIT 0x0000000a |
||||
#define QE_CELL_POOL_GET 0x0000000b |
||||
#define QE_CELL_POOL_PUT 0x0000000c |
||||
#define QE_IMA_HOST_CMD 0x0000000d |
||||
#define QE_ATM_MULTI_THREAD_INIT 0x00000011 |
||||
#define QE_ASSIGN_PAGE 0x00000012 |
||||
#define QE_START_FLOW_CONTROL 0x00000014 |
||||
#define QE_STOP_FLOW_CONTROL 0x00000015 |
||||
#define QE_ASSIGN_PAGE_TO_DEVICE 0x00000016 |
||||
#define QE_GRACEFUL_STOP_RX 0x0000001a |
||||
#define QE_RESTART_RX 0x0000001b |
||||
|
||||
/* QE CECR Sub Block Code - sub block code of QE command.
|
||||
*/ |
||||
#define QE_CR_SUBBLOCK_INVALID 0x00000000 |
||||
#define QE_CR_SUBBLOCK_USB 0x03200000 |
||||
#define QE_CR_SUBBLOCK_UCCFAST1 0x02000000 |
||||
#define QE_CR_SUBBLOCK_UCCFAST2 0x02200000 |
||||
#define QE_CR_SUBBLOCK_UCCFAST3 0x02400000 |
||||
#define QE_CR_SUBBLOCK_UCCFAST4 0x02600000 |
||||
#define QE_CR_SUBBLOCK_UCCFAST5 0x02800000 |
||||
#define QE_CR_SUBBLOCK_UCCFAST6 0x02a00000 |
||||
#define QE_CR_SUBBLOCK_UCCFAST7 0x02c00000 |
||||
#define QE_CR_SUBBLOCK_UCCFAST8 0x02e00000 |
||||
#define QE_CR_SUBBLOCK_UCCSLOW1 0x00000000 |
||||
#define QE_CR_SUBBLOCK_UCCSLOW2 0x00200000 |
||||
#define QE_CR_SUBBLOCK_UCCSLOW3 0x00400000 |
||||
#define QE_CR_SUBBLOCK_UCCSLOW4 0x00600000 |
||||
#define QE_CR_SUBBLOCK_UCCSLOW5 0x00800000 |
||||
#define QE_CR_SUBBLOCK_UCCSLOW6 0x00a00000 |
||||
#define QE_CR_SUBBLOCK_UCCSLOW7 0x00c00000 |
||||
#define QE_CR_SUBBLOCK_UCCSLOW8 0x00e00000 |
||||
#define QE_CR_SUBBLOCK_MCC1 0x03800000 |
||||
#define QE_CR_SUBBLOCK_MCC2 0x03a00000 |
||||
#define QE_CR_SUBBLOCK_MCC3 0x03000000 |
||||
#define QE_CR_SUBBLOCK_IDMA1 0x02800000 |
||||
#define QE_CR_SUBBLOCK_IDMA2 0x02a00000 |
||||
#define QE_CR_SUBBLOCK_IDMA3 0x02c00000 |
||||
#define QE_CR_SUBBLOCK_IDMA4 0x02e00000 |
||||
#define QE_CR_SUBBLOCK_HPAC 0x01e00000 |
||||
#define QE_CR_SUBBLOCK_SPI1 0x01400000 |
||||
#define QE_CR_SUBBLOCK_SPI2 0x01600000 |
||||
#define QE_CR_SUBBLOCK_RAND 0x01c00000 |
||||
#define QE_CR_SUBBLOCK_TIMER 0x01e00000 |
||||
#define QE_CR_SUBBLOCK_GENERAL 0x03c00000 |
||||
|
||||
/* QE CECR Protocol - For non-MCC, specifies mode for QE CECR command.
|
||||
*/ |
||||
#define QE_CR_PROTOCOL_UNSPECIFIED 0x00 /* For all other protocols */ |
||||
#define QE_CR_PROTOCOL_HDLC_TRANSPARENT 0x00 |
||||
#define QE_CR_PROTOCOL_ATM_POS 0x0A |
||||
#define QE_CR_PROTOCOL_ETHERNET 0x0C |
||||
#define QE_CR_PROTOCOL_L2_SWITCH 0x0D |
||||
#define QE_CR_PROTOCOL_SHIFT 6 |
||||
|
||||
/* QE ASSIGN PAGE command
|
||||
*/ |
||||
#define QE_CR_ASSIGN_PAGE_SNUM_SHIFT 17 |
||||
|
||||
/* Communication Direction.
|
||||
*/ |
||||
typedef enum comm_dir { |
||||
COMM_DIR_NONE = 0, |
||||
COMM_DIR_RX = 1, |
||||
COMM_DIR_TX = 2, |
||||
COMM_DIR_RX_AND_TX = 3 |
||||
} comm_dir_e; |
||||
|
||||
/* Clocks and BRG's
|
||||
*/ |
||||
typedef enum qe_clock { |
||||
QE_CLK_NONE = 0, |
||||
QE_BRG1, /* Baud Rate Generator 1 */ |
||||
QE_BRG2, /* Baud Rate Generator 2 */ |
||||
QE_BRG3, /* Baud Rate Generator 3 */ |
||||
QE_BRG4, /* Baud Rate Generator 4 */ |
||||
QE_BRG5, /* Baud Rate Generator 5 */ |
||||
QE_BRG6, /* Baud Rate Generator 6 */ |
||||
QE_BRG7, /* Baud Rate Generator 7 */ |
||||
QE_BRG8, /* Baud Rate Generator 8 */ |
||||
QE_BRG9, /* Baud Rate Generator 9 */ |
||||
QE_BRG10, /* Baud Rate Generator 10 */ |
||||
QE_BRG11, /* Baud Rate Generator 11 */ |
||||
QE_BRG12, /* Baud Rate Generator 12 */ |
||||
QE_BRG13, /* Baud Rate Generator 13 */ |
||||
QE_BRG14, /* Baud Rate Generator 14 */ |
||||
QE_BRG15, /* Baud Rate Generator 15 */ |
||||
QE_BRG16, /* Baud Rate Generator 16 */ |
||||
QE_CLK1, /* Clock 1 */ |
||||
QE_CLK2, /* Clock 2 */ |
||||
QE_CLK3, /* Clock 3 */ |
||||
QE_CLK4, /* Clock 4 */ |
||||
QE_CLK5, /* Clock 5 */ |
||||
QE_CLK6, /* Clock 6 */ |
||||
QE_CLK7, /* Clock 7 */ |
||||
QE_CLK8, /* Clock 8 */ |
||||
QE_CLK9, /* Clock 9 */ |
||||
QE_CLK10, /* Clock 10 */ |
||||
QE_CLK11, /* Clock 11 */ |
||||
QE_CLK12, /* Clock 12 */ |
||||
QE_CLK13, /* Clock 13 */ |
||||
QE_CLK14, /* Clock 14 */ |
||||
QE_CLK15, /* Clock 15 */ |
||||
QE_CLK16, /* Clock 16 */ |
||||
QE_CLK17, /* Clock 17 */ |
||||
QE_CLK18, /* Clock 18 */ |
||||
QE_CLK19, /* Clock 19 */ |
||||
QE_CLK20, /* Clock 20 */ |
||||
QE_CLK21, /* Clock 21 */ |
||||
QE_CLK22, /* Clock 22 */ |
||||
QE_CLK23, /* Clock 23 */ |
||||
QE_CLK24, /* Clock 24 */ |
||||
QE_CLK_DUMMY |
||||
} qe_clock_e; |
||||
|
||||
/* QE CMXGCR register
|
||||
*/ |
||||
#define QE_CMXGCR_MII_ENET_MNG_MASK 0x00007000 |
||||
#define QE_CMXGCR_MII_ENET_MNG_SHIFT 12 |
||||
|
||||
/* QE CMXUCR registers
|
||||
*/ |
||||
#define QE_CMXUCR_TX_CLK_SRC_MASK 0x0000000F |
||||
|
||||
/* QE BRG configuration register
|
||||
*/ |
||||
#define QE_BRGC_ENABLE 0x00010000 |
||||
#define QE_BRGC_DIVISOR_SHIFT 1 |
||||
#define QE_BRGC_DIVISOR_MAX 0xFFF |
||||
#define QE_BRGC_DIV16 1 |
||||
|
||||
/* QE SDMA registers
|
||||
*/ |
||||
#define QE_SDSR_BER1 0x02000000 |
||||
#define QE_SDSR_BER2 0x01000000 |
||||
|
||||
#define QE_SDMR_GLB_1_MSK 0x80000000 |
||||
#define QE_SDMR_ADR_SEL 0x20000000 |
||||
#define QE_SDMR_BER1_MSK 0x02000000 |
||||
#define QE_SDMR_BER2_MSK 0x01000000 |
||||
#define QE_SDMR_EB1_MSK 0x00800000 |
||||
#define QE_SDMR_ER1_MSK 0x00080000 |
||||
#define QE_SDMR_ER2_MSK 0x00040000 |
||||
#define QE_SDMR_CEN_MASK 0x0000E000 |
||||
#define QE_SDMR_SBER_1 0x00000200 |
||||
#define QE_SDMR_SBER_2 0x00000200 |
||||
#define QE_SDMR_EB1_PR_MASK 0x000000C0 |
||||
#define QE_SDMR_ER1_PR 0x00000008 |
||||
|
||||
#define QE_SDMR_CEN_SHIFT 13 |
||||
#define QE_SDMR_EB1_PR_SHIFT 6 |
||||
|
||||
#define QE_SDTM_MSNUM_SHIFT 24 |
||||
|
||||
#define QE_SDEBCR_BA_MASK 0x01FFFFFF |
||||
|
||||
void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign); |
||||
void qe_issue_cmd(uint cmd, uint sbc, u8 mcn, u32 cmd_data); |
||||
uint qe_muram_alloc(uint size, uint align); |
||||
void *qe_muram_addr(uint offset); |
||||
int qe_get_snum(void); |
||||
void qe_put_snum(u8 snum); |
||||
void qe_init(uint qe_base); |
||||
void qe_reset(void); |
||||
void qe_assign_page(uint snum, uint para_ram_base); |
||||
int qe_set_brg(uint brg, uint rate); |
||||
int qe_set_mii_clk_src(int ucc_num); |
||||
|
||||
#endif /* __QE_H__ */ |
||||
@ -0,0 +1,404 @@ |
||||
/*
|
||||
* Copyright (C) 2006 Freescale Semiconductor, Inc. |
||||
* |
||||
* Dave Liu <daveliu@freescale.com> |
||||
* based on source code of Shlomi Gridish |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include "common.h" |
||||
#include "malloc.h" |
||||
#include "asm/errno.h" |
||||
#include "asm/io.h" |
||||
#include "asm/immap_qe.h" |
||||
#include "qe.h" |
||||
#include "uccf.h" |
||||
|
||||
#if defined(CONFIG_QE) |
||||
void ucc_fast_transmit_on_demand(ucc_fast_private_t *uccf) |
||||
{ |
||||
out_be16(&uccf->uf_regs->utodr, UCC_FAST_TOD); |
||||
} |
||||
|
||||
u32 ucc_fast_get_qe_cr_subblock(int ucc_num) |
||||
{ |
||||
switch (ucc_num) { |
||||
case 0: return QE_CR_SUBBLOCK_UCCFAST1; |
||||
case 1: return QE_CR_SUBBLOCK_UCCFAST2; |
||||
case 2: return QE_CR_SUBBLOCK_UCCFAST3; |
||||
case 3: return QE_CR_SUBBLOCK_UCCFAST4; |
||||
case 4: return QE_CR_SUBBLOCK_UCCFAST5; |
||||
case 5: return QE_CR_SUBBLOCK_UCCFAST6; |
||||
case 6: return QE_CR_SUBBLOCK_UCCFAST7; |
||||
case 7: return QE_CR_SUBBLOCK_UCCFAST8; |
||||
default: return QE_CR_SUBBLOCK_INVALID; |
||||
} |
||||
} |
||||
|
||||
static void ucc_get_cmxucr_reg(int ucc_num, volatile u32 **p_cmxucr, |
||||
u8 *reg_num, u8 *shift) |
||||
{ |
||||
switch (ucc_num) { |
||||
case 0: /* UCC1 */ |
||||
*p_cmxucr = &(qe_immr->qmx.cmxucr1); |
||||
*reg_num = 1; |
||||
*shift = 16; |
||||
break; |
||||
case 2: /* UCC3 */ |
||||
*p_cmxucr = &(qe_immr->qmx.cmxucr1); |
||||
*reg_num = 1; |
||||
*shift = 0; |
||||
break; |
||||
case 4: /* UCC5 */ |
||||
*p_cmxucr = &(qe_immr->qmx.cmxucr2); |
||||
*reg_num = 2; |
||||
*shift = 16; |
||||
break; |
||||
case 6: /* UCC7 */ |
||||
*p_cmxucr = &(qe_immr->qmx.cmxucr2); |
||||
*reg_num = 2; |
||||
*shift = 0; |
||||
break; |
||||
case 1: /* UCC2 */ |
||||
*p_cmxucr = &(qe_immr->qmx.cmxucr3); |
||||
*reg_num = 3; |
||||
*shift = 16; |
||||
break; |
||||
case 3: /* UCC4 */ |
||||
*p_cmxucr = &(qe_immr->qmx.cmxucr3); |
||||
*reg_num = 3; |
||||
*shift = 0; |
||||
break; |
||||
case 5: /* UCC6 */ |
||||
*p_cmxucr = &(qe_immr->qmx.cmxucr4); |
||||
*reg_num = 4; |
||||
*shift = 16; |
||||
break; |
||||
case 7: /* UCC8 */ |
||||
*p_cmxucr = &(qe_immr->qmx.cmxucr4); |
||||
*reg_num = 4; |
||||
*shift = 0; |
||||
break; |
||||
default: |
||||
break; |
||||
} |
||||
} |
||||
|
||||
static int ucc_set_clk_src(int ucc_num, qe_clock_e clock, comm_dir_e mode) |
||||
{ |
||||
volatile u32 *p_cmxucr = NULL; |
||||
u8 reg_num = 0; |
||||
u8 shift = 0; |
||||
u32 clockBits; |
||||
u32 clockMask; |
||||
int source = -1; |
||||
|
||||
/* check if the UCC number is in range. */ |
||||
if ((ucc_num > UCC_MAX_NUM - 1) || (ucc_num < 0)) |
||||
return -EINVAL; |
||||
|
||||
if (! ((mode == COMM_DIR_RX) || (mode == COMM_DIR_TX))) { |
||||
printf("%s: bad comm mode type passed\n", __FUNCTION__); |
||||
return -EINVAL; |
||||
} |
||||
|
||||
ucc_get_cmxucr_reg(ucc_num, &p_cmxucr, ®_num, &shift); |
||||
|
||||
switch (reg_num) { |
||||
case 1: |
||||
switch (clock) { |
||||
case QE_BRG1: source = 1; break; |
||||
case QE_BRG2: source = 2; break; |
||||
case QE_BRG7: source = 3; break; |
||||
case QE_BRG8: source = 4; break; |
||||
case QE_CLK9: source = 5; break; |
||||
case QE_CLK10: source = 6; break; |
||||
case QE_CLK11: source = 7; break; |
||||
case QE_CLK12: source = 8; break; |
||||
case QE_CLK15: source = 9; break; |
||||
case QE_CLK16: source = 10; break; |
||||
default: source = -1; break; |
||||
} |
||||
break; |
||||
case 2: |
||||
switch (clock) { |
||||
case QE_BRG5: source = 1; break; |
||||
case QE_BRG6: source = 2; break; |
||||
case QE_BRG7: source = 3; break; |
||||
case QE_BRG8: source = 4; break; |
||||
case QE_CLK13: source = 5; break; |
||||
case QE_CLK14: source = 6; break; |
||||
case QE_CLK19: source = 7; break; |
||||
case QE_CLK20: source = 8; break; |
||||
case QE_CLK15: source = 9; break; |
||||
case QE_CLK16: source = 10; break; |
||||
default: source = -1; break; |
||||
} |
||||
break; |
||||
case 3: |
||||
switch (clock) { |
||||
case QE_BRG9: source = 1; break; |
||||
case QE_BRG10: source = 2; break; |
||||
case QE_BRG15: source = 3; break; |
||||
case QE_BRG16: source = 4; break; |
||||
case QE_CLK3: source = 5; break; |
||||
case QE_CLK4: source = 6; break; |
||||
case QE_CLK17: source = 7; break; |
||||
case QE_CLK18: source = 8; break; |
||||
case QE_CLK7: source = 9; break; |
||||
case QE_CLK8: source = 10; break; |
||||
case QE_CLK16: source = 11; break; |
||||
default: source = -1; break; |
||||
} |
||||
break; |
||||
case 4: |
||||
switch (clock) { |
||||
case QE_BRG13: source = 1; break; |
||||
case QE_BRG14: source = 2; break; |
||||
case QE_BRG15: source = 3; break; |
||||
case QE_BRG16: source = 4; break; |
||||
case QE_CLK5: source = 5; break; |
||||
case QE_CLK6: source = 6; break; |
||||
case QE_CLK21: source = 7; break; |
||||
case QE_CLK22: source = 8; break; |
||||
case QE_CLK7: source = 9; break; |
||||
case QE_CLK8: source = 10; break; |
||||
case QE_CLK16: source = 11; break; |
||||
default: source = -1; break; |
||||
} |
||||
break; |
||||
default: |
||||
source = -1; |
||||
break; |
||||
} |
||||
|
||||
if (source == -1) { |
||||
printf("%s: Bad combination of clock and UCC\n", __FUNCTION__); |
||||
return -ENOENT; |
||||
} |
||||
|
||||
clockBits = (u32) source; |
||||
clockMask = QE_CMXUCR_TX_CLK_SRC_MASK; |
||||
if (mode == COMM_DIR_RX) { |
||||
clockBits <<= 4; /* Rx field is 4 bits to left of Tx field */ |
||||
clockMask <<= 4; /* Rx field is 4 bits to left of Tx field */ |
||||
} |
||||
clockBits <<= shift; |
||||
clockMask <<= shift; |
||||
|
||||
out_be32(p_cmxucr, (in_be32(p_cmxucr) & ~clockMask) | clockBits); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static uint ucc_get_reg_baseaddr(int ucc_num) |
||||
{ |
||||
uint base = 0; |
||||
|
||||
/* check if the UCC number is in range */ |
||||
if ((ucc_num > UCC_MAX_NUM - 1) || (ucc_num < 0)) { |
||||
printf("%s: the UCC num not in ranges\n", __FUNCTION__); |
||||
return 0; |
||||
} |
||||
|
||||
switch (ucc_num) { |
||||
case 0: base = 0x00002000; break; |
||||
case 1: base = 0x00003000; break; |
||||
case 2: base = 0x00002200; break; |
||||
case 3: base = 0x00003200; break; |
||||
case 4: base = 0x00002400; break; |
||||
case 5: base = 0x00003400; break; |
||||
case 6: base = 0x00002600; break; |
||||
case 7: base = 0x00003600; break; |
||||
default: break; |
||||
} |
||||
|
||||
base = (uint)qe_immr + base; |
||||
return base; |
||||
} |
||||
|
||||
void ucc_fast_enable(ucc_fast_private_t *uccf, comm_dir_e mode) |
||||
{ |
||||
ucc_fast_t *uf_regs; |
||||
u32 gumr; |
||||
|
||||
uf_regs = uccf->uf_regs; |
||||
|
||||
/* Enable reception and/or transmission on this UCC. */ |
||||
gumr = in_be32(&uf_regs->gumr); |
||||
if (mode & COMM_DIR_TX) { |
||||
gumr |= UCC_FAST_GUMR_ENT; |
||||
uccf->enabled_tx = 1; |
||||
} |
||||
if (mode & COMM_DIR_RX) { |
||||
gumr |= UCC_FAST_GUMR_ENR; |
||||
uccf->enabled_rx = 1; |
||||
} |
||||
out_be32(&uf_regs->gumr, gumr); |
||||
} |
||||
|
||||
void ucc_fast_disable(ucc_fast_private_t *uccf, comm_dir_e mode) |
||||
{ |
||||
ucc_fast_t *uf_regs; |
||||
u32 gumr; |
||||
|
||||
uf_regs = uccf->uf_regs; |
||||
|
||||
/* Disable reception and/or transmission on this UCC. */ |
||||
gumr = in_be32(&uf_regs->gumr); |
||||
if (mode & COMM_DIR_TX) { |
||||
gumr &= ~UCC_FAST_GUMR_ENT; |
||||
uccf->enabled_tx = 0; |
||||
} |
||||
if (mode & COMM_DIR_RX) { |
||||
gumr &= ~UCC_FAST_GUMR_ENR; |
||||
uccf->enabled_rx = 0; |
||||
} |
||||
out_be32(&uf_regs->gumr, gumr); |
||||
} |
||||
|
||||
int ucc_fast_init(ucc_fast_info_t *uf_info, ucc_fast_private_t **uccf_ret) |
||||
{ |
||||
ucc_fast_private_t *uccf; |
||||
ucc_fast_t *uf_regs; |
||||
|
||||
if (!uf_info) |
||||
return -EINVAL; |
||||
|
||||
if ((uf_info->ucc_num < 0) || (uf_info->ucc_num > UCC_MAX_NUM - 1)) { |
||||
printf("%s: Illagal UCC number!\n", __FUNCTION__); |
||||
return -EINVAL; |
||||
} |
||||
|
||||
uccf = (ucc_fast_private_t *)malloc(sizeof(ucc_fast_private_t)); |
||||
if (!uccf) { |
||||
printf("%s: No memory for UCC fast data structure!\n", |
||||
__FUNCTION__); |
||||
return -ENOMEM; |
||||
} |
||||
memset(uccf, 0, sizeof(ucc_fast_private_t)); |
||||
|
||||
/* Save fast UCC structure */ |
||||
uccf->uf_info = uf_info; |
||||
uccf->uf_regs = (ucc_fast_t *)ucc_get_reg_baseaddr(uf_info->ucc_num); |
||||
|
||||
if (uccf->uf_regs == NULL) { |
||||
printf("%s: No memory map for UCC fast controller!\n", |
||||
__FUNCTION__); |
||||
return -ENOMEM; |
||||
} |
||||
|
||||
uccf->enabled_tx = 0; |
||||
uccf->enabled_rx = 0; |
||||
|
||||
uf_regs = uccf->uf_regs; |
||||
uccf->p_ucce = (u32 *) &(uf_regs->ucce); |
||||
uccf->p_uccm = (u32 *) &(uf_regs->uccm); |
||||
|
||||
/* Init GUEMR register, UCC both Rx and Tx is Fast protocol */ |
||||
out_8(&uf_regs->guemr, UCC_GUEMR_SET_RESERVED3 | UCC_GUEMR_MODE_FAST_RX |
||||
| UCC_GUEMR_MODE_FAST_TX); |
||||
|
||||
/* Set GUMR, disable UCC both Rx and Tx, Ethernet protocol */ |
||||
out_be32(&uf_regs->gumr, UCC_FAST_GUMR_ETH); |
||||
|
||||
/* Set the Giga ethernet VFIFO stuff */ |
||||
if (uf_info->eth_type == GIGA_ETH) { |
||||
/* Allocate memory for Tx Virtual Fifo */ |
||||
uccf->ucc_fast_tx_virtual_fifo_base_offset = |
||||
qe_muram_alloc(UCC_GETH_UTFS_GIGA_INIT, |
||||
UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT); |
||||
|
||||
/* Allocate memory for Rx Virtual Fifo */ |
||||
uccf->ucc_fast_rx_virtual_fifo_base_offset = |
||||
qe_muram_alloc(UCC_GETH_URFS_GIGA_INIT + |
||||
UCC_FAST_RX_VIRTUAL_FIFO_SIZE_PAD, |
||||
UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT); |
||||
|
||||
/* utfb, urfb are offsets from MURAM base */ |
||||
out_be32(&uf_regs->utfb, |
||||
uccf->ucc_fast_tx_virtual_fifo_base_offset); |
||||
out_be32(&uf_regs->urfb, |
||||
uccf->ucc_fast_rx_virtual_fifo_base_offset); |
||||
|
||||
/* Set Virtual Fifo registers */ |
||||
out_be16(&uf_regs->urfs, UCC_GETH_URFS_GIGA_INIT); |
||||
out_be16(&uf_regs->urfet, UCC_GETH_URFET_GIGA_INIT); |
||||
out_be16(&uf_regs->urfset, UCC_GETH_URFSET_GIGA_INIT); |
||||
out_be16(&uf_regs->utfs, UCC_GETH_UTFS_GIGA_INIT); |
||||
out_be16(&uf_regs->utfet, UCC_GETH_UTFET_GIGA_INIT); |
||||
out_be16(&uf_regs->utftt, UCC_GETH_UTFTT_GIGA_INIT); |
||||
} |
||||
|
||||
/* Set the Fast ethernet VFIFO stuff */ |
||||
if (uf_info->eth_type == FAST_ETH) { |
||||
/* Allocate memory for Tx Virtual Fifo */ |
||||
uccf->ucc_fast_tx_virtual_fifo_base_offset = |
||||
qe_muram_alloc(UCC_GETH_UTFS_INIT, |
||||
UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT); |
||||
|
||||
/* Allocate memory for Rx Virtual Fifo */ |
||||
uccf->ucc_fast_rx_virtual_fifo_base_offset = |
||||
qe_muram_alloc(UCC_GETH_URFS_INIT + |
||||
UCC_FAST_RX_VIRTUAL_FIFO_SIZE_PAD, |
||||
UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT); |
||||
|
||||
/* utfb, urfb are offsets from MURAM base */ |
||||
out_be32(&uf_regs->utfb, |
||||
uccf->ucc_fast_tx_virtual_fifo_base_offset); |
||||
out_be32(&uf_regs->urfb, |
||||
uccf->ucc_fast_rx_virtual_fifo_base_offset); |
||||
|
||||
/* Set Virtual Fifo registers */ |
||||
out_be16(&uf_regs->urfs, UCC_GETH_URFS_INIT); |
||||
out_be16(&uf_regs->urfet, UCC_GETH_URFET_INIT); |
||||
out_be16(&uf_regs->urfset, UCC_GETH_URFSET_INIT); |
||||
out_be16(&uf_regs->utfs, UCC_GETH_UTFS_INIT); |
||||
out_be16(&uf_regs->utfet, UCC_GETH_UTFET_INIT); |
||||
out_be16(&uf_regs->utftt, UCC_GETH_UTFTT_INIT); |
||||
} |
||||
|
||||
/* Rx clock routing */ |
||||
if (uf_info->rx_clock != QE_CLK_NONE) { |
||||
if (ucc_set_clk_src(uf_info->ucc_num, |
||||
uf_info->rx_clock, COMM_DIR_RX)) { |
||||
printf("%s: Illegal value for parameter 'RxClock'.\n", |
||||
__FUNCTION__); |
||||
return -EINVAL; |
||||
} |
||||
} |
||||
|
||||
/* Tx clock routing */ |
||||
if (uf_info->tx_clock != QE_CLK_NONE) { |
||||
if (ucc_set_clk_src(uf_info->ucc_num, |
||||
uf_info->tx_clock, COMM_DIR_TX)) { |
||||
printf("%s: Illegal value for parameter 'TxClock'.\n", |
||||
__FUNCTION__); |
||||
return -EINVAL; |
||||
} |
||||
} |
||||
|
||||
/* Clear interrupt mask register to disable all of interrupts */ |
||||
out_be32(&uf_regs->uccm, 0x0); |
||||
|
||||
/* Writing '1' to clear all of envents */ |
||||
out_be32(&uf_regs->ucce, 0xffffffff); |
||||
|
||||
*uccf_ret = uccf; |
||||
return 0; |
||||
} |
||||
#endif /* CONFIG_QE */ |
||||
@ -0,0 +1,130 @@ |
||||
/*
|
||||
* Copyright (C) 2006 Freescale Semiconductor, Inc. |
||||
* |
||||
* Dave Liu <daveliu@freescale.com> |
||||
* based on source code of Shlomi Gridish |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __UCCF_H__ |
||||
#define __UCCF_H__ |
||||
|
||||
#include "common.h" |
||||
#include "qe.h" |
||||
|
||||
/* Fast or Giga ethernet
|
||||
*/ |
||||
typedef enum enet_type { |
||||
FAST_ETH, |
||||
GIGA_ETH, |
||||
} enet_type_e; |
||||
|
||||
/* General UCC Extended Mode Register
|
||||
*/ |
||||
#define UCC_GUEMR_MODE_MASK_RX 0x02 |
||||
#define UCC_GUEMR_MODE_MASK_TX 0x01 |
||||
#define UCC_GUEMR_MODE_FAST_RX 0x02 |
||||
#define UCC_GUEMR_MODE_FAST_TX 0x01 |
||||
#define UCC_GUEMR_MODE_SLOW_RX 0x00 |
||||
#define UCC_GUEMR_MODE_SLOW_TX 0x00 |
||||
#define UCC_GUEMR_SET_RESERVED3 0x10 /* Bit 3 must be set 1 */ |
||||
|
||||
/* General UCC FAST Mode Register
|
||||
*/ |
||||
#define UCC_FAST_GUMR_TCI 0x20000000 |
||||
#define UCC_FAST_GUMR_TRX 0x10000000 |
||||
#define UCC_FAST_GUMR_TTX 0x08000000 |
||||
#define UCC_FAST_GUMR_CDP 0x04000000 |
||||
#define UCC_FAST_GUMR_CTSP 0x02000000 |
||||
#define UCC_FAST_GUMR_CDS 0x01000000 |
||||
#define UCC_FAST_GUMR_CTSS 0x00800000 |
||||
#define UCC_FAST_GUMR_TXSY 0x00020000 |
||||
#define UCC_FAST_GUMR_RSYN 0x00010000 |
||||
#define UCC_FAST_GUMR_RTSM 0x00002000 |
||||
#define UCC_FAST_GUMR_REVD 0x00000400 |
||||
#define UCC_FAST_GUMR_ENR 0x00000020 |
||||
#define UCC_FAST_GUMR_ENT 0x00000010 |
||||
|
||||
/* GUMR [MODE] bit maps
|
||||
*/ |
||||
#define UCC_FAST_GUMR_HDLC 0x00000000 |
||||
#define UCC_FAST_GUMR_QMC 0x00000002 |
||||
#define UCC_FAST_GUMR_UART 0x00000004 |
||||
#define UCC_FAST_GUMR_BISYNC 0x00000008 |
||||
#define UCC_FAST_GUMR_ATM 0x0000000a |
||||
#define UCC_FAST_GUMR_ETH 0x0000000c |
||||
|
||||
/* Transmit On Demand (UTORD)
|
||||
*/ |
||||
#define UCC_SLOW_TOD 0x8000 |
||||
#define UCC_FAST_TOD 0x8000 |
||||
|
||||
/* Fast Ethernet (10/100 Mbps)
|
||||
*/ |
||||
#define UCC_GETH_URFS_INIT 512 /* Rx virtual FIFO size */ |
||||
#define UCC_GETH_URFET_INIT 256 /* 1/2 urfs */ |
||||
#define UCC_GETH_URFSET_INIT 384 /* 3/4 urfs */ |
||||
#define UCC_GETH_UTFS_INIT 512 /* Tx virtual FIFO size */ |
||||
#define UCC_GETH_UTFET_INIT 256 /* 1/2 utfs */ |
||||
#define UCC_GETH_UTFTT_INIT 128 |
||||
|
||||
/* Gigabit Ethernet (1000 Mbps)
|
||||
*/ |
||||
#define UCC_GETH_URFS_GIGA_INIT 4096/*2048*/ /* Rx virtual FIFO size */ |
||||
#define UCC_GETH_URFET_GIGA_INIT 2048/*1024*/ /* 1/2 urfs */ |
||||
#define UCC_GETH_URFSET_GIGA_INIT 3072/*1536*/ /* 3/4 urfs */ |
||||
#define UCC_GETH_UTFS_GIGA_INIT 8192/*2048*/ /* Tx virtual FIFO size */ |
||||
#define UCC_GETH_UTFET_GIGA_INIT 4096/*1024*/ /* 1/2 utfs */ |
||||
#define UCC_GETH_UTFTT_GIGA_INIT 0x400/*0x40*/ /* */ |
||||
|
||||
/* UCC fast alignment
|
||||
*/ |
||||
#define UCC_FAST_RX_ALIGN 4 |
||||
#define UCC_FAST_MRBLR_ALIGNMENT 4 |
||||
#define UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT 8 |
||||
|
||||
/* Sizes
|
||||
*/ |
||||
#define UCC_FAST_RX_VIRTUAL_FIFO_SIZE_PAD 8 |
||||
|
||||
/* UCC fast structure.
|
||||
*/ |
||||
typedef struct ucc_fast_info { |
||||
int ucc_num; |
||||
qe_clock_e rx_clock; |
||||
qe_clock_e tx_clock; |
||||
enet_type_e eth_type; |
||||
} ucc_fast_info_t; |
||||
|
||||
typedef struct ucc_fast_private { |
||||
ucc_fast_info_t *uf_info; |
||||
ucc_fast_t *uf_regs; /* a pointer to memory map of UCC regs */ |
||||
u32 *p_ucce; /* a pointer to the event register */ |
||||
u32 *p_uccm; /* a pointer to the mask register */ |
||||
int enabled_tx; /* whether UCC is enabled for Tx (ENT) */ |
||||
int enabled_rx; /* whether UCC is enabled for Rx (ENR) */ |
||||
u32 ucc_fast_tx_virtual_fifo_base_offset; |
||||
u32 ucc_fast_rx_virtual_fifo_base_offset; |
||||
} ucc_fast_private_t; |
||||
|
||||
void ucc_fast_transmit_on_demand(ucc_fast_private_t *uccf); |
||||
u32 ucc_fast_get_qe_cr_subblock(int ucc_num); |
||||
void ucc_fast_enable(ucc_fast_private_t *uccf, comm_dir_e mode); |
||||
void ucc_fast_disable(ucc_fast_private_t *uccf, comm_dir_e mode); |
||||
int ucc_fast_init(ucc_fast_info_t *uf_info, ucc_fast_private_t **uccf_ret); |
||||
|
||||
#endif /* __UCCF_H__ */ |
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,716 @@ |
||||
/*
|
||||
* Copyright (C) 2006 Freescale Semiconductor, Inc. |
||||
* |
||||
* Dave Liu <daveliu@freescale.com> |
||||
* based on source code of Shlomi Gridish |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __UEC_H__ |
||||
#define __UEC_H__ |
||||
|
||||
#define MAX_TX_THREADS 8 |
||||
#define MAX_RX_THREADS 8 |
||||
#define MAX_TX_QUEUES 8 |
||||
#define MAX_RX_QUEUES 8 |
||||
#define MAX_PREFETCHED_BDS 4 |
||||
#define MAX_IPH_OFFSET_ENTRY 8 |
||||
#define MAX_ENET_INIT_PARAM_ENTRIES_RX 9 |
||||
#define MAX_ENET_INIT_PARAM_ENTRIES_TX 8 |
||||
|
||||
/* UEC UPSMR (Protocol Specific Mode Register)
|
||||
*/ |
||||
#define UPSMR_ECM 0x04000000 /* Enable CAM Miss */ |
||||
#define UPSMR_HSE 0x02000000 /* Hardware Statistics Enable */ |
||||
#define UPSMR_PRO 0x00400000 /* Promiscuous */ |
||||
#define UPSMR_CAP 0x00200000 /* CAM polarity */ |
||||
#define UPSMR_RSH 0x00100000 /* Receive Short Frames */ |
||||
#define UPSMR_RPM 0x00080000 /* Reduced Pin Mode interfaces */ |
||||
#define UPSMR_R10M 0x00040000 /* RGMII/RMII 10 Mode */ |
||||
#define UPSMR_RLPB 0x00020000 /* RMII Loopback Mode */ |
||||
#define UPSMR_TBIM 0x00010000 /* Ten-bit Interface Mode */ |
||||
#define UPSMR_RMM 0x00001000 /* RMII/RGMII Mode */ |
||||
#define UPSMR_CAM 0x00000400 /* CAM Address Matching */ |
||||
#define UPSMR_BRO 0x00000200 /* Broadcast Address */ |
||||
#define UPSMR_RES1 0x00002000 /* Reserved feild - must be 1 */ |
||||
|
||||
#define UPSMR_INIT_VALUE (UPSMR_HSE | UPSMR_RES1) |
||||
|
||||
/* UEC MACCFG1 (MAC Configuration 1 Register)
|
||||
*/ |
||||
#define MACCFG1_FLOW_RX 0x00000020 /* Flow Control Rx */ |
||||
#define MACCFG1_FLOW_TX 0x00000010 /* Flow Control Tx */ |
||||
#define MACCFG1_ENABLE_SYNCHED_RX 0x00000008 /* Enable Rx Sync */ |
||||
#define MACCFG1_ENABLE_RX 0x00000004 /* Enable Rx */ |
||||
#define MACCFG1_ENABLE_SYNCHED_TX 0x00000002 /* Enable Tx Sync */ |
||||
#define MACCFG1_ENABLE_TX 0x00000001 /* Enable Tx */ |
||||
|
||||
#define MACCFG1_INIT_VALUE (0) |
||||
|
||||
/* UEC MACCFG2 (MAC Configuration 2 Register)
|
||||
*/ |
||||
#define MACCFG2_PREL 0x00007000 |
||||
#define MACCFG2_PREL_SHIFT (31 - 19) |
||||
#define MACCFG2_PREL_MASK 0x0000f000 |
||||
#define MACCFG2_SRP 0x00000080 |
||||
#define MACCFG2_STP 0x00000040 |
||||
#define MACCFG2_RESERVED_1 0x00000020 /* must be set */ |
||||
#define MACCFG2_LC 0x00000010 /* Length Check */ |
||||
#define MACCFG2_MPE 0x00000008 |
||||
#define MACCFG2_FDX 0x00000001 /* Full Duplex */ |
||||
#define MACCFG2_FDX_MASK 0x00000001 |
||||
#define MACCFG2_PAD_CRC 0x00000004 |
||||
#define MACCFG2_CRC_EN 0x00000002 |
||||
#define MACCFG2_PAD_AND_CRC_MODE_NONE 0x00000000 |
||||
#define MACCFG2_PAD_AND_CRC_MODE_CRC_ONLY 0x00000002 |
||||
#define MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC 0x00000004 |
||||
#define MACCFG2_INTERFACE_MODE_NIBBLE 0x00000100 |
||||
#define MACCFG2_INTERFACE_MODE_BYTE 0x00000200 |
||||
#define MACCFG2_INTERFACE_MODE_MASK 0x00000300 |
||||
|
||||
#define MACCFG2_INIT_VALUE (MACCFG2_PREL | MACCFG2_RESERVED_1 | \ |
||||
MACCFG2_LC | MACCFG2_PAD_CRC | MACCFG2_FDX) |
||||
|
||||
/* UEC Event Register
|
||||
*/ |
||||
#define UCCE_MPD 0x80000000 |
||||
#define UCCE_SCAR 0x40000000 |
||||
#define UCCE_GRA 0x20000000 |
||||
#define UCCE_CBPR 0x10000000 |
||||
#define UCCE_BSY 0x08000000 |
||||
#define UCCE_RXC 0x04000000 |
||||
#define UCCE_TXC 0x02000000 |
||||
#define UCCE_TXE 0x01000000 |
||||
#define UCCE_TXB7 0x00800000 |
||||
#define UCCE_TXB6 0x00400000 |
||||
#define UCCE_TXB5 0x00200000 |
||||
#define UCCE_TXB4 0x00100000 |
||||
#define UCCE_TXB3 0x00080000 |
||||
#define UCCE_TXB2 0x00040000 |
||||
#define UCCE_TXB1 0x00020000 |
||||
#define UCCE_TXB0 0x00010000 |
||||
#define UCCE_RXB7 0x00008000 |
||||
#define UCCE_RXB6 0x00004000 |
||||
#define UCCE_RXB5 0x00002000 |
||||
#define UCCE_RXB4 0x00001000 |
||||
#define UCCE_RXB3 0x00000800 |
||||
#define UCCE_RXB2 0x00000400 |
||||
#define UCCE_RXB1 0x00000200 |
||||
#define UCCE_RXB0 0x00000100 |
||||
#define UCCE_RXF7 0x00000080 |
||||
#define UCCE_RXF6 0x00000040 |
||||
#define UCCE_RXF5 0x00000020 |
||||
#define UCCE_RXF4 0x00000010 |
||||
#define UCCE_RXF3 0x00000008 |
||||
#define UCCE_RXF2 0x00000004 |
||||
#define UCCE_RXF1 0x00000002 |
||||
#define UCCE_RXF0 0x00000001 |
||||
|
||||
#define UCCE_TXB (UCCE_TXB7 | UCCE_TXB6 | UCCE_TXB5 | UCCE_TXB4 | \ |
||||
UCCE_TXB3 | UCCE_TXB2 | UCCE_TXB1 | UCCE_TXB0) |
||||
#define UCCE_RXB (UCCE_RXB7 | UCCE_RXB6 | UCCE_RXB5 | UCCE_RXB4 | \ |
||||
UCCE_RXB3 | UCCE_RXB2 | UCCE_RXB1 | UCCE_RXB0) |
||||
#define UCCE_RXF (UCCE_RXF7 | UCCE_RXF6 | UCCE_RXF5 | UCCE_RXF4 | \ |
||||
UCCE_RXF3 | UCCE_RXF2 | UCCE_RXF1 | UCCE_RXF0) |
||||
#define UCCE_OTHER (UCCE_SCAR | UCCE_GRA | UCCE_CBPR | UCCE_BSY | \ |
||||
UCCE_RXC | UCCE_TXC | UCCE_TXE) |
||||
|
||||
/* UEC TEMODR Register
|
||||
*/ |
||||
#define TEMODER_SCHEDULER_ENABLE 0x2000 |
||||
#define TEMODER_IP_CHECKSUM_GENERATE 0x0400 |
||||
#define TEMODER_PERFORMANCE_OPTIMIZATION_MODE1 0x0200 |
||||
#define TEMODER_RMON_STATISTICS 0x0100 |
||||
#define TEMODER_NUM_OF_QUEUES_SHIFT (15-15) |
||||
|
||||
#define TEMODER_INIT_VALUE 0xc000 |
||||
|
||||
/* UEC REMODR Register
|
||||
*/ |
||||
#define REMODER_RX_RMON_STATISTICS_ENABLE 0x00001000 |
||||
#define REMODER_RX_EXTENDED_FEATURES 0x80000000 |
||||
#define REMODER_VLAN_OPERATION_TAGGED_SHIFT (31-9 ) |
||||
#define REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT (31-10) |
||||
#define REMODER_RX_QOS_MODE_SHIFT (31-15) |
||||
#define REMODER_RMON_STATISTICS 0x00001000 |
||||
#define REMODER_RX_EXTENDED_FILTERING 0x00000800 |
||||
#define REMODER_NUM_OF_QUEUES_SHIFT (31-23) |
||||
#define REMODER_DYNAMIC_MAX_FRAME_LENGTH 0x00000008 |
||||
#define REMODER_DYNAMIC_MIN_FRAME_LENGTH 0x00000004 |
||||
#define REMODER_IP_CHECKSUM_CHECK 0x00000002 |
||||
#define REMODER_IP_ADDRESS_ALIGNMENT 0x00000001 |
||||
|
||||
#define REMODER_INIT_VALUE 0 |
||||
|
||||
/* BMRx - Bus Mode Register */ |
||||
#define BMR_GLB 0x20 |
||||
#define BMR_BO_BE 0x10 |
||||
#define BMR_DTB_SECONDARY_BUS 0x02 |
||||
#define BMR_BDB_SECONDARY_BUS 0x01 |
||||
|
||||
#define BMR_SHIFT 24 |
||||
#define BMR_INIT_VALUE (BMR_GLB | BMR_BO_BE) |
||||
|
||||
/* UEC UCCS (Ethernet Status Register)
|
||||
*/ |
||||
#define UCCS_BPR 0x02 |
||||
#define UCCS_PAU 0x02 |
||||
#define UCCS_MPD 0x01 |
||||
|
||||
/* UEC MIIMCFG (MII Management Configuration Register)
|
||||
*/ |
||||
#define MIIMCFG_RESET_MANAGEMENT 0x80000000 |
||||
#define MIIMCFG_NO_PREAMBLE 0x00000010 |
||||
#define MIIMCFG_CLOCK_DIVIDE_SHIFT (31 - 31) |
||||
#define MIIMCFG_CLOCK_DIVIDE_MASK 0x0000000f |
||||
#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_4 0x00000001 |
||||
#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_6 0x00000002 |
||||
#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_8 0x00000003 |
||||
#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_10 0x00000004 |
||||
#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_14 0x00000005 |
||||
#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_20 0x00000006 |
||||
#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_28 0x00000007 |
||||
|
||||
#define MIIMCFG_MNGMNT_CLC_DIV_INIT_VALUE \ |
||||
MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_10 |
||||
|
||||
/* UEC MIIMCOM (MII Management Command Register)
|
||||
*/ |
||||
#define MIIMCOM_SCAN_CYCLE 0x00000002 /* Scan cycle */ |
||||
#define MIIMCOM_READ_CYCLE 0x00000001 /* Read cycle */ |
||||
|
||||
/* UEC MIIMADD (MII Management Address Register)
|
||||
*/ |
||||
#define MIIMADD_PHY_ADDRESS_SHIFT (31 - 23) |
||||
#define MIIMADD_PHY_REGISTER_SHIFT (31 - 31) |
||||
|
||||
/* UEC MIIMCON (MII Management Control Register)
|
||||
*/ |
||||
#define MIIMCON_PHY_CONTROL_SHIFT (31 - 31) |
||||
#define MIIMCON_PHY_STATUS_SHIFT (31 - 31) |
||||
|
||||
/* UEC MIIMIND (MII Management Indicator Register)
|
||||
*/ |
||||
#define MIIMIND_NOT_VALID 0x00000004 |
||||
#define MIIMIND_SCAN 0x00000002 |
||||
#define MIIMIND_BUSY 0x00000001 |
||||
|
||||
/* UEC UTBIPAR (Ten Bit Interface Physical Address Register)
|
||||
*/ |
||||
#define UTBIPAR_PHY_ADDRESS_SHIFT (31 - 31) |
||||
#define UTBIPAR_PHY_ADDRESS_MASK 0x0000001f |
||||
|
||||
/* UEC UESCR (Ethernet Statistics Control Register)
|
||||
*/ |
||||
#define UESCR_AUTOZ 0x8000 |
||||
#define UESCR_CLRCNT 0x4000 |
||||
#define UESCR_MAXCOV_SHIFT (15 - 7) |
||||
#define UESCR_SCOV_SHIFT (15 - 15) |
||||
|
||||
/****** Tx data struct collection ******/ |
||||
/* Tx thread data, each Tx thread has one this struct.
|
||||
*/ |
||||
typedef struct uec_thread_data_tx { |
||||
u8 res0[136]; |
||||
} __attribute__ ((packed)) uec_thread_data_tx_t; |
||||
|
||||
/* Tx thread parameter, each Tx thread has one this struct.
|
||||
*/ |
||||
typedef struct uec_thread_tx_pram { |
||||
u8 res0[64]; |
||||
} __attribute__ ((packed)) uec_thread_tx_pram_t; |
||||
|
||||
/* Send queue queue-descriptor, each Tx queue has one this QD
|
||||
*/ |
||||
typedef struct uec_send_queue_qd { |
||||
u32 bd_ring_base; /* pointer to BD ring base address */ |
||||
u8 res0[0x8]; |
||||
u32 last_bd_completed_address; /* last entry in BD ring */ |
||||
u8 res1[0x30]; |
||||
} __attribute__ ((packed)) uec_send_queue_qd_t; |
||||
|
||||
/* Send queue memory region */ |
||||
typedef struct uec_send_queue_mem_region { |
||||
uec_send_queue_qd_t sqqd[MAX_TX_QUEUES]; |
||||
} __attribute__ ((packed)) uec_send_queue_mem_region_t; |
||||
|
||||
/* Scheduler struct
|
||||
*/ |
||||
typedef struct uec_scheduler { |
||||
u16 cpucount0; /* CPU packet counter */ |
||||
u16 cpucount1; /* CPU packet counter */ |
||||
u16 cecount0; /* QE packet counter */ |
||||
u16 cecount1; /* QE packet counter */ |
||||
u16 cpucount2; /* CPU packet counter */ |
||||
u16 cpucount3; /* CPU packet counter */ |
||||
u16 cecount2; /* QE packet counter */ |
||||
u16 cecount3; /* QE packet counter */ |
||||
u16 cpucount4; /* CPU packet counter */ |
||||
u16 cpucount5; /* CPU packet counter */ |
||||
u16 cecount4; /* QE packet counter */ |
||||
u16 cecount5; /* QE packet counter */ |
||||
u16 cpucount6; /* CPU packet counter */ |
||||
u16 cpucount7; /* CPU packet counter */ |
||||
u16 cecount6; /* QE packet counter */ |
||||
u16 cecount7; /* QE packet counter */ |
||||
u32 weightstatus[MAX_TX_QUEUES]; /* accumulated weight factor */ |
||||
u32 rtsrshadow; /* temporary variable handled by QE */ |
||||
u32 time; /* temporary variable handled by QE */ |
||||
u32 ttl; /* temporary variable handled by QE */ |
||||
u32 mblinterval; /* max burst length interval */ |
||||
u16 nortsrbytetime; /* normalized value of byte time in tsr units */ |
||||
u8 fracsiz; |
||||
u8 res0[1]; |
||||
u8 strictpriorityq; /* Strict Priority Mask register */ |
||||
u8 txasap; /* Transmit ASAP register */ |
||||
u8 extrabw; /* Extra BandWidth register */ |
||||
u8 oldwfqmask; /* temporary variable handled by QE */ |
||||
u8 weightfactor[MAX_TX_QUEUES]; /**< weight factor for queues */ |
||||
u32 minw; /* temporary variable handled by QE */ |
||||
u8 res1[0x70-0x64]; |
||||
} __attribute__ ((packed)) uec_scheduler_t; |
||||
|
||||
/* Tx firmware counters
|
||||
*/ |
||||
typedef struct uec_tx_firmware_statistics_pram { |
||||
u32 sicoltx; /* single collision */ |
||||
u32 mulcoltx; /* multiple collision */ |
||||
u32 latecoltxfr; /* late collision */ |
||||
u32 frabortduecol; /* frames aborted due to tx collision */ |
||||
u32 frlostinmactxer; /* frames lost due to internal MAC error tx */ |
||||
u32 carriersenseertx; /* carrier sense error */ |
||||
u32 frtxok; /* frames transmitted OK */ |
||||
u32 txfrexcessivedefer; |
||||
u32 txpkts256; /* total packets(including bad) 256~511 B */ |
||||
u32 txpkts512; /* total packets(including bad) 512~1023B */ |
||||
u32 txpkts1024; /* total packets(including bad) 1024~1518B */ |
||||
u32 txpktsjumbo; /* total packets(including bad) >1024 */ |
||||
} __attribute__ ((packed)) uec_tx_firmware_statistics_pram_t; |
||||
|
||||
/* Tx global parameter table
|
||||
*/ |
||||
typedef struct uec_tx_global_pram { |
||||
u16 temoder; |
||||
u8 res0[0x38-0x02]; |
||||
u32 sqptr; |
||||
u32 schedulerbasepointer; |
||||
u32 txrmonbaseptr; |
||||
u32 tstate; |
||||
u8 iphoffset[MAX_IPH_OFFSET_ENTRY]; |
||||
u32 vtagtable[0x8]; |
||||
u32 tqptr; |
||||
u8 res2[0x80-0x74]; |
||||
} __attribute__ ((packed)) uec_tx_global_pram_t; |
||||
|
||||
|
||||
/****** Rx data struct collection ******/ |
||||
/* Rx thread data, each Rx thread has one this struct.
|
||||
*/ |
||||
typedef struct uec_thread_data_rx { |
||||
u8 res0[40]; |
||||
} __attribute__ ((packed)) uec_thread_data_rx_t; |
||||
|
||||
/* Rx thread parameter, each Rx thread has one this struct.
|
||||
*/ |
||||
typedef struct uec_thread_rx_pram { |
||||
u8 res0[128]; |
||||
} __attribute__ ((packed)) uec_thread_rx_pram_t; |
||||
|
||||
/* Rx firmware counters
|
||||
*/ |
||||
typedef struct uec_rx_firmware_statistics_pram { |
||||
u32 frrxfcser; /* frames with crc error */ |
||||
u32 fraligner; /* frames with alignment error */ |
||||
u32 inrangelenrxer; /* in range length error */ |
||||
u32 outrangelenrxer; /* out of range length error */ |
||||
u32 frtoolong; /* frame too long */ |
||||
u32 runt; /* runt */ |
||||
u32 verylongevent; /* very long event */ |
||||
u32 symbolerror; /* symbol error */ |
||||
u32 dropbsy; /* drop because of BD not ready */ |
||||
u8 res0[0x8]; |
||||
u32 mismatchdrop; /* drop because of MAC filtering */ |
||||
u32 underpkts; /* total frames less than 64 octets */ |
||||
u32 pkts256; /* total frames(including bad)256~511 B */ |
||||
u32 pkts512; /* total frames(including bad)512~1023 B */ |
||||
u32 pkts1024; /* total frames(including bad)1024~1518 B */ |
||||
u32 pktsjumbo; /* total frames(including bad) >1024 B */ |
||||
u32 frlossinmacer; |
||||
u32 pausefr; /* pause frames */ |
||||
u8 res1[0x4]; |
||||
u32 removevlan; |
||||
u32 replacevlan; |
||||
u32 insertvlan; |
||||
} __attribute__ ((packed)) uec_rx_firmware_statistics_pram_t; |
||||
|
||||
/* Rx interrupt coalescing entry, each Rx queue has one this entry.
|
||||
*/ |
||||
typedef struct uec_rx_interrupt_coalescing_entry { |
||||
u32 maxvalue; |
||||
u32 counter; |
||||
} __attribute__ ((packed)) uec_rx_interrupt_coalescing_entry_t; |
||||
|
||||
typedef struct uec_rx_interrupt_coalescing_table { |
||||
uec_rx_interrupt_coalescing_entry_t entry[MAX_RX_QUEUES]; |
||||
} __attribute__ ((packed)) uec_rx_interrupt_coalescing_table_t; |
||||
|
||||
/* RxBD queue entry, each Rx queue has one this entry.
|
||||
*/ |
||||
typedef struct uec_rx_bd_queues_entry { |
||||
u32 bdbaseptr; /* BD base pointer */ |
||||
u32 bdptr; /* BD pointer */ |
||||
u32 externalbdbaseptr; /* external BD base pointer */ |
||||
u32 externalbdptr; /* external BD pointer */ |
||||
} __attribute__ ((packed)) uec_rx_bd_queues_entry_t; |
||||
|
||||
/* Rx global paramter table
|
||||
*/ |
||||
typedef struct uec_rx_global_pram { |
||||
u32 remoder; /* ethernet mode reg. */ |
||||
u32 rqptr; /* base pointer to the Rx Queues */ |
||||
u32 res0[0x1]; |
||||
u8 res1[0x20-0xC]; |
||||
u16 typeorlen; |
||||
u8 res2[0x1]; |
||||
u8 rxgstpack; /* ack on GRACEFUL STOP RX command */ |
||||
u32 rxrmonbaseptr; /* Rx RMON statistics base */ |
||||
u8 res3[0x30-0x28]; |
||||
u32 intcoalescingptr; /* Interrupt coalescing table pointer */ |
||||
u8 res4[0x36-0x34]; |
||||
u8 rstate; |
||||
u8 res5[0x46-0x37]; |
||||
u16 mrblr; /* max receive buffer length reg. */ |
||||
u32 rbdqptr; /* RxBD parameter table description */ |
||||
u16 mflr; /* max frame length reg. */ |
||||
u16 minflr; /* min frame length reg. */ |
||||
u16 maxd1; /* max dma1 length reg. */ |
||||
u16 maxd2; /* max dma2 length reg. */ |
||||
u32 ecamptr; /* external CAM address */ |
||||
u32 l2qt; /* VLAN priority mapping table. */ |
||||
u32 l3qt[0x8]; /* IP priority mapping table. */ |
||||
u16 vlantype; /* vlan type */ |
||||
u16 vlantci; /* default vlan tci */ |
||||
u8 addressfiltering[64];/* address filtering data structure */ |
||||
u32 exfGlobalParam; /* extended filtering global parameters */ |
||||
u8 res6[0x100-0xC4]; /* Initialize to zero */ |
||||
} __attribute__ ((packed)) uec_rx_global_pram_t; |
||||
|
||||
#define GRACEFUL_STOP_ACKNOWLEDGE_RX 0x01 |
||||
|
||||
|
||||
/****** UEC common ******/ |
||||
/* UCC statistics - hardware counters
|
||||
*/ |
||||
typedef struct uec_hardware_statistics { |
||||
u32 tx64; |
||||
u32 tx127; |
||||
u32 tx255; |
||||
u32 rx64; |
||||
u32 rx127; |
||||
u32 rx255; |
||||
u32 txok; |
||||
u16 txcf; |
||||
u32 tmca; |
||||
u32 tbca; |
||||
u32 rxfok; |
||||
u32 rxbok; |
||||
u32 rbyt; |
||||
u32 rmca; |
||||
u32 rbca; |
||||
} __attribute__ ((packed)) uec_hardware_statistics_t; |
||||
|
||||
/* InitEnet command parameter
|
||||
*/ |
||||
typedef struct uec_init_cmd_pram { |
||||
u8 resinit0; |
||||
u8 resinit1; |
||||
u8 resinit2; |
||||
u8 resinit3; |
||||
u16 resinit4; |
||||
u8 res1[0x1]; |
||||
u8 largestexternallookupkeysize; |
||||
u32 rgftgfrxglobal; |
||||
u32 rxthread[MAX_ENET_INIT_PARAM_ENTRIES_RX]; /* rx threads */ |
||||
u8 res2[0x38 - 0x30]; |
||||
u32 txglobal; /* tx global */ |
||||
u32 txthread[MAX_ENET_INIT_PARAM_ENTRIES_TX]; /* tx threads */ |
||||
u8 res3[0x1]; |
||||
} __attribute__ ((packed)) uec_init_cmd_pram_t; |
||||
|
||||
#define ENET_INIT_PARAM_RGF_SHIFT (32 - 4) |
||||
#define ENET_INIT_PARAM_TGF_SHIFT (32 - 8) |
||||
|
||||
#define ENET_INIT_PARAM_RISC_MASK 0x0000003f |
||||
#define ENET_INIT_PARAM_PTR_MASK 0x00ffffc0 |
||||
#define ENET_INIT_PARAM_SNUM_MASK 0xff000000 |
||||
#define ENET_INIT_PARAM_SNUM_SHIFT 24 |
||||
|
||||
#define ENET_INIT_PARAM_MAGIC_RES_INIT0 0x06 |
||||
#define ENET_INIT_PARAM_MAGIC_RES_INIT1 0x30 |
||||
#define ENET_INIT_PARAM_MAGIC_RES_INIT2 0xff |
||||
#define ENET_INIT_PARAM_MAGIC_RES_INIT3 0x00 |
||||
#define ENET_INIT_PARAM_MAGIC_RES_INIT4 0x0400 |
||||
|
||||
/* structure representing 82xx Address Filtering Enet Address in PRAM
|
||||
*/ |
||||
typedef struct uec_82xx_enet_address { |
||||
u8 res1[0x2]; |
||||
u16 h; /* address (MSB) */ |
||||
u16 m; /* address */ |
||||
u16 l; /* address (LSB) */ |
||||
} __attribute__ ((packed)) uec_82xx_enet_address_t; |
||||
|
||||
/* structure representing 82xx Address Filtering PRAM
|
||||
*/ |
||||
typedef struct uec_82xx_address_filtering_pram { |
||||
u32 iaddr_h; /* individual address filter, high */ |
||||
u32 iaddr_l; /* individual address filter, low */ |
||||
u32 gaddr_h; /* group address filter, high */ |
||||
u32 gaddr_l; /* group address filter, low */ |
||||
uec_82xx_enet_address_t taddr; |
||||
uec_82xx_enet_address_t paddr[4]; |
||||
u8 res0[0x40-0x38]; |
||||
} __attribute__ ((packed)) uec_82xx_address_filtering_pram_t; |
||||
|
||||
/* Buffer Descriptor
|
||||
*/ |
||||
typedef struct buffer_descriptor { |
||||
u16 status; |
||||
u16 len; |
||||
u32 data; |
||||
} __attribute__ ((packed)) qe_bd_t, *p_bd_t; |
||||
|
||||
#define SIZEOFBD sizeof(qe_bd_t) |
||||
|
||||
/* Common BD flags
|
||||
*/ |
||||
#define BD_WRAP 0x2000 |
||||
#define BD_INT 0x1000 |
||||
#define BD_LAST 0x0800 |
||||
#define BD_CLEAN 0x3000 |
||||
|
||||
/* TxBD status flags
|
||||
*/ |
||||
#define TxBD_READY 0x8000 |
||||
#define TxBD_PADCRC 0x4000 |
||||
#define TxBD_WRAP BD_WRAP |
||||
#define TxBD_INT BD_INT |
||||
#define TxBD_LAST BD_LAST |
||||
#define TxBD_TXCRC 0x0400 |
||||
#define TxBD_DEF 0x0200 |
||||
#define TxBD_PP 0x0100 |
||||
#define TxBD_LC 0x0080 |
||||
#define TxBD_RL 0x0040 |
||||
#define TxBD_RC 0x003C |
||||
#define TxBD_UNDERRUN 0x0002 |
||||
#define TxBD_TRUNC 0x0001 |
||||
|
||||
#define TxBD_ERROR (TxBD_UNDERRUN | TxBD_TRUNC) |
||||
|
||||
/* RxBD status flags
|
||||
*/ |
||||
#define RxBD_EMPTY 0x8000 |
||||
#define RxBD_OWNER 0x4000 |
||||
#define RxBD_WRAP BD_WRAP |
||||
#define RxBD_INT BD_INT |
||||
#define RxBD_LAST BD_LAST |
||||
#define RxBD_FIRST 0x0400 |
||||
#define RxBD_CMR 0x0200 |
||||
#define RxBD_MISS 0x0100 |
||||
#define RxBD_BCAST 0x0080 |
||||
#define RxBD_MCAST 0x0040 |
||||
#define RxBD_LG 0x0020 |
||||
#define RxBD_NO 0x0010 |
||||
#define RxBD_SHORT 0x0008 |
||||
#define RxBD_CRCERR 0x0004 |
||||
#define RxBD_OVERRUN 0x0002 |
||||
#define RxBD_IPCH 0x0001 |
||||
|
||||
#define RxBD_ERROR (RxBD_LG | RxBD_NO | RxBD_SHORT | \ |
||||
RxBD_CRCERR | RxBD_OVERRUN) |
||||
|
||||
/* BD access macros
|
||||
*/ |
||||
#define BD_STATUS(_bd) (((p_bd_t)(_bd))->status) |
||||
#define BD_STATUS_SET(_bd, _val) (((p_bd_t)(_bd))->status = _val) |
||||
#define BD_LENGTH(_bd) (((p_bd_t)(_bd))->len) |
||||
#define BD_LENGTH_SET(_bd, _val) (((p_bd_t)(_bd))->len = _val) |
||||
#define BD_DATA_CLEAR(_bd) (((p_bd_t)(_bd))->data = 0) |
||||
#define BD_IS_DATA(_bd) (((p_bd_t)(_bd))->data) |
||||
#define BD_DATA(_bd) ((u8 *)(((p_bd_t)(_bd))->data)) |
||||
#define BD_DATA_SET(_bd, _data) (((p_bd_t)(_bd))->data = (u32)(_data)) |
||||
#define BD_ADVANCE(_bd,_status,_base) \ |
||||
(((_status) & BD_WRAP) ? (_bd) = ((p_bd_t)(_base)) : ++(_bd)) |
||||
|
||||
/* Rx Prefetched BDs
|
||||
*/ |
||||
typedef struct uec_rx_prefetched_bds { |
||||
qe_bd_t bd[MAX_PREFETCHED_BDS]; /* prefetched bd */ |
||||
} __attribute__ ((packed)) uec_rx_prefetched_bds_t; |
||||
|
||||
/* Alignments
|
||||
*/ |
||||
#define UEC_RX_GLOBAL_PRAM_ALIGNMENT 64 |
||||
#define UEC_TX_GLOBAL_PRAM_ALIGNMENT 64 |
||||
#define UEC_THREAD_RX_PRAM_ALIGNMENT 128 |
||||
#define UEC_THREAD_TX_PRAM_ALIGNMENT 64 |
||||
#define UEC_THREAD_DATA_ALIGNMENT 256 |
||||
#define UEC_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT 32 |
||||
#define UEC_SCHEDULER_ALIGNMENT 4 |
||||
#define UEC_TX_STATISTICS_ALIGNMENT 4 |
||||
#define UEC_RX_STATISTICS_ALIGNMENT 4 |
||||
#define UEC_RX_INTERRUPT_COALESCING_ALIGNMENT 4 |
||||
#define UEC_RX_BD_QUEUES_ALIGNMENT 8 |
||||
#define UEC_RX_PREFETCHED_BDS_ALIGNMENT 128 |
||||
#define UEC_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT 4 |
||||
#define UEC_RX_BD_RING_ALIGNMENT 32 |
||||
#define UEC_TX_BD_RING_ALIGNMENT 32 |
||||
#define UEC_MRBLR_ALIGNMENT 128 |
||||
#define UEC_RX_BD_RING_SIZE_ALIGNMENT 4 |
||||
#define UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT 32 |
||||
#define UEC_RX_DATA_BUF_ALIGNMENT 64 |
||||
|
||||
#define UEC_VLAN_PRIORITY_MAX 8 |
||||
#define UEC_IP_PRIORITY_MAX 64 |
||||
#define UEC_TX_VTAG_TABLE_ENTRY_MAX 8 |
||||
#define UEC_RX_BD_RING_SIZE_MIN 8 |
||||
#define UEC_TX_BD_RING_SIZE_MIN 2 |
||||
|
||||
/* Ethernet speed
|
||||
*/ |
||||
typedef enum enet_speed { |
||||
ENET_SPEED_10BT, /* 10 Base T */ |
||||
ENET_SPEED_100BT, /* 100 Base T */ |
||||
ENET_SPEED_1000BT /* 1000 Base T */ |
||||
} enet_speed_e; |
||||
|
||||
/* Ethernet Address Type.
|
||||
*/ |
||||
typedef enum enet_addr_type { |
||||
ENET_ADDR_TYPE_INDIVIDUAL, |
||||
ENET_ADDR_TYPE_GROUP, |
||||
ENET_ADDR_TYPE_BROADCAST |
||||
} enet_addr_type_e; |
||||
|
||||
/* TBI / MII Set Register
|
||||
*/ |
||||
typedef enum enet_tbi_mii_reg { |
||||
ENET_TBI_MII_CR = 0x00, |
||||
ENET_TBI_MII_SR = 0x01, |
||||
ENET_TBI_MII_ANA = 0x04, |
||||
ENET_TBI_MII_ANLPBPA = 0x05, |
||||
ENET_TBI_MII_ANEX = 0x06, |
||||
ENET_TBI_MII_ANNPT = 0x07, |
||||
ENET_TBI_MII_ANLPANP = 0x08, |
||||
ENET_TBI_MII_EXST = 0x0F, |
||||
ENET_TBI_MII_JD = 0x10, |
||||
ENET_TBI_MII_TBICON = 0x11 |
||||
} enet_tbi_mii_reg_e; |
||||
|
||||
/* UEC number of threads
|
||||
*/ |
||||
typedef enum uec_num_of_threads { |
||||
UEC_NUM_OF_THREADS_1 = 0x1, /* 1 */ |
||||
UEC_NUM_OF_THREADS_2 = 0x2, /* 2 */ |
||||
UEC_NUM_OF_THREADS_4 = 0x0, /* 4 */ |
||||
UEC_NUM_OF_THREADS_6 = 0x3, /* 6 */ |
||||
UEC_NUM_OF_THREADS_8 = 0x4 /* 8 */ |
||||
} uec_num_of_threads_e; |
||||
|
||||
/* UEC ethernet interface type
|
||||
*/ |
||||
typedef enum enet_interface { |
||||
ENET_10_MII, |
||||
ENET_10_RMII, |
||||
ENET_10_RGMII, |
||||
ENET_100_MII, |
||||
ENET_100_RMII, |
||||
ENET_100_RGMII, |
||||
ENET_1000_GMII, |
||||
ENET_1000_RGMII, |
||||
ENET_1000_TBI, |
||||
ENET_1000_RTBI |
||||
} enet_interface_e; |
||||
|
||||
/* UEC initialization info struct
|
||||
*/ |
||||
typedef struct uec_info { |
||||
ucc_fast_info_t uf_info; |
||||
uec_num_of_threads_e num_threads_tx; |
||||
uec_num_of_threads_e num_threads_rx; |
||||
qe_risc_allocation_e riscTx; |
||||
qe_risc_allocation_e riscRx; |
||||
u16 rx_bd_ring_len; |
||||
u16 tx_bd_ring_len; |
||||
u8 phy_address; |
||||
enet_interface_e enet_interface; |
||||
} uec_info_t; |
||||
|
||||
/* UEC driver initialized info
|
||||
*/ |
||||
#define MAX_RXBUF_LEN 1536 |
||||
#define MAX_FRAME_LEN 1518 |
||||
#define MIN_FRAME_LEN 64 |
||||
#define MAX_DMA1_LEN 1520 |
||||
#define MAX_DMA2_LEN 1520 |
||||
|
||||
/* UEC driver private struct
|
||||
*/ |
||||
typedef struct uec_private { |
||||
uec_info_t *uec_info; |
||||
ucc_fast_private_t *uccf; |
||||
struct eth_device *dev; |
||||
uec_t *uec_regs; |
||||
/* enet init command parameter */ |
||||
uec_init_cmd_pram_t *p_init_enet_param; |
||||
u32 init_enet_param_offset; |
||||
/* Rx and Tx paramter */ |
||||
uec_rx_global_pram_t *p_rx_glbl_pram; |
||||
u32 rx_glbl_pram_offset; |
||||
uec_tx_global_pram_t *p_tx_glbl_pram; |
||||
u32 tx_glbl_pram_offset; |
||||
uec_send_queue_mem_region_t *p_send_q_mem_reg; |
||||
u32 send_q_mem_reg_offset; |
||||
uec_thread_data_tx_t *p_thread_data_tx; |
||||
u32 thread_dat_tx_offset; |
||||
uec_thread_data_rx_t *p_thread_data_rx; |
||||
u32 thread_dat_rx_offset; |
||||
uec_rx_bd_queues_entry_t *p_rx_bd_qs_tbl; |
||||
u32 rx_bd_qs_tbl_offset; |
||||
/* BDs specific */ |
||||
u8 *p_tx_bd_ring; |
||||
u32 tx_bd_ring_offset; |
||||
u8 *p_rx_bd_ring; |
||||
u32 rx_bd_ring_offset; |
||||
u8 *p_rx_buf; |
||||
u32 rx_buf_offset; |
||||
volatile qe_bd_t *txBd; |
||||
volatile qe_bd_t *rxBd; |
||||
/* Status */ |
||||
int mac_tx_enabled; |
||||
int mac_rx_enabled; |
||||
int grace_stopped_tx; |
||||
int grace_stopped_rx; |
||||
int the_first_run; |
||||
/* PHY specific */ |
||||
struct uec_mii_info *mii_info; |
||||
int oldspeed; |
||||
int oldduplex; |
||||
int oldlink; |
||||
} uec_private_t; |
||||
|
||||
#endif /* __UEC_H__ */ |
||||
@ -0,0 +1,604 @@ |
||||
/*
|
||||
* Copyright (C) 2005 Freescale Semiconductor, Inc. |
||||
* |
||||
* Author: Shlomi Gridish |
||||
* |
||||
* Description: UCC GETH Driver -- PHY handling |
||||
* Driver for UEC on QE |
||||
* Based on 8260_io/fcc_enet.c |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify it |
||||
* under the terms of the GNU General Public License as published by the |
||||
* Free Software Foundation; either version 2 of the License, or (at your |
||||
* option) any later version. |
||||
* |
||||
*/ |
||||
|
||||
#include "common.h" |
||||
#include "net.h" |
||||
#include "malloc.h" |
||||
#include "asm/errno.h" |
||||
#include "asm/immap_qe.h" |
||||
#include "asm/io.h" |
||||
#include "qe.h" |
||||
#include "uccf.h" |
||||
#include "uec.h" |
||||
#include "uec_phy.h" |
||||
#include "miiphy.h" |
||||
|
||||
#if defined(CONFIG_QE) |
||||
|
||||
#define UEC_VERBOSE_DEBUG |
||||
#define ugphy_printk(format, arg...) \ |
||||
printf(format "\n", ## arg) |
||||
|
||||
#define ugphy_dbg(format, arg...) \ |
||||
ugphy_printk(format , ## arg) |
||||
#define ugphy_err(format, arg...) \ |
||||
ugphy_printk(format , ## arg) |
||||
#define ugphy_info(format, arg...) \ |
||||
ugphy_printk(format , ## arg) |
||||
#define ugphy_warn(format, arg...) \ |
||||
ugphy_printk(format , ## arg) |
||||
|
||||
#ifdef UEC_VERBOSE_DEBUG |
||||
#define ugphy_vdbg ugphy_dbg |
||||
#else |
||||
#define ugphy_vdbg(ugeth, fmt, args...) do { } while (0) |
||||
#endif /* UEC_VERBOSE_DEBUG */ |
||||
|
||||
static void config_genmii_advert(struct uec_mii_info *mii_info); |
||||
static void genmii_setup_forced(struct uec_mii_info *mii_info); |
||||
static void genmii_restart_aneg(struct uec_mii_info *mii_info); |
||||
static int gbit_config_aneg(struct uec_mii_info *mii_info); |
||||
static int genmii_config_aneg(struct uec_mii_info *mii_info); |
||||
static int genmii_update_link(struct uec_mii_info *mii_info); |
||||
static int genmii_read_status(struct uec_mii_info *mii_info); |
||||
u16 phy_read(struct uec_mii_info *mii_info, u16 regnum); |
||||
void phy_write(struct uec_mii_info *mii_info, u16 regnum, u16 val); |
||||
|
||||
/* Write value to the PHY for this device to the register at regnum, */ |
||||
/* waiting until the write is done before it returns. All PHY */ |
||||
/* configuration has to be done through the TSEC1 MIIM regs */ |
||||
void write_phy_reg(struct eth_device *dev, int mii_id, int regnum, int value) |
||||
{ |
||||
uec_private_t *ugeth = (uec_private_t *)dev->priv; |
||||
uec_t *ug_regs; |
||||
enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e)regnum; |
||||
u32 tmp_reg; |
||||
|
||||
ug_regs = ugeth->uec_regs; |
||||
|
||||
/* Stop the MII management read cycle */ |
||||
out_be32(&ug_regs->miimcom, 0); |
||||
/* Setting up the MII Mangement Address Register */ |
||||
tmp_reg = ((u32)mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg; |
||||
out_be32(&ug_regs->miimadd, tmp_reg); |
||||
|
||||
/* Setting up the MII Mangement Control Register with the value */ |
||||
out_be32(&ug_regs->miimcon, (u32)value); |
||||
|
||||
/* Wait till MII management write is complete */ |
||||
while((in_be32(&ug_regs->miimind)) & MIIMIND_BUSY); |
||||
|
||||
udelay(100000); |
||||
} |
||||
|
||||
/* Reads from register regnum in the PHY for device dev, */ |
||||
/* returning the value. Clears miimcom first. All PHY */ |
||||
/* configuration has to be done through the TSEC1 MIIM regs */ |
||||
int read_phy_reg(struct eth_device *dev, int mii_id, int regnum) |
||||
{ |
||||
uec_private_t *ugeth = (uec_private_t *)dev->priv; |
||||
uec_t *ug_regs; |
||||
enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e)regnum; |
||||
u32 tmp_reg; |
||||
u16 value; |
||||
|
||||
ug_regs = ugeth->uec_regs; |
||||
|
||||
/* Setting up the MII Mangement Address Register */ |
||||
tmp_reg = ((u32)mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg ; |
||||
out_be32(&ug_regs->miimadd, tmp_reg); |
||||
|
||||
/* Perform an MII management read cycle */ |
||||
out_be32(&ug_regs->miimcom, 0); |
||||
out_be32(&ug_regs->miimcom, MIIMCOM_READ_CYCLE); |
||||
|
||||
/* Wait till MII management write is complete */ |
||||
while((in_be32(&ug_regs->miimind)) & (MIIMIND_NOT_VALID | MIIMIND_BUSY)); |
||||
|
||||
udelay(100000); |
||||
|
||||
/* Read MII management status */ |
||||
value = (u16)in_be32(&ug_regs->miimstat); |
||||
if(value == 0xffff) |
||||
ugphy_warn("read wrong value : mii_id %d,mii_reg %d, base %08x", |
||||
mii_id, mii_reg, (u32) &(ug_regs->miimcfg)); |
||||
|
||||
return (value); |
||||
} |
||||
|
||||
void mii_clear_phy_interrupt(struct uec_mii_info *mii_info) |
||||
{ |
||||
if(mii_info->phyinfo->ack_interrupt) |
||||
mii_info->phyinfo->ack_interrupt(mii_info); |
||||
} |
||||
|
||||
void mii_configure_phy_interrupt(struct uec_mii_info *mii_info, u32 interrupts) |
||||
{ |
||||
mii_info->interrupts = interrupts; |
||||
if(mii_info->phyinfo->config_intr) |
||||
mii_info->phyinfo->config_intr(mii_info); |
||||
} |
||||
|
||||
/* Writes MII_ADVERTISE with the appropriate values, after
|
||||
* sanitizing advertise to make sure only supported features |
||||
* are advertised |
||||
*/ |
||||
static void config_genmii_advert(struct uec_mii_info *mii_info) |
||||
{ |
||||
u32 advertise; |
||||
u16 adv; |
||||
|
||||
/* Only allow advertising what this PHY supports */ |
||||
mii_info->advertising &= mii_info->phyinfo->features; |
||||
advertise = mii_info->advertising; |
||||
|
||||
/* Setup standard advertisement */ |
||||
adv = phy_read(mii_info, PHY_ANAR); |
||||
adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4); |
||||
if (advertise & ADVERTISED_10baseT_Half) |
||||
adv |= ADVERTISE_10HALF; |
||||
if (advertise & ADVERTISED_10baseT_Full) |
||||
adv |= ADVERTISE_10FULL; |
||||
if (advertise & ADVERTISED_100baseT_Half) |
||||
adv |= ADVERTISE_100HALF; |
||||
if (advertise & ADVERTISED_100baseT_Full) |
||||
adv |= ADVERTISE_100FULL; |
||||
phy_write(mii_info, PHY_ANAR, adv); |
||||
} |
||||
|
||||
static void genmii_setup_forced(struct uec_mii_info *mii_info) |
||||
{ |
||||
u16 ctrl; |
||||
u32 features = mii_info->phyinfo->features; |
||||
|
||||
ctrl = phy_read(mii_info, PHY_BMCR); |
||||
|
||||
ctrl &= ~(PHY_BMCR_DPLX|PHY_BMCR_100_MBPS| |
||||
PHY_BMCR_1000_MBPS|PHY_BMCR_AUTON); |
||||
ctrl |= PHY_BMCR_RESET; |
||||
|
||||
switch(mii_info->speed) { |
||||
case SPEED_1000: |
||||
if(features & (SUPPORTED_1000baseT_Half |
||||
| SUPPORTED_1000baseT_Full)) { |
||||
ctrl |= PHY_BMCR_1000_MBPS; |
||||
break; |
||||
} |
||||
mii_info->speed = SPEED_100; |
||||
case SPEED_100: |
||||
if (features & (SUPPORTED_100baseT_Half |
||||
| SUPPORTED_100baseT_Full)) { |
||||
ctrl |= PHY_BMCR_100_MBPS; |
||||
break; |
||||
} |
||||
mii_info->speed = SPEED_10; |
||||
case SPEED_10: |
||||
if (features & (SUPPORTED_10baseT_Half |
||||
| SUPPORTED_10baseT_Full)) |
||||
break; |
||||
default: /* Unsupported speed! */ |
||||
ugphy_err("%s: Bad speed!", mii_info->dev->name); |
||||
break; |
||||
} |
||||
|
||||
phy_write(mii_info, PHY_BMCR, ctrl); |
||||
} |
||||
|
||||
/* Enable and Restart Autonegotiation */ |
||||
static void genmii_restart_aneg(struct uec_mii_info *mii_info) |
||||
{ |
||||
u16 ctl; |
||||
|
||||
ctl = phy_read(mii_info, PHY_BMCR); |
||||
ctl |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); |
||||
phy_write(mii_info, PHY_BMCR, ctl); |
||||
} |
||||
|
||||
static int gbit_config_aneg(struct uec_mii_info *mii_info) |
||||
{ |
||||
u16 adv; |
||||
u32 advertise; |
||||
|
||||
if(mii_info->autoneg) { |
||||
/* Configure the ADVERTISE register */ |
||||
config_genmii_advert(mii_info); |
||||
advertise = mii_info->advertising; |
||||
|
||||
adv = phy_read(mii_info, MII_1000BASETCONTROL); |
||||
adv &= ~(MII_1000BASETCONTROL_FULLDUPLEXCAP | |
||||
MII_1000BASETCONTROL_HALFDUPLEXCAP); |
||||
if (advertise & SUPPORTED_1000baseT_Half) |
||||
adv |= MII_1000BASETCONTROL_HALFDUPLEXCAP; |
||||
if (advertise & SUPPORTED_1000baseT_Full) |
||||
adv |= MII_1000BASETCONTROL_FULLDUPLEXCAP; |
||||
phy_write(mii_info, MII_1000BASETCONTROL, adv); |
||||
|
||||
/* Start/Restart aneg */ |
||||
genmii_restart_aneg(mii_info); |
||||
} else |
||||
genmii_setup_forced(mii_info); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int marvell_config_aneg(struct uec_mii_info *mii_info) |
||||
{ |
||||
/* The Marvell PHY has an errata which requires
|
||||
* that certain registers get written in order |
||||
* to restart autonegotiation */ |
||||
phy_write(mii_info, PHY_BMCR, PHY_BMCR_RESET); |
||||
|
||||
phy_write(mii_info, 0x1d, 0x1f); |
||||
phy_write(mii_info, 0x1e, 0x200c); |
||||
phy_write(mii_info, 0x1d, 0x5); |
||||
phy_write(mii_info, 0x1e, 0); |
||||
phy_write(mii_info, 0x1e, 0x100); |
||||
|
||||
gbit_config_aneg(mii_info); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int genmii_config_aneg(struct uec_mii_info *mii_info) |
||||
{ |
||||
if (mii_info->autoneg) { |
||||
config_genmii_advert(mii_info); |
||||
genmii_restart_aneg(mii_info); |
||||
} else |
||||
genmii_setup_forced(mii_info); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int genmii_update_link(struct uec_mii_info *mii_info) |
||||
{ |
||||
u16 status; |
||||
|
||||
/* Do a fake read */ |
||||
phy_read(mii_info, PHY_BMSR); |
||||
|
||||
/* Read link and autonegotiation status */ |
||||
status = phy_read(mii_info, PHY_BMSR); |
||||
if ((status & PHY_BMSR_LS) == 0) |
||||
mii_info->link = 0; |
||||
else |
||||
mii_info->link = 1; |
||||
|
||||
/* If we are autonegotiating, and not done,
|
||||
* return an error */ |
||||
if (mii_info->autoneg && !(status & PHY_BMSR_AUTN_COMP)) |
||||
return -EAGAIN; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int genmii_read_status(struct uec_mii_info *mii_info) |
||||
{ |
||||
u16 status; |
||||
int err; |
||||
|
||||
/* Update the link, but return if there
|
||||
* was an error */ |
||||
err = genmii_update_link(mii_info); |
||||
if (err) |
||||
return err; |
||||
|
||||
if (mii_info->autoneg) { |
||||
status = phy_read(mii_info, PHY_ANLPAR); |
||||
|
||||
if (status & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD)) |
||||
mii_info->duplex = DUPLEX_FULL; |
||||
else |
||||
mii_info->duplex = DUPLEX_HALF; |
||||
if (status & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX)) |
||||
mii_info->speed = SPEED_100; |
||||
else |
||||
mii_info->speed = SPEED_10; |
||||
mii_info->pause = 0; |
||||
} |
||||
/* On non-aneg, we assume what we put in BMCR is the speed,
|
||||
* though magic-aneg shouldn't prevent this case from occurring |
||||
*/ |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int marvell_read_status(struct uec_mii_info *mii_info) |
||||
{ |
||||
u16 status; |
||||
int err; |
||||
|
||||
/* Update the link, but return if there
|
||||
* was an error */ |
||||
err = genmii_update_link(mii_info); |
||||
if (err) |
||||
return err; |
||||
|
||||
/* If the link is up, read the speed and duplex */ |
||||
/* If we aren't autonegotiating, assume speeds
|
||||
* are as set */ |
||||
if (mii_info->autoneg && mii_info->link) { |
||||
int speed; |
||||
status = phy_read(mii_info, MII_M1011_PHY_SPEC_STATUS); |
||||
|
||||
/* Get the duplexity */ |
||||
if (status & MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX) |
||||
mii_info->duplex = DUPLEX_FULL; |
||||
else |
||||
mii_info->duplex = DUPLEX_HALF; |
||||
|
||||
/* Get the speed */ |
||||
speed = status & MII_M1011_PHY_SPEC_STATUS_SPD_MASK; |
||||
switch(speed) { |
||||
case MII_M1011_PHY_SPEC_STATUS_1000: |
||||
mii_info->speed = SPEED_1000; |
||||
break; |
||||
case MII_M1011_PHY_SPEC_STATUS_100: |
||||
mii_info->speed = SPEED_100; |
||||
break; |
||||
default: |
||||
mii_info->speed = SPEED_10; |
||||
break; |
||||
} |
||||
mii_info->pause = 0; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int marvell_ack_interrupt(struct uec_mii_info *mii_info) |
||||
{ |
||||
/* Clear the interrupts by reading the reg */ |
||||
phy_read(mii_info, MII_M1011_IEVENT); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int marvell_config_intr(struct uec_mii_info *mii_info) |
||||
{ |
||||
if(mii_info->interrupts == MII_INTERRUPT_ENABLED) |
||||
phy_write(mii_info, MII_M1011_IMASK, MII_M1011_IMASK_INIT); |
||||
else |
||||
phy_write(mii_info, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int dm9161_init(struct uec_mii_info *mii_info) |
||||
{ |
||||
/* Reset the PHY */ |
||||
phy_write(mii_info, PHY_BMCR, phy_read(mii_info, PHY_BMCR) | |
||||
PHY_BMCR_RESET); |
||||
/* PHY and MAC connect*/ |
||||
phy_write(mii_info, PHY_BMCR, phy_read(mii_info, PHY_BMCR) & |
||||
~PHY_BMCR_ISO); |
||||
#ifdef CONFIG_RMII_MODE |
||||
phy_write(mii_info, MII_DM9161_SCR, MII_DM9161_SCR_RMII_INIT); |
||||
#else |
||||
phy_write(mii_info, MII_DM9161_SCR, MII_DM9161_SCR_INIT); |
||||
#endif |
||||
config_genmii_advert(mii_info); |
||||
/* Start/restart aneg */ |
||||
genmii_config_aneg(mii_info); |
||||
/* Delay to wait the aneg compeleted */ |
||||
udelay(3000000); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int dm9161_config_aneg(struct uec_mii_info *mii_info) |
||||
{ |
||||
return 0; |
||||
} |
||||
|
||||
static int dm9161_read_status(struct uec_mii_info *mii_info) |
||||
{ |
||||
u16 status; |
||||
int err; |
||||
|
||||
/* Update the link, but return if there was an error*/ |
||||
err = genmii_update_link(mii_info); |
||||
if (err) |
||||
return err; |
||||
/* If the link is up, read the speed and duplex
|
||||
If we aren't autonegotiating assume speeds are as set */ |
||||
if (mii_info->autoneg && mii_info->link) { |
||||
status = phy_read(mii_info, MII_DM9161_SCSR); |
||||
if (status & (MII_DM9161_SCSR_100F | MII_DM9161_SCSR_100H)) |
||||
mii_info->speed = SPEED_100; |
||||
else |
||||
mii_info->speed = SPEED_10; |
||||
|
||||
if (status & (MII_DM9161_SCSR_100F | MII_DM9161_SCSR_10F)) |
||||
mii_info->duplex = DUPLEX_FULL; |
||||
else |
||||
mii_info->duplex = DUPLEX_HALF; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int dm9161_ack_interrupt(struct uec_mii_info *mii_info) |
||||
{ |
||||
/* Clear the interrupt by reading the reg */ |
||||
phy_read(mii_info, MII_DM9161_INTR); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int dm9161_config_intr(struct uec_mii_info *mii_info) |
||||
{ |
||||
if (mii_info->interrupts == MII_INTERRUPT_ENABLED) |
||||
phy_write(mii_info, MII_DM9161_INTR, MII_DM9161_INTR_INIT); |
||||
else |
||||
phy_write(mii_info, MII_DM9161_INTR, MII_DM9161_INTR_STOP); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static void dm9161_close(struct uec_mii_info *mii_info) |
||||
{ |
||||
} |
||||
|
||||
static struct phy_info phy_info_dm9161 = { |
||||
.phy_id = 0x0181b880, |
||||
.phy_id_mask = 0x0ffffff0, |
||||
.name = "Davicom DM9161E", |
||||
.init = dm9161_init, |
||||
.config_aneg = dm9161_config_aneg, |
||||
.read_status = dm9161_read_status, |
||||
.close = dm9161_close, |
||||
}; |
||||
|
||||
static struct phy_info phy_info_dm9161a = { |
||||
.phy_id = 0x0181b8a0, |
||||
.phy_id_mask = 0x0ffffff0, |
||||
.name = "Davicom DM9161A", |
||||
.features = MII_BASIC_FEATURES, |
||||
.init = dm9161_init, |
||||
.config_aneg = dm9161_config_aneg, |
||||
.read_status = dm9161_read_status, |
||||
.ack_interrupt = dm9161_ack_interrupt, |
||||
.config_intr = dm9161_config_intr, |
||||
.close = dm9161_close, |
||||
}; |
||||
|
||||
static struct phy_info phy_info_marvell = { |
||||
.phy_id = 0x01410c00, |
||||
.phy_id_mask = 0xffffff00, |
||||
.name = "Marvell 88E11x1", |
||||
.features = MII_GBIT_FEATURES, |
||||
.config_aneg = &marvell_config_aneg, |
||||
.read_status = &marvell_read_status, |
||||
.ack_interrupt = &marvell_ack_interrupt, |
||||
.config_intr = &marvell_config_intr, |
||||
}; |
||||
|
||||
static struct phy_info phy_info_genmii= { |
||||
.phy_id = 0x00000000, |
||||
.phy_id_mask = 0x00000000, |
||||
.name = "Generic MII", |
||||
.features = MII_BASIC_FEATURES, |
||||
.config_aneg = genmii_config_aneg, |
||||
.read_status = genmii_read_status, |
||||
}; |
||||
|
||||
static struct phy_info *phy_info[] = { |
||||
&phy_info_dm9161, |
||||
&phy_info_dm9161a, |
||||
&phy_info_marvell, |
||||
&phy_info_genmii, |
||||
NULL |
||||
}; |
||||
|
||||
u16 phy_read(struct uec_mii_info *mii_info, u16 regnum) |
||||
{ |
||||
return mii_info->mdio_read(mii_info->dev, mii_info->mii_id, regnum); |
||||
} |
||||
|
||||
void phy_write(struct uec_mii_info *mii_info, u16 regnum, u16 val) |
||||
{ |
||||
mii_info->mdio_write(mii_info->dev, |
||||
mii_info->mii_id, |
||||
regnum, val); |
||||
} |
||||
|
||||
/* Use the PHY ID registers to determine what type of PHY is attached
|
||||
* to device dev. return a struct phy_info structure describing that PHY |
||||
*/ |
||||
struct phy_info * get_phy_info(struct uec_mii_info *mii_info) |
||||
{ |
||||
u16 phy_reg; |
||||
u32 phy_ID; |
||||
int i; |
||||
struct phy_info *theInfo = NULL; |
||||
|
||||
/* Grab the bits from PHYIR1, and put them in the upper half */ |
||||
phy_reg = phy_read(mii_info, PHY_PHYIDR1); |
||||
phy_ID = (phy_reg & 0xffff) << 16; |
||||
|
||||
/* Grab the bits from PHYIR2, and put them in the lower half */ |
||||
phy_reg = phy_read(mii_info, PHY_PHYIDR2); |
||||
phy_ID |= (phy_reg & 0xffff); |
||||
|
||||
/* loop through all the known PHY types, and find one that */ |
||||
/* matches the ID we read from the PHY. */ |
||||
for (i = 0; phy_info[i]; i++) |
||||
if (phy_info[i]->phy_id == |
||||
(phy_ID & phy_info[i]->phy_id_mask)) { |
||||
theInfo = phy_info[i]; |
||||
break; |
||||
} |
||||
|
||||
/* This shouldn't happen, as we have generic PHY support */ |
||||
if (theInfo == NULL) { |
||||
ugphy_info("UEC: PHY id %x is not supported!", phy_ID); |
||||
return NULL; |
||||
} else { |
||||
ugphy_info("UEC: PHY is %s (%x)", theInfo->name, phy_ID); |
||||
} |
||||
|
||||
return theInfo; |
||||
} |
||||
|
||||
void marvell_phy_interface_mode(struct eth_device *dev, enet_interface_e mode) |
||||
{ |
||||
uec_private_t *uec = (uec_private_t *)dev->priv; |
||||
struct uec_mii_info *mii_info; |
||||
|
||||
if (!uec->mii_info) { |
||||
printf("%s: the PHY not intialized\n", __FUNCTION__); |
||||
return; |
||||
} |
||||
mii_info = uec->mii_info; |
||||
|
||||
if (mode == ENET_100_RGMII) { |
||||
phy_write(mii_info, 0x00, 0x9140); |
||||
phy_write(mii_info, 0x1d, 0x001f); |
||||
phy_write(mii_info, 0x1e, 0x200c); |
||||
phy_write(mii_info, 0x1d, 0x0005); |
||||
phy_write(mii_info, 0x1e, 0x0000); |
||||
phy_write(mii_info, 0x1e, 0x0100); |
||||
phy_write(mii_info, 0x09, 0x0e00); |
||||
phy_write(mii_info, 0x04, 0x01e1); |
||||
phy_write(mii_info, 0x00, 0x9140); |
||||
phy_write(mii_info, 0x00, 0x1000); |
||||
udelay(100000); |
||||
phy_write(mii_info, 0x00, 0x2900); |
||||
phy_write(mii_info, 0x14, 0x0cd2); |
||||
phy_write(mii_info, 0x00, 0xa100); |
||||
phy_write(mii_info, 0x09, 0x0000); |
||||
phy_write(mii_info, 0x1b, 0x800b); |
||||
phy_write(mii_info, 0x04, 0x05e1); |
||||
phy_write(mii_info, 0x00, 0xa100); |
||||
phy_write(mii_info, 0x00, 0x2100); |
||||
udelay(1000000); |
||||
} else if (mode == ENET_10_RGMII) { |
||||
phy_write(mii_info, 0x14, 0x8e40); |
||||
phy_write(mii_info, 0x1b, 0x800b); |
||||
phy_write(mii_info, 0x14, 0x0c82); |
||||
phy_write(mii_info, 0x00, 0x8100); |
||||
udelay(1000000); |
||||
} |
||||
} |
||||
|
||||
void change_phy_interface_mode(struct eth_device *dev, enet_interface_e mode) |
||||
{ |
||||
#ifdef CONFIG_PHY_MODE_NEED_CHANGE |
||||
marvell_phy_interface_mode(dev, mode); |
||||
#endif |
||||
} |
||||
#endif /* CONFIG_QE */ |
||||
@ -0,0 +1,256 @@ |
||||
/*
|
||||
* Copyright (C) 2005 Freescale Semiconductor, Inc. |
||||
* |
||||
* Author: Shlomi Gridish <gridish@freescale.com> |
||||
* |
||||
* Description: UCC ethernet driver -- PHY handling |
||||
* Driver for UEC on QE |
||||
* Based on 8260_io/fcc_enet.c |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify it |
||||
* under the terms of the GNU General Public License as published by the |
||||
* Free Software Foundation; either version 2 of the License, or (at your |
||||
* option) any later version. |
||||
* |
||||
*/ |
||||
#ifndef __UEC_PHY_H__ |
||||
#define __UEC_PHY_H__ |
||||
|
||||
#define MII_end ((u32)-2) |
||||
#define MII_read ((u32)-1) |
||||
|
||||
#define MIIMIND_BUSY 0x00000001 |
||||
#define MIIMIND_NOTVALID 0x00000004 |
||||
|
||||
#define UGETH_AN_TIMEOUT 2000 |
||||
|
||||
/* 1000BT control (Marvell & BCM54xx at least) */ |
||||
#define MII_1000BASETCONTROL 0x09 |
||||
#define MII_1000BASETCONTROL_FULLDUPLEXCAP 0x0200 |
||||
#define MII_1000BASETCONTROL_HALFDUPLEXCAP 0x0100 |
||||
|
||||
/* Cicada Extended Control Register 1 */ |
||||
#define MII_CIS8201_EXT_CON1 0x17 |
||||
#define MII_CIS8201_EXTCON1_INIT 0x0000 |
||||
|
||||
/* Cicada Interrupt Mask Register */ |
||||
#define MII_CIS8201_IMASK 0x19 |
||||
#define MII_CIS8201_IMASK_IEN 0x8000 |
||||
#define MII_CIS8201_IMASK_SPEED 0x4000 |
||||
#define MII_CIS8201_IMASK_LINK 0x2000 |
||||
#define MII_CIS8201_IMASK_DUPLEX 0x1000 |
||||
#define MII_CIS8201_IMASK_MASK 0xf000 |
||||
|
||||
/* Cicada Interrupt Status Register */ |
||||
#define MII_CIS8201_ISTAT 0x1a |
||||
#define MII_CIS8201_ISTAT_STATUS 0x8000 |
||||
#define MII_CIS8201_ISTAT_SPEED 0x4000 |
||||
#define MII_CIS8201_ISTAT_LINK 0x2000 |
||||
#define MII_CIS8201_ISTAT_DUPLEX 0x1000 |
||||
|
||||
/* Cicada Auxiliary Control/Status Register */ |
||||
#define MII_CIS8201_AUX_CONSTAT 0x1c |
||||
#define MII_CIS8201_AUXCONSTAT_INIT 0x0004 |
||||
#define MII_CIS8201_AUXCONSTAT_DUPLEX 0x0020 |
||||
#define MII_CIS8201_AUXCONSTAT_SPEED 0x0018 |
||||
#define MII_CIS8201_AUXCONSTAT_GBIT 0x0010 |
||||
#define MII_CIS8201_AUXCONSTAT_100 0x0008 |
||||
|
||||
/* 88E1011 PHY Status Register */ |
||||
#define MII_M1011_PHY_SPEC_STATUS 0x11 |
||||
#define MII_M1011_PHY_SPEC_STATUS_1000 0x8000 |
||||
#define MII_M1011_PHY_SPEC_STATUS_100 0x4000 |
||||
#define MII_M1011_PHY_SPEC_STATUS_SPD_MASK 0xc000 |
||||
#define MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX 0x2000 |
||||
#define MII_M1011_PHY_SPEC_STATUS_RESOLVED 0x0800 |
||||
#define MII_M1011_PHY_SPEC_STATUS_LINK 0x0400 |
||||
|
||||
#define MII_M1011_IEVENT 0x13 |
||||
#define MII_M1011_IEVENT_CLEAR 0x0000 |
||||
|
||||
#define MII_M1011_IMASK 0x12 |
||||
#define MII_M1011_IMASK_INIT 0x6400 |
||||
#define MII_M1011_IMASK_CLEAR 0x0000 |
||||
|
||||
#define MII_DM9161_SCR 0x10 |
||||
#define MII_DM9161_SCR_INIT 0x0610 |
||||
#define MII_DM9161_SCR_RMII_INIT 0x0710 |
||||
|
||||
/* DM9161 Specified Configuration and Status Register */ |
||||
#define MII_DM9161_SCSR 0x11 |
||||
#define MII_DM9161_SCSR_100F 0x8000 |
||||
#define MII_DM9161_SCSR_100H 0x4000 |
||||
#define MII_DM9161_SCSR_10F 0x2000 |
||||
#define MII_DM9161_SCSR_10H 0x1000 |
||||
|
||||
/* DM9161 Interrupt Register */ |
||||
#define MII_DM9161_INTR 0x15 |
||||
#define MII_DM9161_INTR_PEND 0x8000 |
||||
#define MII_DM9161_INTR_DPLX_MASK 0x0800 |
||||
#define MII_DM9161_INTR_SPD_MASK 0x0400 |
||||
#define MII_DM9161_INTR_LINK_MASK 0x0200 |
||||
#define MII_DM9161_INTR_MASK 0x0100 |
||||
#define MII_DM9161_INTR_DPLX_CHANGE 0x0010 |
||||
#define MII_DM9161_INTR_SPD_CHANGE 0x0008 |
||||
#define MII_DM9161_INTR_LINK_CHANGE 0x0004 |
||||
#define MII_DM9161_INTR_INIT 0x0000 |
||||
#define MII_DM9161_INTR_STOP \ |
||||
(MII_DM9161_INTR_DPLX_MASK | MII_DM9161_INTR_SPD_MASK \
|
||||
| MII_DM9161_INTR_LINK_MASK | MII_DM9161_INTR_MASK) |
||||
|
||||
/* DM9161 10BT Configuration/Status */ |
||||
#define MII_DM9161_10BTCSR 0x12 |
||||
#define MII_DM9161_10BTCSR_INIT 0x7800 |
||||
|
||||
#define MII_BASIC_FEATURES (SUPPORTED_10baseT_Half | \ |
||||
SUPPORTED_10baseT_Full | \
|
||||
SUPPORTED_100baseT_Half | \
|
||||
SUPPORTED_100baseT_Full | \
|
||||
SUPPORTED_Autoneg | \
|
||||
SUPPORTED_TP | \
|
||||
SUPPORTED_MII) |
||||
|
||||
#define MII_GBIT_FEATURES (MII_BASIC_FEATURES | \ |
||||
SUPPORTED_1000baseT_Half | \
|
||||
SUPPORTED_1000baseT_Full) |
||||
|
||||
#define MII_READ_COMMAND 0x00000001 |
||||
|
||||
#define MII_INTERRUPT_DISABLED 0x0 |
||||
#define MII_INTERRUPT_ENABLED 0x1 |
||||
|
||||
#define SPEED_10 10 |
||||
#define SPEED_100 100 |
||||
#define SPEED_1000 1000 |
||||
|
||||
/* Duplex, half or full. */ |
||||
#define DUPLEX_HALF 0x00 |
||||
#define DUPLEX_FULL 0x01 |
||||
|
||||
/* Indicates what features are supported by the interface. */ |
||||
#define SUPPORTED_10baseT_Half (1 << 0) |
||||
#define SUPPORTED_10baseT_Full (1 << 1) |
||||
#define SUPPORTED_100baseT_Half (1 << 2) |
||||
#define SUPPORTED_100baseT_Full (1 << 3) |
||||
#define SUPPORTED_1000baseT_Half (1 << 4) |
||||
#define SUPPORTED_1000baseT_Full (1 << 5) |
||||
#define SUPPORTED_Autoneg (1 << 6) |
||||
#define SUPPORTED_TP (1 << 7) |
||||
#define SUPPORTED_AUI (1 << 8) |
||||
#define SUPPORTED_MII (1 << 9) |
||||
#define SUPPORTED_FIBRE (1 << 10) |
||||
#define SUPPORTED_BNC (1 << 11) |
||||
#define SUPPORTED_10000baseT_Full (1 << 12) |
||||
|
||||
#define ADVERTISED_10baseT_Half (1 << 0) |
||||
#define ADVERTISED_10baseT_Full (1 << 1) |
||||
#define ADVERTISED_100baseT_Half (1 << 2) |
||||
#define ADVERTISED_100baseT_Full (1 << 3) |
||||
#define ADVERTISED_1000baseT_Half (1 << 4) |
||||
#define ADVERTISED_1000baseT_Full (1 << 5) |
||||
#define ADVERTISED_Autoneg (1 << 6) |
||||
#define ADVERTISED_TP (1 << 7) |
||||
#define ADVERTISED_AUI (1 << 8) |
||||
#define ADVERTISED_MII (1 << 9) |
||||
#define ADVERTISED_FIBRE (1 << 10) |
||||
#define ADVERTISED_BNC (1 << 11) |
||||
#define ADVERTISED_10000baseT_Full (1 << 12) |
||||
|
||||
/* Advertisement control register. */ |
||||
#define ADVERTISE_SLCT 0x001f /* Selector bits */ |
||||
#define ADVERTISE_CSMA 0x0001 /* Only selector supported */ |
||||
#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */ |
||||
#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ |
||||
#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ |
||||
#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ |
||||
#define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */ |
||||
#define ADVERTISE_RESV 0x1c00 /* Unused... */ |
||||
#define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */ |
||||
#define ADVERTISE_LPACK 0x4000 /* Ack link partners response */ |
||||
#define ADVERTISE_NPAGE 0x8000 /* Next page bit */ |
||||
|
||||
#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \ |
||||
ADVERTISE_CSMA) |
||||
#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \ |
||||
ADVERTISE_100HALF | ADVERTISE_100FULL) |
||||
|
||||
/* Taken from mii_if_info and sungem_phy.h */ |
||||
struct uec_mii_info { |
||||
/* Information about the PHY type */ |
||||
/* And management functions */ |
||||
struct phy_info *phyinfo; |
||||
|
||||
struct eth_device *dev; |
||||
|
||||
/* forced speed & duplex (no autoneg)
|
||||
* partner speed & duplex & pause (autoneg) |
||||
*/ |
||||
int speed; |
||||
int duplex; |
||||
int pause; |
||||
|
||||
/* The most recently read link state */ |
||||
int link; |
||||
|
||||
/* Enabled Interrupts */ |
||||
u32 interrupts; |
||||
|
||||
u32 advertising; |
||||
int autoneg; |
||||
int mii_id; |
||||
|
||||
/* private data pointer */ |
||||
/* For use by PHYs to maintain extra state */ |
||||
void *priv; |
||||
|
||||
/* Provided by ethernet driver */ |
||||
int (*mdio_read) (struct eth_device *dev, int mii_id, int reg); |
||||
void (*mdio_write) (struct eth_device *dev, int mii_id, int reg, int val); |
||||
}; |
||||
|
||||
/* struct phy_info: a structure which defines attributes for a PHY
|
||||
* |
||||
* id will contain a number which represents the PHY. During |
||||
* startup, the driver will poll the PHY to find out what its |
||||
* UID--as defined by registers 2 and 3--is. The 32-bit result |
||||
* gotten from the PHY will be ANDed with phy_id_mask to |
||||
* discard any bits which may change based on revision numbers |
||||
* unimportant to functionality |
||||
* |
||||
* There are 6 commands which take a ugeth_mii_info structure. |
||||
* Each PHY must declare config_aneg, and read_status. |
||||
*/ |
||||
struct phy_info { |
||||
u32 phy_id; |
||||
char *name; |
||||
unsigned int phy_id_mask; |
||||
u32 features; |
||||
|
||||
/* Called to initialize the PHY */ |
||||
int (*init)(struct uec_mii_info *mii_info); |
||||
|
||||
/* Called to suspend the PHY for power */ |
||||
int (*suspend)(struct uec_mii_info *mii_info); |
||||
|
||||
/* Reconfigures autonegotiation (or disables it) */ |
||||
int (*config_aneg)(struct uec_mii_info *mii_info); |
||||
|
||||
/* Determines the negotiated speed and duplex */ |
||||
int (*read_status)(struct uec_mii_info *mii_info); |
||||
|
||||
/* Clears any pending interrupts */ |
||||
int (*ack_interrupt)(struct uec_mii_info *mii_info); |
||||
|
||||
/* Enables or disables interrupts */ |
||||
int (*config_intr)(struct uec_mii_info *mii_info); |
||||
|
||||
/* Clears up any memory if needed */ |
||||
void (*close)(struct uec_mii_info *mii_info); |
||||
}; |
||||
|
||||
struct phy_info *get_phy_info(struct uec_mii_info *mii_info); |
||||
void write_phy_reg(struct eth_device *dev, int mii_id, int regnum, int value); |
||||
int read_phy_reg(struct eth_device *dev, int mii_id, int regnum); |
||||
void mii_clear_phy_interrupt(struct uec_mii_info *mii_info); |
||||
void mii_configure_phy_interrupt(struct uec_mii_info *mii_info, u32 interrupts); |
||||
#endif /* __UEC_PHY_H__ */ |
||||
@ -1,103 +0,0 @@ |
||||
/*
|
||||
* Freescale I2C Controller |
||||
* |
||||
* This software may be used and distributed according to the |
||||
* terms of the GNU Public License, Version 2, incorporated |
||||
* herein by reference. |
||||
* |
||||
* Copyright 2004 Freescale Semiconductor. |
||||
* (C) Copyright 2003, Motorola, Inc. |
||||
* author: Eran Liberty (liberty@freescale.com) |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef _ASM_I2C_H_ |
||||
#define _ASM_I2C_H_ |
||||
|
||||
#include <asm/types.h> |
||||
|
||||
typedef struct i2c |
||||
{ |
||||
u8 adr; /**< I2C slave address */ |
||||
#define I2C_ADR 0xFE |
||||
#define I2C_ADR_SHIFT 1 |
||||
#define I2C_ADR_RES ~(I2C_ADR) |
||||
u8 res0[3]; |
||||
u8 fdr; /**< I2C frequency divider register */ |
||||
#define IC2_FDR 0x3F |
||||
#define IC2_FDR_SHIFT 0 |
||||
#define IC2_FDR_RES ~(IC2_FDR) |
||||
u8 res1[3]; |
||||
u8 cr; /**< I2C control redister */ |
||||
#define I2C_CR_MEN 0x80 |
||||
#define I2C_CR_MIEN 0x40 |
||||
#define I2C_CR_MSTA 0x20 |
||||
#define I2C_CR_MTX 0x10 |
||||
#define I2C_CR_TXAK 0x08 |
||||
#define I2C_CR_RSTA 0x04 |
||||
#define I2C_CR_BCST 0x01 |
||||
u8 res2[3]; |
||||
u8 sr; /**< I2C status register */ |
||||
#define I2C_SR_MCF 0x80 |
||||
#define I2C_SR_MAAS 0x40 |
||||
#define I2C_SR_MBB 0x20 |
||||
#define I2C_SR_MAL 0x10 |
||||
#define I2C_SR_BCSTM 0x08 |
||||
#define I2C_SR_SRW 0x04 |
||||
#define I2C_SR_MIF 0x02 |
||||
#define I2C_SR_RXAK 0x01 |
||||
u8 res3[3]; |
||||
u8 dr; /**< I2C data register */ |
||||
#define I2C_DR 0xFF |
||||
#define I2C_DR_SHIFT 0 |
||||
#define I2C_DR_RES ~(I2C_DR) |
||||
u8 res4[3]; |
||||
u8 dfsrr; /**< I2C digital filter sampling rate register */ |
||||
#define I2C_DFSRR 0x3F |
||||
#define I2C_DFSRR_SHIFT 0 |
||||
#define I2C_DFSRR_RES ~(I2C_DR) |
||||
u8 res5[3]; |
||||
u8 res6[0xE8]; |
||||
} i2c_t; |
||||
|
||||
#ifndef CFG_HZ |
||||
#error CFG_HZ is not defined in /include/configs/${BOARD}.h |
||||
#endif |
||||
#define I2C_TIMEOUT (CFG_HZ/4) |
||||
|
||||
#ifndef CFG_IMMRBAR |
||||
#error CFG_IMMRBAR is not defined in /include/configs/${BOARD}.h |
||||
#endif |
||||
|
||||
#ifndef CFG_I2C_OFFSET |
||||
#error CFG_I2C_OFFSET is not defined in /include/configs/${BOARD}.h |
||||
#endif |
||||
|
||||
#if defined(CONFIG_MPC8349EMDS) || defined(CONFIG_TQM834X) |
||||
/*
|
||||
* MPC8349 have two i2c bus |
||||
*/ |
||||
extern i2c_t * mpc8349_i2c; |
||||
#define I2C mpc8349_i2c |
||||
#else |
||||
#define I2C ((i2c_t*)(CFG_IMMRBAR + CFG_I2C_OFFSET)) |
||||
#endif |
||||
|
||||
#define I2C_READ 1 |
||||
#define I2C_WRITE 0 |
||||
|
||||
#endif /* _ASM_I2C_H_ */ |
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,550 @@ |
||||
/*
|
||||
* QUICC Engine (QE) Internal Memory Map. |
||||
* The Internal Memory Map for devices with QE on them. This |
||||
* is the superset of all QE devices (8360, etc.). |
||||
* |
||||
* Copyright (c) 2006 Freescale Semiconductor, Inc. |
||||
* Author: Shlomi Gridih <gridish@freescale.com> |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify it |
||||
* under the terms of the GNU General Public License as published by the |
||||
* Free Software Foundation; either version 2 of the License, or (at your |
||||
* option) any later version. |
||||
*/ |
||||
|
||||
#ifndef __IMMAP_QE_H__ |
||||
#define __IMMAP_QE_H__ |
||||
|
||||
/* QE I-RAM
|
||||
*/ |
||||
typedef struct qe_iram { |
||||
u32 iadd; /* I-RAM Address Register */ |
||||
u32 idata; /* I-RAM Data Register */ |
||||
u8 res0[0x78]; |
||||
} __attribute__ ((packed)) qe_iram_t; |
||||
|
||||
/* QE Interrupt Controller
|
||||
*/ |
||||
typedef struct qe_ic { |
||||
u32 qicr; |
||||
u32 qivec; |
||||
u32 qripnr; |
||||
u32 qipnr; |
||||
u32 qipxcc; |
||||
u32 qipycc; |
||||
u32 qipwcc; |
||||
u32 qipzcc; |
||||
u32 qimr; |
||||
u32 qrimr; |
||||
u32 qicnr; |
||||
u8 res0[0x4]; |
||||
u32 qiprta; |
||||
u32 qiprtb; |
||||
u8 res1[0x4]; |
||||
u32 qricr; |
||||
u8 res2[0x20]; |
||||
u32 qhivec; |
||||
u8 res3[0x1C]; |
||||
} __attribute__ ((packed)) qe_ic_t; |
||||
|
||||
/* Communications Processor
|
||||
*/ |
||||
typedef struct cp_qe { |
||||
u32 cecr; /* QE command register */ |
||||
u32 ceccr; /* QE controller configuration register */ |
||||
u32 cecdr; /* QE command data register */ |
||||
u8 res0[0xA]; |
||||
u16 ceter; /* QE timer event register */ |
||||
u8 res1[0x2]; |
||||
u16 cetmr; /* QE timers mask register */ |
||||
u32 cetscr; /* QE time-stamp timer control register */ |
||||
u32 cetsr1; /* QE time-stamp register 1 */ |
||||
u32 cetsr2; /* QE time-stamp register 2 */ |
||||
u8 res2[0x8]; |
||||
u32 cevter; /* QE virtual tasks event register */ |
||||
u32 cevtmr; /* QE virtual tasks mask register */ |
||||
u16 cercr; /* QE RAM control register */ |
||||
u8 res3[0x2]; |
||||
u8 res4[0x24]; |
||||
u16 ceexe1; /* QE external request 1 event register */ |
||||
u8 res5[0x2]; |
||||
u16 ceexm1; /* QE external request 1 mask register */ |
||||
u8 res6[0x2]; |
||||
u16 ceexe2; /* QE external request 2 event register */ |
||||
u8 res7[0x2]; |
||||
u16 ceexm2; /* QE external request 2 mask register */ |
||||
u8 res8[0x2]; |
||||
u16 ceexe3; /* QE external request 3 event register */ |
||||
u8 res9[0x2]; |
||||
u16 ceexm3; /* QE external request 3 mask register */ |
||||
u8 res10[0x2]; |
||||
u16 ceexe4; /* QE external request 4 event register */ |
||||
u8 res11[0x2]; |
||||
u16 ceexm4; /* QE external request 4 mask register */ |
||||
u8 res12[0x2]; |
||||
u8 res13[0x280]; |
||||
} __attribute__ ((packed)) cp_qe_t; |
||||
|
||||
/* QE Multiplexer
|
||||
*/ |
||||
typedef struct qe_mux { |
||||
u32 cmxgcr; /* CMX general clock route register */ |
||||
u32 cmxsi1cr_l; /* CMX SI1 clock route low register */ |
||||
u32 cmxsi1cr_h; /* CMX SI1 clock route high register */ |
||||
u32 cmxsi1syr; /* CMX SI1 SYNC route register */ |
||||
u32 cmxucr1; /* CMX UCC1, UCC3 clock route register */ |
||||
u32 cmxucr2; /* CMX UCC5, UCC7 clock route register */ |
||||
u32 cmxucr3; /* CMX UCC2, UCC4 clock route register */ |
||||
u32 cmxucr4; /* CMX UCC6, UCC8 clock route register */ |
||||
u32 cmxupcr; /* CMX UPC clock route register */ |
||||
u8 res0[0x1C]; |
||||
} __attribute__ ((packed)) qe_mux_t; |
||||
|
||||
/* QE Timers
|
||||
*/ |
||||
typedef struct qe_timers { |
||||
u8 gtcfr1; /* Timer 1 2 global configuration register */ |
||||
u8 res0[0x3]; |
||||
u8 gtcfr2; /* Timer 3 4 global configuration register */ |
||||
u8 res1[0xB]; |
||||
u16 gtmdr1; /* Timer 1 mode register */ |
||||
u16 gtmdr2; /* Timer 2 mode register */ |
||||
u16 gtrfr1; /* Timer 1 reference register */ |
||||
u16 gtrfr2; /* Timer 2 reference register */ |
||||
u16 gtcpr1; /* Timer 1 capture register */ |
||||
u16 gtcpr2; /* Timer 2 capture register */ |
||||
u16 gtcnr1; /* Timer 1 counter */ |
||||
u16 gtcnr2; /* Timer 2 counter */ |
||||
u16 gtmdr3; /* Timer 3 mode register */ |
||||
u16 gtmdr4; /* Timer 4 mode register */ |
||||
u16 gtrfr3; /* Timer 3 reference register */ |
||||
u16 gtrfr4; /* Timer 4 reference register */ |
||||
u16 gtcpr3; /* Timer 3 capture register */ |
||||
u16 gtcpr4; /* Timer 4 capture register */ |
||||
u16 gtcnr3; /* Timer 3 counter */ |
||||
u16 gtcnr4; /* Timer 4 counter */ |
||||
u16 gtevr1; /* Timer 1 event register */ |
||||
u16 gtevr2; /* Timer 2 event register */ |
||||
u16 gtevr3; /* Timer 3 event register */ |
||||
u16 gtevr4; /* Timer 4 event register */ |
||||
u16 gtps; /* Timer 1 prescale register */ |
||||
u8 res2[0x46]; |
||||
} __attribute__ ((packed)) qe_timers_t; |
||||
|
||||
/* BRG
|
||||
*/ |
||||
typedef struct qe_brg { |
||||
u32 brgc1; /* BRG1 configuration register */ |
||||
u32 brgc2; /* BRG2 configuration register */ |
||||
u32 brgc3; /* BRG3 configuration register */ |
||||
u32 brgc4; /* BRG4 configuration register */ |
||||
u32 brgc5; /* BRG5 configuration register */ |
||||
u32 brgc6; /* BRG6 configuration register */ |
||||
u32 brgc7; /* BRG7 configuration register */ |
||||
u32 brgc8; /* BRG8 configuration register */ |
||||
u32 brgc9; /* BRG9 configuration register */ |
||||
u32 brgc10; /* BRG10 configuration register */ |
||||
u32 brgc11; /* BRG11 configuration register */ |
||||
u32 brgc12; /* BRG12 configuration register */ |
||||
u32 brgc13; /* BRG13 configuration register */ |
||||
u32 brgc14; /* BRG14 configuration register */ |
||||
u32 brgc15; /* BRG15 configuration register */ |
||||
u32 brgc16; /* BRG16 configuration register */ |
||||
u8 res0[0x40]; |
||||
} __attribute__ ((packed)) qe_brg_t; |
||||
|
||||
/* SPI
|
||||
*/ |
||||
typedef struct spi { |
||||
u8 res0[0x20]; |
||||
u32 spmode; /* SPI mode register */ |
||||
u8 res1[0x2]; |
||||
u8 spie; /* SPI event register */ |
||||
u8 res2[0x1]; |
||||
u8 res3[0x2]; |
||||
u8 spim; /* SPI mask register */ |
||||
u8 res4[0x1]; |
||||
u8 res5[0x1]; |
||||
u8 spcom; /* SPI command register */ |
||||
u8 res6[0x2]; |
||||
u32 spitd; /* SPI transmit data register (cpu mode) */ |
||||
u32 spird; /* SPI receive data register (cpu mode) */ |
||||
u8 res7[0x8]; |
||||
} __attribute__ ((packed)) spi_t; |
||||
|
||||
/* SI
|
||||
*/ |
||||
typedef struct si1 { |
||||
u16 siamr1; /* SI1 TDMA mode register */ |
||||
u16 sibmr1; /* SI1 TDMB mode register */ |
||||
u16 sicmr1; /* SI1 TDMC mode register */ |
||||
u16 sidmr1; /* SI1 TDMD mode register */ |
||||
u8 siglmr1_h; /* SI1 global mode register high */ |
||||
u8 res0[0x1]; |
||||
u8 sicmdr1_h; /* SI1 command register high */ |
||||
u8 res2[0x1]; |
||||
u8 sistr1_h; /* SI1 status register high */ |
||||
u8 res3[0x1]; |
||||
u16 sirsr1_h; /* SI1 RAM shadow address register high */ |
||||
u8 sitarc1; /* SI1 RAM counter Tx TDMA */ |
||||
u8 sitbrc1; /* SI1 RAM counter Tx TDMB */ |
||||
u8 sitcrc1; /* SI1 RAM counter Tx TDMC */ |
||||
u8 sitdrc1; /* SI1 RAM counter Tx TDMD */ |
||||
u8 sirarc1; /* SI1 RAM counter Rx TDMA */ |
||||
u8 sirbrc1; /* SI1 RAM counter Rx TDMB */ |
||||
u8 sircrc1; /* SI1 RAM counter Rx TDMC */ |
||||
u8 sirdrc1; /* SI1 RAM counter Rx TDMD */ |
||||
u8 res4[0x8]; |
||||
u16 siemr1; /* SI1 TDME mode register 16 bits */ |
||||
u16 sifmr1; /* SI1 TDMF mode register 16 bits */ |
||||
u16 sigmr1; /* SI1 TDMG mode register 16 bits */ |
||||
u16 sihmr1; /* SI1 TDMH mode register 16 bits */ |
||||
u8 siglmg1_l; /* SI1 global mode register low 8 bits */ |
||||
u8 res5[0x1]; |
||||
u8 sicmdr1_l; /* SI1 command register low 8 bits */ |
||||
u8 res6[0x1]; |
||||
u8 sistr1_l; /* SI1 status register low 8 bits */ |
||||
u8 res7[0x1]; |
||||
u16 sirsr1_l; /* SI1 RAM shadow address register low 16 bits */ |
||||
u8 siterc1; /* SI1 RAM counter Tx TDME 8 bits */ |
||||
u8 sitfrc1; /* SI1 RAM counter Tx TDMF 8 bits */ |
||||
u8 sitgrc1; /* SI1 RAM counter Tx TDMG 8 bits */ |
||||
u8 sithrc1; /* SI1 RAM counter Tx TDMH 8 bits */ |
||||
u8 sirerc1; /* SI1 RAM counter Rx TDME 8 bits */ |
||||
u8 sirfrc1; /* SI1 RAM counter Rx TDMF 8 bits */ |
||||
u8 sirgrc1; /* SI1 RAM counter Rx TDMG 8 bits */ |
||||
u8 sirhrc1; /* SI1 RAM counter Rx TDMH 8 bits */ |
||||
u8 res8[0x8]; |
||||
u32 siml1; /* SI1 multiframe limit register */ |
||||
u8 siedm1; /* SI1 extended diagnostic mode register */ |
||||
u8 res9[0xBB]; |
||||
} __attribute__ ((packed)) si1_t; |
||||
|
||||
/* SI Routing Tables
|
||||
*/ |
||||
typedef struct sir { |
||||
u8 tx[0x400]; |
||||
u8 rx[0x400]; |
||||
u8 res0[0x800]; |
||||
} __attribute__ ((packed)) sir_t; |
||||
|
||||
/* USB Controller.
|
||||
*/ |
||||
typedef struct usb_ctlr { |
||||
u8 usb_usmod; |
||||
u8 usb_usadr; |
||||
u8 usb_uscom; |
||||
u8 res1[1]; |
||||
u16 usb_usep1; |
||||
u16 usb_usep2; |
||||
u16 usb_usep3; |
||||
u16 usb_usep4; |
||||
u8 res2[4]; |
||||
u16 usb_usber; |
||||
u8 res3[2]; |
||||
u16 usb_usbmr; |
||||
u8 res4[1]; |
||||
u8 usb_usbs; |
||||
u16 usb_ussft; |
||||
u8 res5[2]; |
||||
u16 usb_usfrn; |
||||
u8 res6[0x22]; |
||||
} __attribute__ ((packed)) usb_t; |
||||
|
||||
/* MCC
|
||||
*/ |
||||
typedef struct mcc { |
||||
u32 mcce; /* MCC event register */ |
||||
u32 mccm; /* MCC mask register */ |
||||
u32 mccf; /* MCC configuration register */ |
||||
u32 merl; /* MCC emergency request level register */ |
||||
u8 res0[0xF0]; |
||||
} __attribute__ ((packed)) mcc_t; |
||||
|
||||
/* QE UCC Slow
|
||||
*/ |
||||
typedef struct ucc_slow { |
||||
u32 gumr_l; /* UCCx general mode register (low) */ |
||||
u32 gumr_h; /* UCCx general mode register (high) */ |
||||
u16 upsmr; /* UCCx protocol-specific mode register */ |
||||
u8 res0[0x2]; |
||||
u16 utodr; /* UCCx transmit on demand register */ |
||||
u16 udsr; /* UCCx data synchronization register */ |
||||
u16 ucce; /* UCCx event register */ |
||||
u8 res1[0x2]; |
||||
u16 uccm; /* UCCx mask register */ |
||||
u8 res2[0x1]; |
||||
u8 uccs; /* UCCx status register */ |
||||
u8 res3[0x24]; |
||||
u16 utpt; |
||||
u8 guemr; /* UCC general extended mode register */ |
||||
u8 res4[0x200 - 0x091]; |
||||
} __attribute__ ((packed)) ucc_slow_t; |
||||
|
||||
typedef struct ucc_ethernet { |
||||
u32 maccfg1; /* mac configuration reg. 1 */ |
||||
u32 maccfg2; /* mac configuration reg. 2 */ |
||||
u32 ipgifg; /* interframe gap reg. */ |
||||
u32 hafdup; /* half-duplex reg. */ |
||||
u8 res1[0x10]; |
||||
u32 miimcfg; /* MII management configuration reg */ |
||||
u32 miimcom; /* MII management command reg */ |
||||
u32 miimadd; /* MII management address reg */ |
||||
u32 miimcon; /* MII management control reg */ |
||||
u32 miimstat; /* MII management status reg */ |
||||
u32 miimind; /* MII management indication reg */ |
||||
u32 ifctl; /* interface control reg */ |
||||
u32 ifstat; /* interface statux reg */ |
||||
u32 macstnaddr1; /* mac station address part 1 reg */ |
||||
u32 macstnaddr2; /* mac station address part 2 reg */ |
||||
u8 res2[0x8]; |
||||
u32 uempr; /* UCC Ethernet Mac parameter reg */ |
||||
u32 utbipar; /* UCC tbi address reg */ |
||||
u16 uescr; /* UCC Ethernet statistics control reg */ |
||||
u8 res3[0x180 - 0x15A]; |
||||
u32 tx64; /* Total number of frames (including bad
|
||||
* frames) transmitted that were exactly |
||||
* of the minimal length (64 for un tagged, |
||||
* 68 for tagged, or with length exactly |
||||
* equal to the parameter MINLength */ |
||||
u32 tx127; /* Total number of frames (including bad
|
||||
* frames) transmitted that were between |
||||
* MINLength (Including FCS length==4) |
||||
* and 127 octets */ |
||||
u32 tx255; /* Total number of frames (including bad
|
||||
* frames) transmitted that were between |
||||
* 128 (Including FCS length==4) and 255 |
||||
* octets */ |
||||
u32 rx64; /* Total number of frames received including
|
||||
* bad frames that were exactly of the |
||||
* mninimal length (64 bytes) */ |
||||
u32 rx127; /* Total number of frames (including bad
|
||||
* frames) received that were between |
||||
* MINLength (Including FCS length==4) |
||||
* and 127 octets */ |
||||
u32 rx255; /* Total number of frames (including
|
||||
* bad frames) received that were between |
||||
* 128 (Including FCS length==4) and 255 |
||||
* octets */ |
||||
u32 txok; /* Total number of octets residing in frames
|
||||
* that where involved in succesfull |
||||
* transmission */ |
||||
u16 txcf; /* Total number of PAUSE control frames
|
||||
* transmitted by this MAC */ |
||||
u8 res4[0x2]; |
||||
u32 tmca; /* Total number of frames that were transmitted
|
||||
* succesfully with the group address bit set |
||||
* that are not broadcast frames */ |
||||
u32 tbca; /* Total number of frames transmitted
|
||||
* succesfully that had destination address |
||||
* field equal to the broadcast address */ |
||||
u32 rxfok; /* Total number of frames received OK */ |
||||
u32 rxbok; /* Total number of octets received OK */ |
||||
u32 rbyt; /* Total number of octets received including
|
||||
* octets in bad frames. Must be implemented |
||||
* in HW because it includes octets in frames |
||||
* that never even reach the UCC */ |
||||
u32 rmca; /* Total number of frames that were received
|
||||
* succesfully with the group address bit set |
||||
* that are not broadcast frames */ |
||||
u32 rbca; /* Total number of frames received succesfully
|
||||
* that had destination address equal to the |
||||
* broadcast address */ |
||||
u32 scar; /* Statistics carry register */ |
||||
u32 scam; /* Statistics caryy mask register */ |
||||
u8 res5[0x200 - 0x1c4]; |
||||
} __attribute__ ((packed)) uec_t; |
||||
|
||||
/* QE UCC Fast
|
||||
*/ |
||||
typedef struct ucc_fast { |
||||
u32 gumr; /* UCCx general mode register */ |
||||
u32 upsmr; /* UCCx protocol-specific mode register */ |
||||
u16 utodr; /* UCCx transmit on demand register */ |
||||
u8 res0[0x2]; |
||||
u16 udsr; /* UCCx data synchronization register */ |
||||
u8 res1[0x2]; |
||||
u32 ucce; /* UCCx event register */ |
||||
u32 uccm; /* UCCx mask register. */ |
||||
u8 uccs; /* UCCx status register */ |
||||
u8 res2[0x7]; |
||||
u32 urfb; /* UCC receive FIFO base */ |
||||
u16 urfs; /* UCC receive FIFO size */ |
||||
u8 res3[0x2]; |
||||
u16 urfet; /* UCC receive FIFO emergency threshold */ |
||||
u16 urfset; /* UCC receive FIFO special emergency
|
||||
* threshold */ |
||||
u32 utfb; /* UCC transmit FIFO base */ |
||||
u16 utfs; /* UCC transmit FIFO size */ |
||||
u8 res4[0x2]; |
||||
u16 utfet; /* UCC transmit FIFO emergency threshold */ |
||||
u8 res5[0x2]; |
||||
u16 utftt; /* UCC transmit FIFO transmit threshold */ |
||||
u8 res6[0x2]; |
||||
u16 utpt; /* UCC transmit polling timer */ |
||||
u8 res7[0x2]; |
||||
u32 urtry; /* UCC retry counter register */ |
||||
u8 res8[0x4C]; |
||||
u8 guemr; /* UCC general extended mode register */ |
||||
u8 res9[0x100 - 0x091]; |
||||
uec_t ucc_eth; |
||||
} __attribute__ ((packed)) ucc_fast_t; |
||||
|
||||
/* QE UCC
|
||||
*/ |
||||
typedef struct ucc_common { |
||||
u8 res1[0x90]; |
||||
u8 guemr; |
||||
u8 res2[0x200 - 0x091]; |
||||
} __attribute__ ((packed)) ucc_common_t; |
||||
|
||||
typedef struct ucc { |
||||
union { |
||||
ucc_slow_t slow; |
||||
ucc_fast_t fast; |
||||
ucc_common_t common; |
||||
}; |
||||
} __attribute__ ((packed)) ucc_t; |
||||
|
||||
/* MultiPHY UTOPIA POS Controllers (UPC)
|
||||
*/ |
||||
typedef struct upc { |
||||
u32 upgcr; /* UTOPIA/POS general configuration register */ |
||||
u32 uplpa; /* UTOPIA/POS last PHY address */ |
||||
u32 uphec; /* ATM HEC register */ |
||||
u32 upuc; /* UTOPIA/POS UCC configuration */ |
||||
u32 updc1; /* UTOPIA/POS device 1 configuration */ |
||||
u32 updc2; /* UTOPIA/POS device 2 configuration */ |
||||
u32 updc3; /* UTOPIA/POS device 3 configuration */ |
||||
u32 updc4; /* UTOPIA/POS device 4 configuration */ |
||||
u32 upstpa; /* UTOPIA/POS STPA threshold */ |
||||
u8 res0[0xC]; |
||||
u32 updrs1_h; /* UTOPIA/POS device 1 rate select */ |
||||
u32 updrs1_l; /* UTOPIA/POS device 1 rate select */ |
||||
u32 updrs2_h; /* UTOPIA/POS device 2 rate select */ |
||||
u32 updrs2_l; /* UTOPIA/POS device 2 rate select */ |
||||
u32 updrs3_h; /* UTOPIA/POS device 3 rate select */ |
||||
u32 updrs3_l; /* UTOPIA/POS device 3 rate select */ |
||||
u32 updrs4_h; /* UTOPIA/POS device 4 rate select */ |
||||
u32 updrs4_l; /* UTOPIA/POS device 4 rate select */ |
||||
u32 updrp1; /* UTOPIA/POS device 1 receive priority low */ |
||||
u32 updrp2; /* UTOPIA/POS device 2 receive priority low */ |
||||
u32 updrp3; /* UTOPIA/POS device 3 receive priority low */ |
||||
u32 updrp4; /* UTOPIA/POS device 4 receive priority low */ |
||||
u32 upde1; /* UTOPIA/POS device 1 event */ |
||||
u32 upde2; /* UTOPIA/POS device 2 event */ |
||||
u32 upde3; /* UTOPIA/POS device 3 event */ |
||||
u32 upde4; /* UTOPIA/POS device 4 event */ |
||||
u16 uprp1; |
||||
u16 uprp2; |
||||
u16 uprp3; |
||||
u16 uprp4; |
||||
u8 res1[0x8]; |
||||
u16 uptirr1_0; /* Device 1 transmit internal rate 0 */ |
||||
u16 uptirr1_1; /* Device 1 transmit internal rate 1 */ |
||||
u16 uptirr1_2; /* Device 1 transmit internal rate 2 */ |
||||
u16 uptirr1_3; /* Device 1 transmit internal rate 3 */ |
||||
u16 uptirr2_0; /* Device 2 transmit internal rate 0 */ |
||||
u16 uptirr2_1; /* Device 2 transmit internal rate 1 */ |
||||
u16 uptirr2_2; /* Device 2 transmit internal rate 2 */ |
||||
u16 uptirr2_3; /* Device 2 transmit internal rate 3 */ |
||||
u16 uptirr3_0; /* Device 3 transmit internal rate 0 */ |
||||
u16 uptirr3_1; /* Device 3 transmit internal rate 1 */ |
||||
u16 uptirr3_2; /* Device 3 transmit internal rate 2 */ |
||||
u16 uptirr3_3; /* Device 3 transmit internal rate 3 */ |
||||
u16 uptirr4_0; /* Device 4 transmit internal rate 0 */ |
||||
u16 uptirr4_1; /* Device 4 transmit internal rate 1 */ |
||||
u16 uptirr4_2; /* Device 4 transmit internal rate 2 */ |
||||
u16 uptirr4_3; /* Device 4 transmit internal rate 3 */ |
||||
u32 uper1; /* Device 1 port enable register */ |
||||
u32 uper2; /* Device 2 port enable register */ |
||||
u32 uper3; /* Device 3 port enable register */ |
||||
u32 uper4; /* Device 4 port enable register */ |
||||
u8 res2[0x150]; |
||||
} __attribute__ ((packed)) upc_t; |
||||
|
||||
/* SDMA
|
||||
*/ |
||||
typedef struct sdma { |
||||
u32 sdsr; /* Serial DMA status register */ |
||||
u32 sdmr; /* Serial DMA mode register */ |
||||
u32 sdtr1; /* SDMA system bus threshold register */ |
||||
u32 sdtr2; /* SDMA secondary bus threshold register */ |
||||
u32 sdhy1; /* SDMA system bus hysteresis register */ |
||||
u32 sdhy2; /* SDMA secondary bus hysteresis register */ |
||||
u32 sdta1; /* SDMA system bus address register */ |
||||
u32 sdta2; /* SDMA secondary bus address register */ |
||||
u32 sdtm1; /* SDMA system bus MSNUM register */ |
||||
u32 sdtm2; /* SDMA secondary bus MSNUM register */ |
||||
u8 res0[0x10]; |
||||
u32 sdaqr; /* SDMA address bus qualify register */ |
||||
u32 sdaqmr; /* SDMA address bus qualify mask register */ |
||||
u8 res1[0x4]; |
||||
u32 sdwbcr; /* SDMA CAM entries base register */ |
||||
u8 res2[0x38]; |
||||
} __attribute__ ((packed)) sdma_t; |
||||
|
||||
/* Debug Space
|
||||
*/ |
||||
typedef struct dbg { |
||||
u32 bpdcr; /* Breakpoint debug command register */ |
||||
u32 bpdsr; /* Breakpoint debug status register */ |
||||
u32 bpdmr; /* Breakpoint debug mask register */ |
||||
u32 bprmrr0; /* Breakpoint request mode risc register 0 */ |
||||
u32 bprmrr1; /* Breakpoint request mode risc register 1 */ |
||||
u8 res0[0x8]; |
||||
u32 bprmtr0; /* Breakpoint request mode trb register 0 */ |
||||
u32 bprmtr1; /* Breakpoint request mode trb register 1 */ |
||||
u8 res1[0x8]; |
||||
u32 bprmir; /* Breakpoint request mode immediate register */ |
||||
u32 bprmsr; /* Breakpoint request mode serial register */ |
||||
u32 bpemr; /* Breakpoint exit mode register */ |
||||
u8 res2[0x48]; |
||||
} __attribute__ ((packed)) dbg_t; |
||||
|
||||
/* RISC Special Registers (Trap and Breakpoint)
|
||||
*/ |
||||
typedef struct rsp { |
||||
u8 fixme[0x100]; |
||||
} __attribute__ ((packed)) rsp_t; |
||||
|
||||
typedef struct qe_immap { |
||||
qe_iram_t iram; /* I-RAM */ |
||||
qe_ic_t ic; /* Interrupt Controller */ |
||||
cp_qe_t cp; /* Communications Processor */ |
||||
qe_mux_t qmx; /* QE Multiplexer */ |
||||
qe_timers_t qet; /* QE Timers */ |
||||
spi_t spi[0x2]; /* spi */ |
||||
mcc_t mcc; /* mcc */ |
||||
qe_brg_t brg; /* brg */ |
||||
usb_t usb; /* USB */ |
||||
si1_t si1; /* SI */ |
||||
u8 res11[0x800]; |
||||
sir_t sir; /* SI Routing Tables */ |
||||
ucc_t ucc1; /* ucc1 */ |
||||
ucc_t ucc3; /* ucc3 */ |
||||
ucc_t ucc5; /* ucc5 */ |
||||
ucc_t ucc7; /* ucc7 */ |
||||
u8 res12[0x600]; |
||||
upc_t upc1; /* MultiPHY UTOPIA POS Controller 1 */ |
||||
ucc_t ucc2; /* ucc2 */ |
||||
ucc_t ucc4; /* ucc4 */ |
||||
ucc_t ucc6; /* ucc6 */ |
||||
ucc_t ucc8; /* ucc8 */ |
||||
u8 res13[0x600]; |
||||
upc_t upc2; /* MultiPHY UTOPIA POS Controller 2 */ |
||||
sdma_t sdma; /* SDMA */ |
||||
dbg_t dbg; /* Debug Space */ |
||||
rsp_t rsp[0x2]; /* RISC Special Registers
|
||||
* (Trap and Breakpoint) */ |
||||
u8 res14[0x300]; |
||||
u8 res15[0x3A00]; |
||||
u8 res16[0x8000]; /* 0x108000 - 0x110000 */ |
||||
u8 muram[0xC000]; /* 0x110000 - 0x11C000 Multi-user RAM */ |
||||
u8 res17[0x24000]; /* 0x11C000 - 0x140000 */ |
||||
u8 res18[0xC0000]; /* 0x140000 - 0x200000 */ |
||||
} __attribute__ ((packed)) qe_map_t; |
||||
|
||||
extern qe_map_t *qe_immr; |
||||
|
||||
#endif /* __IMMAP_QE_H__ */ |
||||
@ -0,0 +1,804 @@ |
||||
/*
|
||||
* Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
MPC8349E-mITX board configuration file |
||||
|
||||
Memory map: |
||||
|
||||
0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB) |
||||
0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB) |
||||
0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB) |
||||
0xE000_0000-0xEFFF_FFFF IMMR (1 MB) |
||||
0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB) |
||||
0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB) |
||||
0xF000_0000-0xF000_FFFF Compact Flash |
||||
0xF001_0000-0xF001_FFFF Local bus expansion slot |
||||
0xF800_0000-0xF801_FFFF GBE L2 Switch VSC7385 |
||||
0xFF00_0000-0xFF7F_FFFF Alternative bank of Flash memory (8MB) |
||||
0xFF80_0000-0xFFFF_FFFF Boot Flash (8 MB) |
||||
|
||||
I2C address list: |
||||
Align. Board |
||||
Bus Addr Part No. Description Length Location |
||||
---------------------------------------------------------------- |
||||
I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64 |
||||
|
||||
I2C1 0x20 PCF8574 I2C Expander 0 U8 |
||||
I2C1 0x21 PCF8574 I2C Expander 0 U10 |
||||
I2C1 0x38 PCF8574A I2C Expander 0 U8 |
||||
I2C1 0x39 PCF8574A I2C Expander 0 U10 |
||||
I2C1 0x51 (DDR) DDR EEPROM 1 U1 |
||||
I2C1 0x68 DS1339 RTC 1 U68 |
||||
|
||||
Note that a given board has *either* a pair of 8574s or a pair of 8574As. |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
#undef DEBUG |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
*/ |
||||
#define CONFIG_MPC834X /* MPC834x family (8343, 8347, 8349) */ |
||||
#define CONFIG_MPC8349 /* MPC8349 specific */ |
||||
|
||||
#define CONFIG_PCI |
||||
|
||||
#define CONFIG_COMPACT_FLASH /* The CF card interface on the back of the board */ |
||||
#define CONFIG_RTC_DS1337 |
||||
|
||||
/* I2C */ |
||||
#define CONFIG_HARD_I2C |
||||
|
||||
#ifdef CONFIG_HARD_I2C |
||||
|
||||
#define CONFIG_MISC_INIT_F |
||||
#define CONFIG_MISC_INIT_R |
||||
|
||||
#define CONFIG_FSL_I2C |
||||
#define CONFIG_I2C_MULTI_BUS |
||||
#define CONFIG_I2C_CMD_TREE |
||||
#define CFG_I2C_OFFSET 0x3000 |
||||
#define CFG_I2C2_OFFSET 0x3100 |
||||
#define CFG_SPD_BUS_NUM 1 /* The I2C bus for SPD */ |
||||
|
||||
#define CFG_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */ |
||||
#define CFG_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */ |
||||
#define CFG_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */ |
||||
#define CFG_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */ |
||||
#define CFG_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */ |
||||
#define CFG_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/ |
||||
#define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */ |
||||
|
||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ |
||||
#define CFG_I2C_SLAVE 0x7F |
||||
|
||||
/* Don't probe these addresses: */ |
||||
#define CFG_I2C_NOPROBES {{1, CFG_I2C_8574_ADDR1}, \ |
||||
{1, CFG_I2C_8574_ADDR2}, \
|
||||
{1, CFG_I2C_8574A_ADDR1}, \
|
||||
{1, CFG_I2C_8574A_ADDR2}} |
||||
/* Bit definitions for the 8574[A] I2C expander */ |
||||
#define I2C_8574_REVISION 0x03 /* Board revision, 00=0.0, 01=0.1, 10=1.0 */ |
||||
#define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */ |
||||
#define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */ |
||||
#define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */ |
||||
#define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/ |
||||
|
||||
#undef CONFIG_SOFT_I2C |
||||
|
||||
#endif |
||||
|
||||
#define CONFIG_TSEC_ENET /* tsec ethernet support */ |
||||
#define CONFIG_ENV_OVERWRITE |
||||
|
||||
#define PCI_66M |
||||
#ifdef PCI_66M |
||||
#define CONFIG_83XX_CLKIN 66666666 /* in Hz */ |
||||
#else |
||||
#define CONFIG_83XX_CLKIN 33333333 /* in Hz */ |
||||
#endif |
||||
|
||||
#ifndef CONFIG_SYS_CLK_FREQ |
||||
#ifdef PCI_66M |
||||
#define CONFIG_SYS_CLK_FREQ 66666666 |
||||
#else |
||||
#define CONFIG_SYS_CLK_FREQ 33333333 |
||||
#endif |
||||
#endif |
||||
|
||||
#define CFG_IMMR 0xE0000000 /* The IMMR is relocated to here */ |
||||
|
||||
#undef CFG_DRAM_TEST /* memory test, takes time */ |
||||
#define CFG_MEMTEST_START 0x00003000 /* memtest region */ |
||||
#define CFG_MEMTEST_END 0x07100000 /* only has 128M */ |
||||
|
||||
/*
|
||||
* DDR Setup |
||||
*/ |
||||
#undef CONFIG_DDR_ECC /* only for ECC DDR module */ |
||||
#undef CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ |
||||
#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ |
||||
|
||||
/*
|
||||
* 32-bit data path mode. |
||||
* |
||||
* Please note that using this mode for devices with the real density of 64-bit |
||||
* effectively reduces the amount of available memory due to the effect of |
||||
* wrapping around while translating address to row/columns, for example in the |
||||
* 256MB module the upper 128MB get aliased with contents of the lower |
||||
* 128MB); normally this define should be used for devices with real 32-bit |
||||
* data path. |
||||
*/ |
||||
#undef CONFIG_DDR_32BIT |
||||
|
||||
#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ |
||||
#define CFG_SDRAM_BASE CFG_DDR_BASE |
||||
#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE |
||||
#undef CONFIG_DDR_2T_TIMING |
||||
#define CFG_83XX_DDR_USES_CS0 |
||||
|
||||
#ifndef CONFIG_SPD_EEPROM |
||||
/*
|
||||
* Manually set up DDR parameters |
||||
*/ |
||||
#define CFG_DDR_SIZE 256 /* Mb */ |
||||
#define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) |
||||
|
||||
#define CFG_DDR_TIMING_1 0x26242321 |
||||
#define CFG_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */ |
||||
#endif |
||||
|
||||
/* FLASH on the Local Bus */ |
||||
#define CFG_FLASH_CFI /* use the Common Flash Interface */ |
||||
#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ |
||||
#define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */ |
||||
#define CFG_FLASH_SIZE 16 /* FLASH size in MB */ |
||||
#define CFG_FLASH_EMPTY_INFO |
||||
|
||||
#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_PS_16 | BR_V) |
||||
#define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ |
||||
OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
|
||||
OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) |
||||
#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */ |
||||
#define CFG_LBLAWAR0_PRELIM 0x80000017 /* 16Mb window bytes */ |
||||
|
||||
/* VSC7385 on the Local Bus */ |
||||
#define CFG_VSC7385_BASE 0xF8000000 /* start of VSC7385 */ |
||||
|
||||
#define CFG_BR1_PRELIM (CFG_VSC7385_BASE | BR_PS_8 | BR_V) |
||||
#define CFG_OR1_PRELIM (0xFFFE0000 /* 128KB */ | \ |
||||
OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
|
||||
OR_GPCM_SETA | OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) |
||||
|
||||
#define CFG_LBLAWBAR1_PRELIM CFG_VSC7385_BASE /* Access window base at VSC7385 base */ |
||||
#define CFG_LBLAWAR1_PRELIM 0x80000010 /* Access window size 128K */ |
||||
|
||||
#define CFG_MAX_FLASH_BANKS 2 /* number of banks */ |
||||
#define CFG_MAX_FLASH_SECT 135 /* sectors per device */ |
||||
|
||||
#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE + 0x800000} |
||||
|
||||
#undef CFG_FLASH_CHECKSUM |
||||
#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ |
||||
|
||||
#define CFG_LED_BASE 0xF9000000 /* start of LED and Board ID */ |
||||
#define CFG_BR2_PRELIM (CFG_LED_BASE | BR_PS_8 | BR_V) |
||||
#define CFG_OR2_PRELIM (0xFFE00000 /* 2MB */ | \ |
||||
OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | \
|
||||
OR_GPCM_SCY_9 | \
|
||||
OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) |
||||
|
||||
#ifdef CONFIG_COMPACT_FLASH |
||||
|
||||
#define CFG_CF_BASE 0xF0000000 |
||||
|
||||
#define CFG_BR3_PRELIM (CFG_CF_BASE | BR_PS_16 | BR_MS_UPMA | BR_V) |
||||
#define CFG_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI) |
||||
|
||||
#define CFG_LBLAWBAR2_PRELIM CFG_CF_BASE /* Window base at flash base + LED & Board ID */ |
||||
#define CFG_LBLAWAR2_PRELIM 0x8000000F /* 64K bytes */ |
||||
|
||||
#undef CONFIG_IDE_RESET |
||||
#undef CONFIG_IDE_PREINIT |
||||
|
||||
#define CFG_IDE_MAXBUS 1 |
||||
#define CFG_IDE_MAXDEVICE 1 |
||||
|
||||
#define CFG_ATA_IDE0_OFFSET 0x0000 |
||||
#define CFG_ATA_BASE_ADDR CFG_CF_BASE |
||||
#define CFG_ATA_DATA_OFFSET 0x0000 |
||||
#define CFG_ATA_REG_OFFSET 0 |
||||
#define CFG_ATA_ALT_OFFSET 0x0200 |
||||
#define CFG_ATA_STRIDE 2 |
||||
|
||||
#define ATA_RESET_TIME 1 /* If a CF card is not inserted, time out quickly */ |
||||
|
||||
#endif |
||||
|
||||
#define CONFIG_DOS_PARTITION |
||||
|
||||
#define CFG_MID_FLASH_JUMP 0x7F000000 |
||||
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ |
||||
|
||||
|
||||
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) |
||||
#define CFG_RAMBOOT |
||||
#else |
||||
#undef CFG_RAMBOOT |
||||
#endif |
||||
|
||||
#define CONFIG_L1_INIT_RAM |
||||
#define CFG_INIT_RAM_LOCK |
||||
#define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ |
||||
#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ |
||||
|
||||
#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
||||
#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ |
||||
|
||||
/*
|
||||
* Local Bus LCRR and LBCR regs |
||||
* LCRR: DLL bypass, Clock divider is 4 |
||||
* External Local Bus rate is |
||||
* CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV |
||||
*/ |
||||
#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) |
||||
#define CFG_LBC_LBCR 0x00000000 |
||||
|
||||
#undef CFG_LB_SDRAM /* if board has SRDAM on local bus */ |
||||
|
||||
#ifdef CFG_LB_SDRAM |
||||
/*local bus BR2, OR2 definition for SDRAM if soldered on the ADS board*/ |
||||
/*
|
||||
* Base Register 2 and Option Register 2 configure SDRAM. |
||||
* The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. |
||||
* |
||||
* For BR2, need: |
||||
* Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 |
||||
* port-size = 32-bits = BR2[19:20] = 11 |
||||
* no parity checking = BR2[21:22] = 00 |
||||
* SDRAM for MSEL = BR2[24:26] = 011 |
||||
* Valid = BR[31] = 1 |
||||
* |
||||
* 0 4 8 12 16 20 24 28 |
||||
* 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 |
||||
*/ |
||||
|
||||
#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ |
||||
#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ |
||||
|
||||
#define CFG_LBLAWBAR2_PRELIM 0xF0000000 |
||||
#define CFG_LBLAWAR2_PRELIM 0x80000019 /* 64M */ |
||||
|
||||
#define CFG_BR2_PRELIM (CFG_LBC_SDRAM_BASE | BR_PS_32 | BR_MS_SDRAM | BR_V) |
||||
#define CFG_OR2_PRELIM (0xFC000000 /* 64 MB */ | \ |
||||
OR_SDRAM_XAM | \
|
||||
((9 - 7) << OR_SDRAM_COLS_SHIFT) | \
|
||||
((13 - 9) << OR_SDRAM_ROWS_SHIFT) | \
|
||||
OR_SDRAM_EAD) |
||||
|
||||
#define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ |
||||
#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32*/ |
||||
|
||||
/*
|
||||
* LSDMR masks |
||||
*/ |
||||
#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) |
||||
#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) |
||||
#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) |
||||
#define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16)) |
||||
#define CFG_LBC_LSDMR_RFCR8 (5 << (31 - 16)) |
||||
#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) |
||||
#define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19)) |
||||
#define CFG_LBC_LSDMR_PRETOACT6 (5 << (31 - 19)) |
||||
#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) |
||||
#define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22)) |
||||
#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) |
||||
#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) |
||||
#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) |
||||
#define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27)) |
||||
#define CFG_LBC_LSDMR_WRC3 (3 << (31 - 27)) |
||||
#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) |
||||
#define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29)) |
||||
#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) |
||||
|
||||
#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) |
||||
#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) |
||||
#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) |
||||
#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) |
||||
#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) |
||||
#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) |
||||
#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) |
||||
#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) |
||||
|
||||
#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFEN \ |
||||
| CFG_LBC_LSDMR_BSMA1516 \
|
||||
| CFG_LBC_LSDMR_RFCR8 \
|
||||
| CFG_LBC_LSDMR_PRETOACT6 \
|
||||
| CFG_LBC_LSDMR_ACTTORW3 \
|
||||
| CFG_LBC_LSDMR_BL8 \
|
||||
| CFG_LBC_LSDMR_WRC3 \
|
||||
| CFG_LBC_LSDMR_CL3 \
|
||||
) |
||||
|
||||
/*
|
||||
* SDRAM Controller configuration sequence. |
||||
*/ |
||||
#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ |
||||
| CFG_LBC_LSDMR_OP_PCHALL) |
||||
#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ |
||||
| CFG_LBC_LSDMR_OP_ARFRSH) |
||||
#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ |
||||
| CFG_LBC_LSDMR_OP_ARFRSH) |
||||
#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ |
||||
| CFG_LBC_LSDMR_OP_MRW) |
||||
#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ |
||||
| CFG_LBC_LSDMR_OP_NORMAL) |
||||
#endif |
||||
|
||||
/*
|
||||
* Serial Port |
||||
*/ |
||||
#define CONFIG_CONS_INDEX 1 |
||||
#undef CONFIG_SERIAL_SOFTWARE_FIFO |
||||
#define CFG_NS16550 |
||||
#define CFG_NS16550_SERIAL |
||||
#define CFG_NS16550_REG_SIZE 1 |
||||
#define CFG_NS16550_CLK get_bus_freq(0) |
||||
|
||||
#define CFG_BAUDRATE_TABLE \ |
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
||||
|
||||
#define CFG_NS16550_COM1 (CFG_IMMR + 0x4500) |
||||
#define CFG_NS16550_COM2 (CFG_IMMR + 0x4600) |
||||
|
||||
/* Use the HUSH parser */ |
||||
#define CFG_HUSH_PARSER |
||||
#ifdef CFG_HUSH_PARSER |
||||
#define CFG_PROMPT_HUSH_PS2 "> " |
||||
#endif |
||||
|
||||
/* pass open firmware flat tree */ |
||||
#define CONFIG_OF_FLAT_TREE 1 |
||||
#define CONFIG_OF_BOARD_SETUP 1 |
||||
|
||||
/* maximum size of the flat tree (8K) */ |
||||
#define OF_FLAT_TREE_MAX_SIZE 8192 |
||||
|
||||
#define OF_CPU "PowerPC,8349@0" |
||||
#define OF_SOC "soc8349@e0000000" |
||||
#define OF_TBCLK (bd->bi_busfreq / 4) |
||||
#define OF_STDOUT_PATH "/soc8349@e0000000/serial@4500" |
||||
|
||||
#ifdef CONFIG_PCI |
||||
|
||||
#define CONFIG_MPC83XX_PCI2 |
||||
|
||||
/*
|
||||
* General PCI |
||||
* Addresses are mapped 1-1. |
||||
*/ |
||||
#define CFG_PCI1_MEM_BASE 0x80000000 |
||||
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE |
||||
#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ |
||||
#define CFG_PCI1_MMIO_BASE (CFG_PCI1_MEM_BASE + CFG_PCI1_MEM_SIZE) |
||||
#define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE |
||||
#define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */ |
||||
#define CFG_PCI1_IO_BASE 0x00000000 |
||||
#define CFG_PCI1_IO_PHYS 0xE2000000 |
||||
#define CFG_PCI1_IO_SIZE 0x01000000 /* 16M */ |
||||
|
||||
#ifdef CONFIG_MPC83XX_PCI2 |
||||
#define CFG_PCI2_MEM_BASE (CFG_PCI1_MMIO_BASE + CFG_PCI1_MMIO_SIZE) |
||||
#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE |
||||
#define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */ |
||||
#define CFG_PCI2_MMIO_BASE (CFG_PCI2_MEM_BASE + CFG_PCI2_MEM_SIZE) |
||||
#define CFG_PCI2_MMIO_PHYS CFG_PCI2_MMIO_BASE |
||||
#define CFG_PCI2_MMIO_SIZE 0x10000000 /* 256M */ |
||||
#define CFG_PCI2_IO_BASE 0x00000000 |
||||
#define CFG_PCI2_IO_PHYS (CFG_PCI1_IO_PHYS + CFG_PCI1_IO_SIZE) |
||||
#define CFG_PCI2_IO_SIZE 0x01000000 /* 16M */ |
||||
#endif |
||||
|
||||
#define _IO_BASE 0x00000000 /* points to PCI I/O space */ |
||||
|
||||
#define CONFIG_NET_MULTI |
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */ |
||||
|
||||
#ifdef CONFIG_RTL8139 |
||||
/* This macro is used by RTL8139 but not defined in PPC architecture */ |
||||
#define KSEG1ADDR(x) (x) |
||||
#endif |
||||
|
||||
#ifndef CONFIG_PCI_PNP |
||||
#define PCI_ENET0_IOADDR 0x00000000 |
||||
#define PCI_ENET0_MEMADDR CFG_PCI2_MEM_BASE |
||||
#define PCI_IDSEL_NUMBER 0x0f /* IDSEL = AD15 */ |
||||
#endif |
||||
|
||||
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
||||
|
||||
#endif |
||||
|
||||
/* TSEC */ |
||||
|
||||
#ifdef CONFIG_TSEC_ENET |
||||
|
||||
#ifndef CONFIG_NET_MULTI |
||||
#define CONFIG_NET_MULTI |
||||
#endif |
||||
|
||||
#define CONFIG_MII |
||||
#define CONFIG_PHY_GIGE /* In case CFG_CMD_MII is specified */ |
||||
|
||||
#define CONFIG_MPC83XX_TSEC1 |
||||
|
||||
#ifdef CONFIG_MPC83XX_TSEC1 |
||||
#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0" |
||||
#define CFG_TSEC1_OFFSET 0x24000 |
||||
#define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */ |
||||
#define TSEC1_PHYIDX 0 |
||||
#endif |
||||
|
||||
#ifdef CONFIG_MPC83XX_TSEC2 |
||||
#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1" |
||||
#define CFG_TSEC2_OFFSET 0x25000 |
||||
#define CONFIG_UNKNOWN_TSEC /* TSEC2 is proprietary */ |
||||
#define TSEC2_PHY_ADDR 4 |
||||
#define TSEC2_PHYIDX 0 |
||||
#endif |
||||
|
||||
#define CONFIG_ETHPRIME "Freescale TSEC" |
||||
|
||||
#endif |
||||
|
||||
|
||||
/*
|
||||
* Environment |
||||
*/ |
||||
#ifndef CFG_RAMBOOT |
||||
#define CFG_ENV_IS_IN_FLASH |
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) |
||||
#define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ |
||||
#define CFG_ENV_SIZE 0x2000 |
||||
#else |
||||
#define CFG_NO_FLASH /* Flash is not usable now */ |
||||
#define CFG_ENV_IS_NOWHERE /* Store ENV in memory only */ |
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) |
||||
#define CFG_ENV_SIZE 0x2000 |
||||
#endif |
||||
|
||||
#define CONFIG_LOADS_ECHO /* echo on for serial download */ |
||||
#define CFG_LOADS_BAUD_CHANGE /* allow baudrate change */ |
||||
|
||||
/* CONFIG_COMMANDS */ |
||||
|
||||
#ifdef CONFIG_COMPACT_FLASH |
||||
#define CONFIG_COMMANDS_CF (CFG_CMD_IDE | CFG_CMD_FAT) |
||||
#else |
||||
#define CONFIG_COMMANDS_CF 0 |
||||
#endif |
||||
|
||||
#ifdef CONFIG_PCI |
||||
#define CONFIG_COMMANDS_PCI CFG_CMD_PCI |
||||
#else |
||||
#define CONFIG_COMMANDS_PCI 0 |
||||
#endif |
||||
|
||||
#ifdef CONFIG_HARD_I2C |
||||
#define CONFIG_COMMANDS_I2C CFG_CMD_I2C |
||||
#else |
||||
#define CONFIG_COMMANDS_I2C 0 |
||||
#endif |
||||
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ |
||||
CONFIG_COMMANDS_CF | \
|
||||
CFG_CMD_NET | \
|
||||
CFG_CMD_PING | \
|
||||
CONFIG_COMMANDS_I2C | \
|
||||
CONFIG_COMMANDS_PCI | \
|
||||
CFG_CMD_SDRAM | \
|
||||
CFG_CMD_DATE | \
|
||||
CFG_CMD_CACHE | \
|
||||
CFG_CMD_IRQ) |
||||
#include <cmd_confdefs.h> |
||||
|
||||
/* Watchdog */ |
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
#ifdef CONFIG_WATCHDOG |
||||
#define CFG_WATCHDOG_VALUE 0xFFFFFFC3 |
||||
#endif |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_LOAD_ADDR 0x2000000 /* default load address */ |
||||
#define CFG_PROMPT "MPC8349E-mITX> " /* Monitor Command Prompt */ |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
|
||||
#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ |
||||
|
||||
/* Cache Configuration */ |
||||
#define CFG_DCACHE_SIZE 32768 |
||||
#define CFG_CACHELINE_SIZE 32 |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CACHELINE_SHIFT 5 /* log2 of the above value */ |
||||
#endif |
||||
|
||||
#define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */ |
||||
|
||||
#define CFG_HRCW_LOW (\ |
||||
HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
|
||||
HRCWL_DDR_TO_SCB_CLK_1X1 |\
|
||||
HRCWL_CSB_TO_CLKIN_4X1 |\
|
||||
HRCWL_VCO_1X2 |\
|
||||
HRCWL_CORE_TO_CSB_2X1) |
||||
|
||||
#ifdef PCI_64BIT |
||||
#define CFG_HRCW_HIGH (\ |
||||
HRCWH_PCI_HOST |\
|
||||
HRCWH_64_BIT_PCI |\
|
||||
HRCWH_PCI1_ARBITER_ENABLE |\
|
||||
HRCWH_PCI2_ARBITER_DISABLE |\
|
||||
HRCWH_CORE_ENABLE |\
|
||||
HRCWH_FROM_0X00000100 |\
|
||||
HRCWH_BOOTSEQ_DISABLE |\
|
||||
HRCWH_SW_WATCHDOG_DISABLE |\
|
||||
HRCWH_ROM_LOC_LOCAL_16BIT |\
|
||||
HRCWH_TSEC1M_IN_GMII |\
|
||||
HRCWH_TSEC2M_IN_GMII ) |
||||
#else |
||||
#define CFG_HRCW_HIGH (\ |
||||
HRCWH_PCI_HOST |\
|
||||
HRCWH_32_BIT_PCI |\
|
||||
HRCWH_PCI1_ARBITER_ENABLE |\
|
||||
HRCWH_PCI2_ARBITER_DISABLE |\
|
||||
HRCWH_CORE_ENABLE |\
|
||||
HRCWH_FROM_0XFFF00100 |\
|
||||
HRCWH_BOOTSEQ_DISABLE |\
|
||||
HRCWH_SW_WATCHDOG_DISABLE |\
|
||||
HRCWH_ROM_LOC_LOCAL_16BIT |\
|
||||
HRCWH_TSEC1M_IN_GMII |\
|
||||
HRCWH_TSEC2M_IN_GMII ) |
||||
#endif |
||||
|
||||
/* System performance */ |
||||
#define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ |
||||
#define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ |
||||
#define CFG_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ |
||||
#define CFG_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ |
||||
#define CFG_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ |
||||
#define CFG_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ |
||||
#define CFG_ACR_RPTCNT 3 /* Arbiter repeat count */ |
||||
|
||||
/* System IO Config */ |
||||
#define CFG_SICRH SICRH_TSOBI1 /* Needed for gigabit to work on TSEC 1 */ |
||||
#define CFG_SICRL (SICRL_LDP_A | SICRL_USB1) |
||||
|
||||
#define CFG_HID0_INIT 0x000000000 |
||||
|
||||
#define CFG_HID0_FINAL CFG_HID0_INIT |
||||
|
||||
#define CFG_HID2 HID2_HBE |
||||
|
||||
/* DDR @ 0x00000000 */ |
||||
#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) |
||||
#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) |
||||
|
||||
/* PCI @ 0x80000000 */ |
||||
#ifdef CONFIG_PCI |
||||
#define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) |
||||
#define CFG_IBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) |
||||
#define CFG_IBAT2L (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
||||
#define CFG_IBAT2U (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) |
||||
#else |
||||
#define CFG_IBAT1L 0 |
||||
#define CFG_IBAT1U 0 |
||||
#define CFG_IBAT2L 0 |
||||
#define CFG_IBAT2U 0 |
||||
#endif |
||||
|
||||
#ifdef CONFIG_MPC83XX_PCI2 |
||||
#define CFG_IBAT3L (CFG_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) |
||||
#define CFG_IBAT3U (CFG_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) |
||||
#define CFG_IBAT4L (CFG_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
||||
#define CFG_IBAT4U (CFG_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) |
||||
#else |
||||
#define CFG_IBAT3L 0 |
||||
#define CFG_IBAT3U 0 |
||||
#define CFG_IBAT4L 0 |
||||
#define CFG_IBAT4U 0 |
||||
#endif |
||||
|
||||
/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ |
||||
#define CFG_IBAT5L (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
||||
#define CFG_IBAT5U (CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) |
||||
|
||||
/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ |
||||
#define CFG_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE) |
||||
#define CFG_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) |
||||
|
||||
#define CFG_IBAT7L 0 |
||||
#define CFG_IBAT7U 0 |
||||
|
||||
#define CFG_DBAT0L CFG_IBAT0L |
||||
#define CFG_DBAT0U CFG_IBAT0U |
||||
#define CFG_DBAT1L CFG_IBAT1L |
||||
#define CFG_DBAT1U CFG_IBAT1U |
||||
#define CFG_DBAT2L CFG_IBAT2L |
||||
#define CFG_DBAT2U CFG_IBAT2U |
||||
#define CFG_DBAT3L CFG_IBAT3L |
||||
#define CFG_DBAT3U CFG_IBAT3U |
||||
#define CFG_DBAT4L CFG_IBAT4L |
||||
#define CFG_DBAT4U CFG_IBAT4U |
||||
#define CFG_DBAT5L CFG_IBAT5L |
||||
#define CFG_DBAT5U CFG_IBAT5U |
||||
#define CFG_DBAT6L CFG_IBAT6L |
||||
#define CFG_DBAT6U CFG_IBAT6U |
||||
#define CFG_DBAT7L CFG_IBAT7L |
||||
#define CFG_DBAT7U CFG_IBAT7U |
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ |
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
||||
#endif |
||||
|
||||
|
||||
/*
|
||||
* Environment Configuration |
||||
*/ |
||||
#define CONFIG_ENV_OVERWRITE |
||||
|
||||
#ifdef CONFIG_MPC83XX_TSEC1 |
||||
#define CONFIG_ETHADDR 00:E0:0C:00:8C:01 |
||||
#endif |
||||
|
||||
#ifdef CONFIG_MPC83XX_TSEC2 |
||||
#define CONFIG_HAS_ETH1 |
||||
#define CONFIG_ETH1ADDR 00:E0:0C:00:8C:02 |
||||
#endif |
||||
|
||||
#if 1 |
||||
#define CONFIG_IPADDR 10.82.19.159 |
||||
#define CONFIG_SERVERIP 10.82.48.106 |
||||
#define CONFIG_GATEWAYIP 10.82.19.254 |
||||
#define CONFIG_NETMASK 255.255.252.0 |
||||
#define CONFIG_NETDEV eth0 |
||||
|
||||
#define CONFIG_HOSTNAME mpc8349emitx |
||||
#define CONFIG_ROOTPATH /nfsroot0/u/timur/itx-ltib/rootfs |
||||
#define CONFIG_BOOTFILE timur/uImage |
||||
|
||||
#define CONFIG_UBOOTPATH timur/u-boot.bin |
||||
#else |
||||
#define CONFIG_IPADDR 192.168.1.253 |
||||
#define CONFIG_SERVERIP 192.168.1.1 |
||||
#define CONFIG_GATEWAYIP 192.168.1.1 |
||||
#define CONFIG_NETMASK 255.255.252.0 |
||||
#define CONFIG_NETDEV eth0 |
||||
|
||||
#define CONFIG_HOSTNAME mpc8349emitx |
||||
#define CONFIG_ROOTPATH /nfsroot/rootfs |
||||
#define CONFIG_BOOTFILE uImage |
||||
|
||||
#define CONFIG_UBOOTPATH u-boot.bin |
||||
#endif |
||||
|
||||
#define CONFIG_UBOOTSTART fe700000 |
||||
#define CONFIG_UBOOTEND fe77ffff |
||||
|
||||
#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ |
||||
|
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
#undef CONFIG_BOOTCOMMAND |
||||
#ifdef CONFIG_BOOTCOMMAND |
||||
#define CONFIG_BOOTDELAY 6 |
||||
#else |
||||
#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */ |
||||
#endif |
||||
|
||||
#define XMK_STR(x) #x |
||||
#define MK_STR(x) XMK_STR(x) |
||||
|
||||
#define CONFIG_BOOTARGS \ |
||||
"root=/dev/nfs rw" \
|
||||
" nfsroot=" MK_STR(CONFIG_SERVERIP) ":" MK_STR(CONFIG_ROOTPATH) \
|
||||
" ip=" MK_STR(CONFIG_IPADDR) ":" MK_STR(CONFIG_SERVERIP) ":" \
|
||||
MK_STR(CONFIG_GATEWAYIP) ":" MK_STR(CONFIG_NETMASK) ":" \
|
||||
MK_STR(CONFIG_HOSTNAME) ":" MK_STR(CONFIG_NETDEV) ":off" \
|
||||
" console=ttyS0," MK_STR(CONFIG_BAUDRATE) |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"netdev=" MK_STR(CONFIG_NETDEV) "\0" \
|
||||
"tftpflash=tftpboot $loadaddr " MK_STR(CONFIG_UBOOTPATH) "; " \
|
||||
"erase " MK_STR(CONFIG_UBOOTSTART) " " MK_STR(CONFIG_UBOOTEND) "; " \
|
||||
"cp.b $loadaddr " MK_STR(CONFIG_UBOOTSTART) " $filesize; " \
|
||||
"cmp.b $loadaddr " MK_STR(CONFIG_UBOOTSTART) " $filesize\0" \
|
||||
"tftpupdate=tftpboot $loadaddr " MK_STR(CONFIG_UBOOTPATH) "; " \
|
||||
"protect off FEF00000 FEF7FFFF; " \
|
||||
"erase FEF00000 FEF7FFFF; " \
|
||||
"cp.b $loadaddr FEF00000 $filesize; " \
|
||||
"protect on FEF00000 FEF7FFFF; " \
|
||||
"cmp.b $loadaddr FEF00000 $filesize\0" \
|
||||
"tftplinux=tftpboot $loadaddr $bootfile; bootm\0" \
|
||||
"copyuboot=erase " MK_STR(CONFIG_UBOOTSTART) " " MK_STR(CONFIG_UBOOTEND) "; " \
|
||||
"cp.b fef00000 " MK_STR(CONFIG_UBOOTSTART) " 80000\0" \
|
||||
"fdtaddr=400000\0" \
|
||||
"fdtfile=mpc8349emitx.dtb\0" \
|
||||
"" |
||||
|
||||
#define CONFIG_NFSBOOTCOMMAND \ |
||||
"setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=$serverip:$rootpath " \
|
||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr - $fdtaddr" |
||||
|
||||
#define CONFIG_RAMBOOTCOMMAND \ |
||||
"setenv bootargs root=/dev/ram rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $ramdiskaddr $ramdiskfile;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr $ramdiskaddr $fdtaddr" |
||||
|
||||
|
||||
#undef MK_STR |
||||
#undef XMK_STR |
||||
|
||||
#endif |
||||
@ -0,0 +1,635 @@ |
||||
/*
|
||||
* Copyright (C) 2006 Freescale Semiconductor, Inc. |
||||
* |
||||
* Dave Liu <daveliu@freescale.com> |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
#undef DEBUG |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
*/ |
||||
#define CONFIG_E300 1 /* E300 family */ |
||||
#define CONFIG_QE 1 /* Has QE */ |
||||
#define CONFIG_MPC83XX 1 /* MPC83XX family */ |
||||
#define CONFIG_MPC8360 1 /* MPC8360 CPU specific */ |
||||
#define CONFIG_MPC8360EMDS 1 /* MPC8360EMDS board specific */ |
||||
|
||||
/*
|
||||
* System Clock Setup |
||||
*/ |
||||
#ifdef CONFIG_PCISLAVE |
||||
#define CONFIG_83XX_PCICLK 66000000 /* in HZ */ |
||||
#else |
||||
#define CONFIG_83XX_CLKIN 66000000 /* in Hz */ |
||||
#endif |
||||
|
||||
#ifndef CONFIG_SYS_CLK_FREQ |
||||
#define CONFIG_SYS_CLK_FREQ 66000000 |
||||
#endif |
||||
|
||||
/*
|
||||
* Hardware Reset Configuration Word |
||||
*/ |
||||
#define CFG_HRCW_LOW (\ |
||||
HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
|
||||
HRCWL_DDR_TO_SCB_CLK_1X1 |\
|
||||
HRCWL_CSB_TO_CLKIN_4X1 |\
|
||||
HRCWL_VCO_1X2 |\
|
||||
HRCWL_CE_PLL_VCO_DIV_4 |\
|
||||
HRCWL_CE_PLL_DIV_1X1 |\
|
||||
HRCWL_CE_TO_PLL_1X6 |\
|
||||
HRCWL_CORE_TO_CSB_2X1) |
||||
|
||||
#ifdef CONFIG_PCISLAVE |
||||
#define CFG_HRCW_HIGH (\ |
||||
HRCWH_PCI_AGENT |\
|
||||
HRCWH_PCI1_ARBITER_DISABLE |\
|
||||
HRCWH_PCICKDRV_DISABLE |\
|
||||
HRCWH_CORE_ENABLE |\
|
||||
HRCWH_FROM_0XFFF00100 |\
|
||||
HRCWH_BOOTSEQ_DISABLE |\
|
||||
HRCWH_SW_WATCHDOG_DISABLE |\
|
||||
HRCWH_ROM_LOC_LOCAL_16BIT) |
||||
#else |
||||
#define CFG_HRCW_HIGH (\ |
||||
HRCWH_PCI_HOST |\
|
||||
HRCWH_PCI1_ARBITER_ENABLE |\
|
||||
HRCWH_PCICKDRV_ENABLE |\
|
||||
HRCWH_CORE_ENABLE |\
|
||||
HRCWH_FROM_0X00000100 |\
|
||||
HRCWH_BOOTSEQ_DISABLE |\
|
||||
HRCWH_SW_WATCHDOG_DISABLE |\
|
||||
HRCWH_ROM_LOC_LOCAL_16BIT) |
||||
#endif |
||||
|
||||
/*
|
||||
* System IO Config |
||||
*/ |
||||
#define CFG_SICRH 0x00000000 |
||||
#define CFG_SICRL 0x40000000 |
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ |
||||
|
||||
/*
|
||||
* IMMR new address |
||||
*/ |
||||
#define CFG_IMMR 0xE0000000 |
||||
|
||||
/*
|
||||
* DDR Setup |
||||
*/ |
||||
#define CFG_DDR_BASE 0x00000000 /* DDR is system memory */ |
||||
#define CFG_SDRAM_BASE CFG_DDR_BASE |
||||
#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE |
||||
|
||||
#define CFG_83XX_DDR_USES_CS0 |
||||
|
||||
#undef CONFIG_DDR_ECC /* only for ECC DDR module */ |
||||
#define CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ |
||||
|
||||
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ |
||||
#if defined(CONFIG_SPD_EEPROM) |
||||
/*
|
||||
* Determine DDR configuration from I2C interface. |
||||
*/ |
||||
#define SPD_EEPROM_ADDRESS 0x52 /* DDR SODIMM */ |
||||
#else |
||||
/*
|
||||
* Manually set up DDR parameters |
||||
*/ |
||||
#define CFG_DDR_SIZE 256 /* MB */ |
||||
#define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9) |
||||
#define CFG_DDR_TIMING_1 0x37344321 /* tCL-tRCD-tRP-tRAS=2.5-3-3-7 */ |
||||
#define CFG_DDR_TIMING_2 0x00000800 /* may need tuning */ |
||||
#define CFG_DDR_CONTROL 0x42008000 /* Self refresh,2T timing */ |
||||
#define CFG_DDR_MODE 0x20000162 /* DLL,normal,seq,4/2.5 */ |
||||
#define CFG_DDR_INTERVAL 0x045b0100 /* page mode */ |
||||
#endif |
||||
|
||||
/*
|
||||
* Memory test |
||||
*/ |
||||
#undef CFG_DRAM_TEST /* memory test, takes time */ |
||||
#define CFG_MEMTEST_START 0x00000000 /* memtest region */ |
||||
#define CFG_MEMTEST_END 0x00100000 |
||||
|
||||
/*
|
||||
* The reserved memory |
||||
*/ |
||||
|
||||
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ |
||||
|
||||
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) |
||||
#define CFG_RAMBOOT |
||||
#else |
||||
#undef CFG_RAMBOOT |
||||
#endif |
||||
|
||||
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
||||
#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ |
||||
|
||||
/*
|
||||
* Initial RAM Base Address Setup |
||||
*/ |
||||
#define CFG_INIT_RAM_LOCK 1 |
||||
#define CFG_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ |
||||
#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM */ |
||||
#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
|
||||
/*
|
||||
* Local Bus Configuration & Clock Setup |
||||
*/ |
||||
#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) |
||||
#define CFG_LBC_LBCR 0x00000000 |
||||
|
||||
/*
|
||||
* FLASH on the Local Bus |
||||
*/ |
||||
#define CFG_FLASH_CFI /* use the Common Flash Interface */ |
||||
#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ |
||||
#define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */ |
||||
#define CFG_FLASH_SIZE 16 /* FLASH size is 16M */ |
||||
|
||||
#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */ |
||||
#define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */ |
||||
|
||||
#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* Flash Base address */ \ |
||||
(2 << BR_PS_SHIFT) | /* 16 bit port size */ \
|
||||
BR_V) /* valid */ |
||||
#define CFG_OR0_PRELIM 0xfe006ff7 /* 16MB Flash size */ |
||||
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ |
||||
#define CFG_MAX_FLASH_SECT 128 /* sectors per device */ |
||||
|
||||
#undef CFG_FLASH_CHECKSUM |
||||
|
||||
/*
|
||||
* BCSR on the Local Bus |
||||
*/ |
||||
#define CFG_BCSR 0xF8000000 |
||||
#define CFG_LBLAWBAR1_PRELIM CFG_BCSR /* Access window base at BCSR base */ |
||||
#define CFG_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */ |
||||
|
||||
#define CFG_BR1_PRELIM (CFG_BCSR|0x00000801) /* Port size=8bit, MSEL=GPCM */ |
||||
#define CFG_OR1_PRELIM 0xFFFFE9f7 /* length 32K */ |
||||
|
||||
/*
|
||||
* SDRAM on the Local Bus |
||||
*/ |
||||
#define CFG_LBC_SDRAM_BASE 0xF0000000 /* SDRAM base address */ |
||||
#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ |
||||
|
||||
#define CFG_LB_SDRAM /* if board has SRDAM on local bus */ |
||||
|
||||
#ifdef CFG_LB_SDRAM |
||||
#define CFG_LBLAWBAR2_PRELIM CFG_LBC_SDRAM_BASE |
||||
#define CFG_LBLAWAR2_PRELIM 0x80000019 /* 64MB */ |
||||
|
||||
/*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */ |
||||
/*
|
||||
* Base Register 2 and Option Register 2 configure SDRAM. |
||||
* The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. |
||||
* |
||||
* For BR2, need: |
||||
* Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 |
||||
* port size = 32-bits = BR2[19:20] = 11 |
||||
* no parity checking = BR2[21:22] = 00 |
||||
* SDRAM for MSEL = BR2[24:26] = 011 |
||||
* Valid = BR[31] = 1 |
||||
* |
||||
* 0 4 8 12 16 20 24 28 |
||||
* 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 |
||||
* |
||||
* CFG_LBC_SDRAM_BASE should be masked and OR'ed into |
||||
* the top 17 bits of BR2. |
||||
*/ |
||||
|
||||
#define CFG_BR2_PRELIM 0xf0001861 /*Port size=32bit, MSEL=SDRAM */ |
||||
|
||||
/*
|
||||
* The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. |
||||
* |
||||
* For OR2, need: |
||||
* 64MB mask for AM, OR2[0:7] = 1111 1100 |
||||
* XAM, OR2[17:18] = 11 |
||||
* 9 columns OR2[19-21] = 010 |
||||
* 13 rows OR2[23-25] = 100 |
||||
* EAD set for extra time OR[31] = 1 |
||||
* |
||||
* 0 4 8 12 16 20 24 28 |
||||
* 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 |
||||
*/ |
||||
|
||||
#define CFG_OR2_PRELIM 0xfc006901 |
||||
|
||||
#define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ |
||||
#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */ |
||||
|
||||
/*
|
||||
* LSDMR masks |
||||
*/ |
||||
#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) |
||||
#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) |
||||
#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) |
||||
#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) |
||||
#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) |
||||
#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) |
||||
#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) |
||||
#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) |
||||
|
||||
#define CFG_LBC_LSDMR_COMMON 0x0063b723 |
||||
|
||||
/*
|
||||
* SDRAM Controller configuration sequence. |
||||
*/ |
||||
#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ |
||||
| CFG_LBC_LSDMR_OP_PCHALL) |
||||
#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ |
||||
| CFG_LBC_LSDMR_OP_ARFRSH) |
||||
#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ |
||||
| CFG_LBC_LSDMR_OP_ARFRSH) |
||||
#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ |
||||
| CFG_LBC_LSDMR_OP_MRW) |
||||
#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ |
||||
| CFG_LBC_LSDMR_OP_NORMAL) |
||||
|
||||
#endif |
||||
|
||||
/*
|
||||
* Windows to access PIB via local bus |
||||
*/ |
||||
#define CFG_LBLAWBAR3_PRELIM 0xf8008000 /* windows base 0xf8008000 */ |
||||
#define CFG_LBLAWAR3_PRELIM 0x8000000f /* windows size 64KB */ |
||||
|
||||
/*
|
||||
* CS4 on Local Bus, to PIB |
||||
*/ |
||||
#define CFG_BR4_PRELIM 0xf8008801 /* CS4 base address at 0xf8008000 */ |
||||
#define CFG_OR4_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */ |
||||
|
||||
/*
|
||||
* CS5 on Local Bus, to PIB |
||||
*/ |
||||
#define CFG_BR5_PRELIM 0xf8010801 /* CS5 base address at 0xf8010000 */ |
||||
#define CFG_OR5_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */ |
||||
|
||||
/*
|
||||
* Serial Port |
||||
*/ |
||||
#define CONFIG_CONS_INDEX 1 |
||||
#undef CONFIG_SERIAL_SOFTWARE_FIFO |
||||
#define CFG_NS16550 |
||||
#define CFG_NS16550_SERIAL |
||||
#define CFG_NS16550_REG_SIZE 1 |
||||
#define CFG_NS16550_CLK get_bus_freq(0) |
||||
|
||||
#define CFG_BAUDRATE_TABLE \ |
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
||||
|
||||
#define CFG_NS16550_COM1 (CFG_IMMR+0x4500) |
||||
#define CFG_NS16550_COM2 (CFG_IMMR+0x4600) |
||||
|
||||
/* Use the HUSH parser */ |
||||
#define CFG_HUSH_PARSER |
||||
#ifdef CFG_HUSH_PARSER |
||||
#define CFG_PROMPT_HUSH_PS2 "> " |
||||
#endif |
||||
|
||||
/* pass open firmware flat tree */ |
||||
#define CONFIG_OF_FLAT_TREE 1 |
||||
#define CONFIG_OF_BOARD_SETUP 1 |
||||
|
||||
/* maximum size of the flat tree (8K) */ |
||||
#define OF_FLAT_TREE_MAX_SIZE 8192 |
||||
|
||||
#define OF_CPU "PowerPC,8360@0" |
||||
#define OF_SOC "soc8360@e0000000" |
||||
#define OF_TBCLK (bd->bi_busfreq / 4) |
||||
#define OF_STDOUT_PATH "/soc8360@e0000000/serial@4500" |
||||
|
||||
/* I2C */ |
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */ |
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
||||
#define CONFIG_FSL_I2C |
||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ |
||||
#define CFG_I2C_SLAVE 0x7F |
||||
#define CFG_I2C_NOPROBES {0x52} /* Don't probe these addrs */ |
||||
#define CFG_I2C_OFFSET 0x3000 |
||||
#define CFG_I2C2_OFFSET 0x3100 |
||||
|
||||
/*
|
||||
* Config on-board RTC |
||||
*/ |
||||
#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ |
||||
#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ |
||||
|
||||
/*
|
||||
* General PCI |
||||
* Addresses are mapped 1-1. |
||||
*/ |
||||
#define CFG_PCI_MEM_BASE 0x80000000 |
||||
#define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BASE |
||||
#define CFG_PCI_MEM_SIZE 0x10000000 /* 256M */ |
||||
#define CFG_PCI_MMIO_BASE 0x90000000 |
||||
#define CFG_PCI_MMIO_PHYS CFG_PCI_MMIO_BASE |
||||
#define CFG_PCI_MMIO_SIZE 0x10000000 /* 256M */ |
||||
#define CFG_PCI_IO_BASE 0xE0300000 |
||||
#define CFG_PCI_IO_PHYS 0xE0300000 |
||||
#define CFG_PCI_IO_SIZE 0x100000 /* 1M */ |
||||
|
||||
#define CFG_PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE |
||||
#define CFG_PCI_SLV_MEM_BUS 0x00000000 |
||||
#define CFG_PCI_SLV_MEM_SIZE 0x80000000 |
||||
|
||||
|
||||
#ifdef CONFIG_PCI |
||||
|
||||
#define CONFIG_NET_MULTI |
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */ |
||||
|
||||
#undef CONFIG_EEPRO100 |
||||
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
||||
#define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ |
||||
|
||||
#endif /* CONFIG_PCI */ |
||||
|
||||
|
||||
#ifndef CONFIG_NET_MULTI |
||||
#define CONFIG_NET_MULTI 1 |
||||
#endif |
||||
|
||||
/*
|
||||
* QE UEC ethernet configuration |
||||
*/ |
||||
#define CONFIG_UEC_ETH |
||||
#define CONFIG_ETHPRIME "Freescale GETH" |
||||
#define CONFIG_PHY_MODE_NEED_CHANGE |
||||
|
||||
#define CONFIG_UEC_ETH1 /* GETH1 */ |
||||
|
||||
#ifdef CONFIG_UEC_ETH1 |
||||
#define CFG_UEC1_UCC_NUM 0 /* UCC1 */ |
||||
#define CFG_UEC1_RX_CLK QE_CLK_NONE |
||||
#define CFG_UEC1_TX_CLK QE_CLK9 |
||||
#define CFG_UEC1_ETH_TYPE GIGA_ETH |
||||
#define CFG_UEC1_PHY_ADDR 0 |
||||
#define CFG_UEC1_INTERFACE_MODE ENET_1000_GMII |
||||
#endif |
||||
|
||||
#define CONFIG_UEC_ETH2 /* GETH2 */ |
||||
|
||||
#ifdef CONFIG_UEC_ETH2 |
||||
#define CFG_UEC2_UCC_NUM 1 /* UCC2 */ |
||||
#define CFG_UEC2_RX_CLK QE_CLK_NONE |
||||
#define CFG_UEC2_TX_CLK QE_CLK4 |
||||
#define CFG_UEC2_ETH_TYPE GIGA_ETH |
||||
#define CFG_UEC2_PHY_ADDR 1 |
||||
#define CFG_UEC2_INTERFACE_MODE ENET_1000_GMII |
||||
#endif |
||||
|
||||
/*
|
||||
* Environment |
||||
*/ |
||||
|
||||
#ifndef CFG_RAMBOOT |
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) |
||||
#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ |
||||
#define CFG_ENV_SIZE 0x2000 |
||||
#else |
||||
#define CFG_NO_FLASH 1 /* Flash is not usable now */ |
||||
#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) |
||||
#define CFG_ENV_SIZE 0x2000 |
||||
#endif |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
||||
|
||||
#if defined(CFG_RAMBOOT) |
||||
#if defined(CONFIG_PCI) |
||||
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ |
||||
| CFG_CMD_PING \
|
||||
| CFG_CMD_ASKENV \
|
||||
| CFG_CMD_PCI \
|
||||
| CFG_CMD_I2C) \
|
||||
& \
|
||||
~(CFG_CMD_ENV \
|
||||
| CFG_CMD_LOADS)) |
||||
#else |
||||
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ |
||||
| CFG_CMD_PING \
|
||||
| CFG_CMD_ASKENV \
|
||||
| CFG_CMD_I2C) \
|
||||
& \
|
||||
~(CFG_CMD_ENV \
|
||||
| CFG_CMD_LOADS)) |
||||
#endif |
||||
#else |
||||
#if defined(CONFIG_PCI) |
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ |
||||
| CFG_CMD_PCI \
|
||||
| CFG_CMD_PING \
|
||||
| CFG_CMD_ASKENV \
|
||||
| CFG_CMD_I2C) |
||||
#else |
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ |
||||
| CFG_CMD_PING \
|
||||
| CFG_CMD_ASKENV \
|
||||
| CFG_CMD_I2C ) |
||||
#endif |
||||
#endif |
||||
|
||||
#include <cmd_confdefs.h> |
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_LOAD_ADDR 0x2000000 /* default load address */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
/*
|
||||
* Core HID Setup |
||||
*/ |
||||
#define CFG_HID0_INIT 0x000000000 |
||||
#define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK |
||||
#define CFG_HID2 HID2_HBE |
||||
|
||||
/*
|
||||
* Cache Config |
||||
*/ |
||||
#define CFG_DCACHE_SIZE 32768 |
||||
#define CFG_CACHELINE_SIZE 32 |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*
|
||||
* MMU Setup |
||||
*/ |
||||
|
||||
/* DDR: cache cacheable */ |
||||
#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) |
||||
#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) |
||||
#define CFG_DBAT0L CFG_IBAT0L |
||||
#define CFG_DBAT0U CFG_IBAT0U |
||||
|
||||
/* IMMRBAR & PCI IO: cache-inhibit and guarded */ |
||||
#define CFG_IBAT1L (CFG_IMMR | BATL_PP_10 | \ |
||||
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
||||
#define CFG_IBAT1U (CFG_IMMR | BATU_BL_4M | BATU_VS | BATU_VP) |
||||
#define CFG_DBAT1L CFG_IBAT1L |
||||
#define CFG_DBAT1U CFG_IBAT1U |
||||
|
||||
/* BCSR: cache-inhibit and guarded */ |
||||
#define CFG_IBAT2L (CFG_BCSR | BATL_PP_10 | \ |
||||
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
||||
#define CFG_IBAT2U (CFG_BCSR | BATU_BL_128K | BATU_VS | BATU_VP) |
||||
#define CFG_DBAT2L CFG_IBAT2L |
||||
#define CFG_DBAT2U CFG_IBAT2U |
||||
|
||||
/* FLASH: icache cacheable, but dcache-inhibit and guarded */ |
||||
#define CFG_IBAT3L (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) |
||||
#define CFG_IBAT3U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP) |
||||
#define CFG_DBAT3L (CFG_FLASH_BASE | BATL_PP_10 | \ |
||||
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
||||
#define CFG_DBAT3U CFG_IBAT3U |
||||
|
||||
/* Local bus SDRAM: cacheable */ |
||||
#define CFG_IBAT4L (CFG_LBC_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) |
||||
#define CFG_IBAT4U (CFG_LBC_SDRAM_BASE | BATU_BL_64M | BATU_VS | BATU_VP) |
||||
#define CFG_DBAT4L CFG_IBAT4L |
||||
#define CFG_DBAT4U CFG_IBAT4U |
||||
|
||||
/* Stack in dcache: cacheable, no memory coherence */ |
||||
#define CFG_IBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_10) |
||||
#define CFG_IBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) |
||||
#define CFG_DBAT5L CFG_IBAT5L |
||||
#define CFG_DBAT5U CFG_IBAT5U |
||||
|
||||
#ifdef CONFIG_PCI |
||||
/* PCI MEM space: cacheable */ |
||||
#define CFG_IBAT6L (CFG_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) |
||||
#define CFG_IBAT6U (CFG_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) |
||||
#define CFG_DBAT6L CFG_IBAT6L |
||||
#define CFG_DBAT6U CFG_IBAT6U |
||||
/* PCI MMIO space: cache-inhibit and guarded */ |
||||
#define CFG_IBAT7L (CFG_PCI_MMIO_PHYS | BATL_PP_10 | \ |
||||
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
||||
#define CFG_IBAT7U (CFG_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) |
||||
#define CFG_DBAT7L CFG_IBAT7L |
||||
#define CFG_DBAT7U CFG_IBAT7U |
||||
#else |
||||
#define CFG_IBAT6L (0) |
||||
#define CFG_IBAT6U (0) |
||||
#define CFG_IBAT7L (0) |
||||
#define CFG_IBAT7U (0) |
||||
#define CFG_DBAT6L CFG_IBAT6L |
||||
#define CFG_DBAT6U CFG_IBAT6U |
||||
#define CFG_DBAT7L CFG_IBAT7L |
||||
#define CFG_DBAT7U CFG_IBAT7U |
||||
#endif |
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ |
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
||||
#endif |
||||
|
||||
/*
|
||||
* Environment Configuration |
||||
*/ |
||||
|
||||
#define CONFIG_ENV_OVERWRITE |
||||
|
||||
#if defined(CONFIG_UEC_ETH) |
||||
#define CONFIG_ETHADDR 00:04:9f:ef:01:01 |
||||
#define CONFIG_HAS_ETH1 |
||||
#define CONFIG_ETH1ADDR 00:04:9f:ef:01:02 |
||||
#endif |
||||
|
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ |
||||
|
||||
#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ |
||||
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"netdev=eth0\0" \
|
||||
"consoledev=ttyS0\0" \
|
||||
"ramdiskaddr=1000000\0" \
|
||||
"ramdiskfile=ramfs.83xx\0" \
|
||||
"fdtaddr=400000\0" \
|
||||
"fdtfile=mpc8349emds.dtb\0" \
|
||||
"" |
||||
|
||||
#define CONFIG_NFSBOOTCOMMAND \ |
||||
"setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=$serverip:$rootpath " \
|
||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr - $fdtaddr" |
||||
|
||||
#define CONFIG_RAMBOOTCOMMAND \ |
||||
"setenv bootargs root=/dev/ram rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $ramdiskaddr $ramdiskfile;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr $ramdiskaddr $fdtaddr" |
||||
|
||||
|
||||
#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
Loading…
Reference in new issue