Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>master
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b491d9757d
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/*
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* LPC32xx Ethernet MAC interface driver |
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* |
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* (C) Copyright 2014 DENX Software Engineering GmbH |
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* Written-by: Albert ARIBAUD - 3ADEV <albert.aribaud@3adev.fr> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <net.h> |
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#include <malloc.h> |
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#include <miiphy.h> |
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#include <asm/io.h> |
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#include <asm/errno.h> |
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#include <asm/types.h> |
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#include <asm/system.h> |
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#include <asm/byteorder.h> |
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#include <asm/arch/cpu.h> |
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#include <asm/arch/config.h> |
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/*
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* Notes: |
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* |
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* 1. Unless specified otherwise, all references to tables or paragraphs |
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* are to UM10326, "LPC32x0 and LPC32x0/01 User manual". |
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* |
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* 2. Only bitfield masks/values which are actually used by the driver |
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* are defined. |
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*/ |
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/* a single RX descriptor. The controller has an array of these */ |
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struct lpc32xx_eth_rxdesc { |
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u32 packet; /* Receive packet pointer */ |
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u32 control; /* Descriptor command status */ |
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}; |
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#define LPC32XX_ETH_RX_DESC_SIZE (sizeof(struct lpc32xx_eth_rxdesc)) |
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/* RX control bitfields/masks (see Table 330) */ |
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#define LPC32XX_ETH_RX_CTRL_SIZE_MASK 0x000007FF |
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#define LPC32XX_ETH_RX_CTRL_UNUSED 0x7FFFF800 |
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#define LPC32XX_ETH_RX_CTRL_INTERRUPT 0x80000000 |
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/* a single RX status. The controller has an array of these */ |
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struct lpc32xx_eth_rxstat { |
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u32 statusinfo; /* Transmit Descriptor status */ |
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u32 statushashcrc; /* Transmit Descriptor CRCs */ |
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}; |
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#define LPC32XX_ETH_RX_STAT_SIZE (sizeof(struct lpc32xx_eth_rxstat)) |
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/* RX statusinfo bitfields/masks (see Table 333) */ |
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#define RX_STAT_RXSIZE 0x000007FF |
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/* Helper: OR of all errors except RANGE */ |
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#define RX_STAT_ERRORS 0x1B800000 |
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/* a single TX descriptor. The controller has an array of these */ |
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struct lpc32xx_eth_txdesc { |
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u32 packet; /* Transmit packet pointer */ |
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u32 control; /* Descriptor control */ |
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}; |
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#define LPC32XX_ETH_TX_DESC_SIZE (sizeof(struct lpc32xx_eth_txdesc)) |
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/* TX control bitfields/masks (see Table 335) */ |
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#define TX_CTRL_TXSIZE 0x000007FF |
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#define TX_CTRL_LAST 0x40000000 |
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/* a single TX status. The controller has an array of these */ |
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struct lpc32xx_eth_txstat { |
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u32 statusinfo; /* Transmit Descriptor status */ |
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}; |
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#define LPC32XX_ETH_TX_STAT_SIZE (sizeof(struct lpc32xx_eth_txstat)) |
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/* Ethernet MAC interface registers (see Table 283) */ |
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struct lpc32xx_eth_registers { |
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/* MAC registers - 0x3106_0000 to 0x3106_01FC */ |
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u32 mac1; /* MAC configuration register 1 */ |
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u32 mac2; /* MAC configuration register 2 */ |
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u32 ipgt; /* Back-to-back Inter-Packet Gap reg. */ |
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u32 ipgr; /* Non-back-to-back IPG register */ |
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u32 clrt; /* Collision Window / Retry register */ |
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u32 maxf; /* Maximum Frame register */ |
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u32 supp; /* Phy Support register */ |
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u32 test; |
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u32 mcfg; /* MII management configuration reg. */ |
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u32 mcmd; /* MII management command register */ |
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u32 madr; /* MII management address register */ |
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u32 mwtd; /* MII management wite data register */ |
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u32 mrdd; /* MII management read data register */ |
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u32 mind; /* MII management indicators register */ |
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u32 reserved1[2]; |
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u32 sa0; /* Station address register 0 */ |
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u32 sa1; /* Station address register 1 */ |
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u32 sa2; /* Station address register 2 */ |
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u32 reserved2[45]; |
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/* Control registers */ |
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u32 command; |
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u32 status; |
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u32 rxdescriptor; |
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u32 rxstatus; |
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u32 rxdescriptornumber; /* actually, number MINUS ONE */ |
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u32 rxproduceindex; /* head of rx desc fifo */ |
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u32 rxconsumeindex; /* tail of rx desc fifo */ |
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u32 txdescriptor; |
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u32 txstatus; |
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u32 txdescriptornumber; /* actually, number MINUS ONE */ |
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u32 txproduceindex; /* head of rx desc fifo */ |
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u32 txconsumeindex; /* tail of rx desc fifo */ |
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u32 reserved3[10]; |
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u32 tsv0; /* Transmit status vector register 0 */ |
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u32 tsv1; /* Transmit status vector register 1 */ |
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u32 rsv; /* Receive status vector register */ |
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u32 reserved4[3]; |
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u32 flowcontrolcounter; |
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u32 flowcontrolstatus; |
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u32 reserved5[34]; |
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/* RX filter registers - 0x3106_0200 to 0x3106_0FDC */ |
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u32 rxfilterctrl; |
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u32 rxfilterwolstatus; |
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u32 rxfilterwolclear; |
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u32 reserved6; |
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u32 hashfilterl; |
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u32 hashfilterh; |
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u32 reserved7[882]; |
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/* Module control registers - 0x3106_0FE0 to 0x3106_0FF8 */ |
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u32 intstatus; /* Interrupt status register */ |
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u32 intenable; |
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u32 intclear; |
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u32 intset; |
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u32 reserved8; |
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u32 powerdown; |
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u32 reserved9; |
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}; |
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/* MAC1 register bitfields/masks and offsets (see Table 283) */ |
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#define MAC1_RECV_ENABLE 0x00000001 |
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#define MAC1_PASS_ALL_RX_FRAMES 0x00000002 |
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#define MAC1_SOFT_RESET 0x00008000 |
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/* Helper: general reset */ |
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#define MAC1_RESETS 0x0000CF00 |
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/* MAC2 register bitfields/masks and offsets (see Table 284) */ |
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#define MAC2_FULL_DUPLEX 0x00000001 |
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#define MAC2_CRC_ENABLE 0x00000010 |
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#define MAC2_PAD_CRC_ENABLE 0x00000020 |
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/* SUPP register bitfields/masks and offsets (see Table 290) */ |
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#define SUPP_SPEED 0x00000100 |
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/* MCFG register bitfields/masks and offsets (see Table 292) */ |
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#define MCFG_CLOCK_SELECT_MASK 0x0000001C |
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/* divide clock by 28 (see Table 293) */ |
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#define MCFG_CLOCK_SELECT_DIV28 0x0000001C |
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/* MADR register bitfields/masks and offsets (see Table 295) */ |
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#define MADR_REG_MASK 0x0000001F |
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#define MADR_PHY_MASK 0x00001F00 |
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#define MADR_REG_OFFSET 0 |
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#define MADR_PHY_OFFSET 8 |
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/* MIND register bitfields/masks (see Table 298) */ |
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#define MIND_BUSY 0x00000001 |
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/* COMMAND register bitfields/masks and offsets (see Table 283) */ |
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#define COMMAND_RXENABLE 0x00000001 |
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#define COMMAND_TXENABLE 0x00000002 |
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#define COMMAND_PASSRUNTFRAME 0x00000040 |
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#define COMMAND_FULL_DUPLEX 0x00000400 |
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/* Helper: general reset */ |
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#define COMMAND_RESETS 0x0000001C |
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/* STATUS register bitfields/masks and offsets (see Table 283) */ |
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#define STATUS_RXSTATUS 0x00000001 |
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#define STATUS_TXSTATUS 0x00000002 |
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/* RXFILTERCTRL register bitfields/masks (see Table 319) */ |
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#define RXFILTERCTRL_ACCEPTBROADCAST 0x00000002 |
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#define RXFILTERCTRL_ACCEPTPERFECT 0x00000020 |
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/* Buffers and descriptors */ |
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#define ATTRS(n) __aligned(n) |
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#define TX_BUF_COUNT 4 |
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#define RX_BUF_COUNT 4 |
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struct lpc32xx_eth_buffers { |
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ATTRS(4) struct lpc32xx_eth_txdesc tx_desc[TX_BUF_COUNT]; |
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ATTRS(4) struct lpc32xx_eth_txstat tx_stat[TX_BUF_COUNT]; |
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ATTRS(PKTALIGN) u8 tx_buf[TX_BUF_COUNT*PKTSIZE_ALIGN]; |
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ATTRS(4) struct lpc32xx_eth_rxdesc rx_desc[RX_BUF_COUNT]; |
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ATTRS(8) struct lpc32xx_eth_rxstat rx_stat[RX_BUF_COUNT]; |
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ATTRS(PKTALIGN) u8 rx_buf[RX_BUF_COUNT*PKTSIZE_ALIGN]; |
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}; |
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/* port device data struct */ |
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struct lpc32xx_eth_device { |
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struct eth_device dev; |
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struct lpc32xx_eth_registers *regs; |
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struct lpc32xx_eth_buffers *bufs; |
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}; |
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#define LPC32XX_ETH_DEVICE_SIZE (sizeof(struct lpc32xx_eth_device)) |
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/* generic macros */ |
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#define to_lpc32xx_eth(_d) container_of(_d, struct lpc32xx_eth_device, dev) |
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/* timeout for MII polling */ |
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#define MII_TIMEOUT 10000000 |
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/* limits for PHY and register addresses */ |
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#define MII_MAX_REG (MADR_REG_MASK >> MADR_REG_OFFSET) |
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#define MII_MAX_PHY (MADR_PHY_MASK >> MADR_PHY_OFFSET) |
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DECLARE_GLOBAL_DATA_PTR; |
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#if defined(CONFIG_PHYLIB) || defined(CONFIG_MII) || defined(CONFIG_CMD_MII) |
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/*
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* mii_reg_read - miiphy_read callback function. |
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* |
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* Returns 16bit phy register value, or 0xffff on error |
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*/ |
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static int mii_reg_read(const char *devname, u8 phy_adr, u8 reg_ofs, u16 *data) |
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{ |
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struct eth_device *dev = eth_get_dev_by_name(devname); |
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struct lpc32xx_eth_device *dlpc32xx_eth = to_lpc32xx_eth(dev); |
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struct lpc32xx_eth_registers *regs = dlpc32xx_eth->regs; |
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u32 mind_reg; |
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u32 timeout; |
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/* check parameters */ |
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if (phy_adr > MII_MAX_PHY) { |
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printf("%s:%u: Invalid PHY address %d\n", |
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__func__, __LINE__, phy_adr); |
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return -EFAULT; |
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} |
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if (reg_ofs > MII_MAX_REG) { |
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printf("%s:%u: Invalid register offset %d\n", |
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__func__, __LINE__, reg_ofs); |
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return -EFAULT; |
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} |
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/* write the phy and reg addressse into the MII address reg */ |
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writel((phy_adr << MADR_PHY_OFFSET) | (reg_ofs << MADR_REG_OFFSET), |
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®s->madr); |
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/* write 1 to the MII command register to cause a read */ |
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writel(1, ®s->mcmd); |
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/* wait till the MII is not busy */ |
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timeout = MII_TIMEOUT; |
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do { |
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/* read MII indicators register */ |
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mind_reg = readl(®s->mind); |
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if (--timeout == 0) |
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break; |
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} while (mind_reg & MIND_BUSY); |
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/* write 0 to the MII command register to finish the read */ |
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writel(0, ®s->mcmd); |
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if (timeout == 0) { |
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printf("%s:%u: MII busy timeout\n", __func__, __LINE__); |
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return -EFAULT; |
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} |
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*data = (u16) readl(®s->mrdd); |
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debug("%s:(adr %d, off %d) => %04x\n", __func__, phy_adr, |
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reg_ofs, *data); |
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return 0; |
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} |
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/*
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* mii_reg_write - imiiphy_write callback function. |
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* |
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* Returns 0 if write succeed, -EINVAL on bad parameters |
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* -ETIME on timeout |
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*/ |
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static int mii_reg_write(const char *devname, u8 phy_adr, u8 reg_ofs, u16 data) |
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{ |
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struct eth_device *dev = eth_get_dev_by_name(devname); |
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struct lpc32xx_eth_device *dlpc32xx_eth = to_lpc32xx_eth(dev); |
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struct lpc32xx_eth_registers *regs = dlpc32xx_eth->regs; |
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u32 mind_reg; |
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u32 timeout; |
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/* check parameters */ |
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if (phy_adr > MII_MAX_PHY) { |
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printf("%s:%u: Invalid PHY address %d\n", |
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__func__, __LINE__, phy_adr); |
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return -EFAULT; |
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} |
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if (reg_ofs > MII_MAX_REG) { |
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printf("%s:%u: Invalid register offset %d\n", |
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__func__, __LINE__, reg_ofs); |
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return -EFAULT; |
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} |
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/* wait till the MII is not busy */ |
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timeout = MII_TIMEOUT; |
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do { |
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/* read MII indicators register */ |
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mind_reg = readl(®s->mind); |
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if (--timeout == 0) |
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break; |
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} while (mind_reg & MIND_BUSY); |
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if (timeout == 0) { |
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printf("%s:%u: MII busy timeout\n", __func__, |
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__LINE__); |
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return -EFAULT; |
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} |
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/* write the phy and reg addressse into the MII address reg */ |
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writel((phy_adr << MADR_PHY_OFFSET) | (reg_ofs << MADR_REG_OFFSET), |
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®s->madr); |
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/* write data to the MII write register */ |
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writel(data, ®s->mwtd); |
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/*debug("%s:(adr %d, off %d) <= %04x\n", __func__, phy_adr,
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reg_ofs, data);*/ |
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return 0; |
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} |
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#endif |
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#if defined(CONFIG_PHYLIB) |
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int lpc32xx_eth_phy_read(struct mii_dev *bus, int phy_addr, int dev_addr, |
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int reg_addr) |
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{ |
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u16 data; |
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int ret; |
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ret = mii_reg_read(bus->name, phy_addr, reg_addr, &data); |
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if (ret) |
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return ret; |
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return data; |
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} |
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int lpc32xx_eth_phy_write(struct mii_dev *bus, int phy_addr, int dev_addr, |
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int reg_addr, u16 data) |
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{ |
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return mii_reg_write(bus->name, phy_addr, reg_addr, data); |
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} |
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#endif |
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/*
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* Locate buffers in SRAM at 0x00001000 to avoid cache issues and |
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* maximize throughput. |
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*/ |
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#define LPC32XX_ETH_BUFS 0x00001000 |
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static struct lpc32xx_eth_device lpc32xx_eth = { |
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.regs = (struct lpc32xx_eth_registers *)LPC32XX_ETH_BASE, |
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.bufs = (struct lpc32xx_eth_buffers *)LPC32XX_ETH_BUFS |
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}; |
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#define TX_TIMEOUT 10000 |
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static int lpc32xx_eth_send(struct eth_device *dev, void *dataptr, int datasize) |
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{ |
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struct lpc32xx_eth_device *lpc32xx_eth_device = |
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container_of(dev, struct lpc32xx_eth_device, dev); |
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struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs; |
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struct lpc32xx_eth_buffers *bufs = lpc32xx_eth_device->bufs; |
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int timeout, tx_index; |
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/* time out if transmit descriptor array remains full too long */ |
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timeout = TX_TIMEOUT; |
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while ((readl(®s->status) & STATUS_TXSTATUS) && |
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(readl(®s->txconsumeindex) |
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== readl(®s->txproduceindex))) { |
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if (timeout-- == 0) |
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return -1; |
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} |
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/* determine next transmit packet index to use */ |
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tx_index = readl(®s->txproduceindex); |
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/* set up transmit packet */ |
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writel((u32)dataptr, &bufs->tx_desc[tx_index].packet); |
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writel(TX_CTRL_LAST | ((datasize - 1) & TX_CTRL_TXSIZE), |
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&bufs->tx_desc[tx_index].control); |
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writel(0, &bufs->tx_stat[tx_index].statusinfo); |
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/* pass transmit packet to DMA engine */ |
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tx_index = (tx_index + 1) % TX_BUF_COUNT; |
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writel(tx_index, ®s->txproduceindex); |
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/* transmission succeeded */ |
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return 0; |
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} |
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#define RX_TIMEOUT 1000000 |
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static int lpc32xx_eth_recv(struct eth_device *dev) |
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{ |
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struct lpc32xx_eth_device *lpc32xx_eth_device = |
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container_of(dev, struct lpc32xx_eth_device, dev); |
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struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs; |
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struct lpc32xx_eth_buffers *bufs = lpc32xx_eth_device->bufs; |
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int timeout, rx_index; |
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/* time out if receive descriptor array remains empty too long */ |
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timeout = RX_TIMEOUT; |
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while (readl(®s->rxproduceindex) == readl(®s->rxconsumeindex)) { |
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if (timeout-- == 0) |
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return -1; |
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} |
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/* determine next receive packet index to use */ |
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rx_index = readl(®s->rxconsumeindex); |
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/* if data was valid, pass it on */ |
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if (!(bufs->rx_stat[rx_index].statusinfo & RX_STAT_ERRORS)) |
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NetReceive(&(bufs->rx_buf[rx_index*PKTSIZE_ALIGN]), |
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(bufs->rx_stat[rx_index].statusinfo |
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& RX_STAT_RXSIZE) + 1); |
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/* pass receive slot back to DMA engine */ |
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rx_index = (rx_index + 1) % RX_BUF_COUNT; |
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writel(rx_index, ®s->rxconsumeindex); |
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/* reception successful */ |
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return 0; |
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} |
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static int lpc32xx_eth_write_hwaddr(struct eth_device *dev) |
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{ |
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struct lpc32xx_eth_device *lpc32xx_eth_device = |
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container_of(dev, struct lpc32xx_eth_device, dev); |
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struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs; |
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/* Save station address */ |
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writel((unsigned long) (dev->enetaddr[0] | |
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(dev->enetaddr[1] << 8)), ®s->sa2); |
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writel((unsigned long) (dev->enetaddr[2] | |
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(dev->enetaddr[3] << 8)), ®s->sa1); |
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writel((unsigned long) (dev->enetaddr[4] | |
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(dev->enetaddr[5] << 8)), ®s->sa0); |
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return 0; |
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} |
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static int lpc32xx_eth_init(struct eth_device *dev) |
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{ |
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struct lpc32xx_eth_device *lpc32xx_eth_device = |
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container_of(dev, struct lpc32xx_eth_device, dev); |
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struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs; |
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struct lpc32xx_eth_buffers *bufs = lpc32xx_eth_device->bufs; |
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int index; |
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/* Release SOFT reset to let MII talk to PHY */ |
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clrbits_le32(®s->mac1, MAC1_SOFT_RESET); |
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/* Configure Full/Half Duplex mode */ |
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if (miiphy_duplex(dev->name, CONFIG_PHY_ADDR) == FULL) { |
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setbits_le32(®s->mac2, MAC2_FULL_DUPLEX); |
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setbits_le32(®s->command, COMMAND_FULL_DUPLEX); |
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writel(0x15, ®s->ipgt); |
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} else { |
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writel(0x12, ®s->ipgt); |
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} |
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/* Configure 100MBit/10MBit mode */ |
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if (miiphy_speed(dev->name, CONFIG_PHY_ADDR) == _100BASET) |
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writel(SUPP_SPEED, ®s->supp); |
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else |
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writel(0, ®s->supp); |
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/* Initial MAC initialization */ |
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writel(MAC1_PASS_ALL_RX_FRAMES, ®s->mac1); |
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writel(MAC2_PAD_CRC_ENABLE | MAC2_CRC_ENABLE, ®s->mac2); |
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writel(PKTSIZE_ALIGN, ®s->maxf); |
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/* Retries: 15 (0xF). Collision window: 57 (0x37). */ |
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writel(0x370F, ®s->clrt); |
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/* Set IP gap pt 2 to default 0x12 but pt 1 to non-default 0 */ |
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writel(0x0012, ®s->ipgr); |
||||
|
||||
/* pass runt (smaller than 64 bytes) frames */ |
||||
writel(COMMAND_PASSRUNTFRAME, ®s->command); |
||||
|
||||
/* Save station address */ |
||||
writel((unsigned long) (dev->enetaddr[0] | |
||||
(dev->enetaddr[1] << 8)), ®s->sa2); |
||||
writel((unsigned long) (dev->enetaddr[2] | |
||||
(dev->enetaddr[3] << 8)), ®s->sa1); |
||||
writel((unsigned long) (dev->enetaddr[4] | |
||||
(dev->enetaddr[5] << 8)), ®s->sa0); |
||||
|
||||
/* set up transmit buffers */ |
||||
for (index = 0; index < TX_BUF_COUNT; index++) { |
||||
bufs->tx_desc[index].control = 0; |
||||
bufs->tx_stat[index].statusinfo = 0; |
||||
} |
||||
writel((u32)(&bufs->tx_desc), (u32 *)®s->txdescriptor); |
||||
writel((u32)(&bufs->tx_stat), ®s->txstatus); |
||||
writel(TX_BUF_COUNT-1, ®s->txdescriptornumber); |
||||
|
||||
/* set up receive buffers */ |
||||
for (index = 0; index < RX_BUF_COUNT; index++) { |
||||
bufs->rx_desc[index].packet = |
||||
(u32) (bufs->rx_buf+index*PKTSIZE_ALIGN); |
||||
bufs->rx_desc[index].control = PKTSIZE_ALIGN - 1; |
||||
bufs->rx_stat[index].statusinfo = 0; |
||||
bufs->rx_stat[index].statushashcrc = 0; |
||||
} |
||||
writel((u32)(&bufs->rx_desc), ®s->rxdescriptor); |
||||
writel((u32)(&bufs->rx_stat), ®s->rxstatus); |
||||
writel(RX_BUF_COUNT-1, ®s->rxdescriptornumber); |
||||
|
||||
/* Enable broadcast and matching address packets */ |
||||
writel(RXFILTERCTRL_ACCEPTBROADCAST | |
||||
RXFILTERCTRL_ACCEPTPERFECT, ®s->rxfilterctrl); |
||||
|
||||
/* Clear and disable interrupts */ |
||||
writel(0xFFFF, ®s->intclear); |
||||
writel(0, ®s->intenable); |
||||
|
||||
/* Enable receive and transmit mode of MAC ethernet core */ |
||||
setbits_le32(®s->command, COMMAND_RXENABLE | COMMAND_TXENABLE); |
||||
setbits_le32(®s->mac1, MAC1_RECV_ENABLE); |
||||
|
||||
/*
|
||||
* Perform a 'dummy' first send to work around Ethernet.1 |
||||
* erratum (see ES_LPC3250 rev. 9 dated 1 June 2011). |
||||
* Use zeroed "index" variable as the dummy. |
||||
*/ |
||||
|
||||
index = 0; |
||||
lpc32xx_eth_send(dev, &index, 4); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int lpc32xx_eth_halt(struct eth_device *dev) |
||||
{ |
||||
struct lpc32xx_eth_device *lpc32xx_eth_device = |
||||
container_of(dev, struct lpc32xx_eth_device, dev); |
||||
struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs; |
||||
|
||||
/* Reset all MAC logic */ |
||||
writel(MAC1_RESETS, ®s->mac1); |
||||
writel(COMMAND_RESETS, ®s->command); |
||||
/* Let reset condition settle */ |
||||
udelay(2000); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
#if defined(CONFIG_PHYLIB) |
||||
int lpc32xx_eth_phylib_init(struct eth_device *dev, int phyid) |
||||
{ |
||||
struct mii_dev *bus; |
||||
struct phy_device *phydev; |
||||
int ret; |
||||
|
||||
bus = mdio_alloc(); |
||||
if (!bus) { |
||||
printf("mdio_alloc failed\n"); |
||||
return -ENOMEM; |
||||
} |
||||
bus->read = lpc32xx_eth_phy_read; |
||||
bus->write = lpc32xx_eth_phy_write; |
||||
sprintf(bus->name, dev->name); |
||||
|
||||
ret = mdio_register(bus); |
||||
if (ret) { |
||||
printf("mdio_register failed\n"); |
||||
free(bus); |
||||
return -ENOMEM; |
||||
} |
||||
|
||||
phydev = phy_connect(bus, phyid, dev, PHY_INTERFACE_MODE_MII); |
||||
if (!phydev) { |
||||
printf("phy_connect failed\n"); |
||||
return -ENODEV; |
||||
} |
||||
|
||||
phy_config(phydev); |
||||
phy_startup(phydev); |
||||
|
||||
return 0; |
||||
} |
||||
#endif |
||||
|
||||
int lpc32xx_eth_initialize(bd_t *bis) |
||||
{ |
||||
struct eth_device *dev = &lpc32xx_eth.dev; |
||||
struct lpc32xx_eth_registers *regs = lpc32xx_eth.regs; |
||||
|
||||
/*
|
||||
* Set RMII management clock rate. With HCLK at 104 MHz and |
||||
* a divider of 28, this will be 3.72 MHz. |
||||
*/ |
||||
|
||||
writel(MCFG_CLOCK_SELECT_DIV28, ®s->mcfg); |
||||
|
||||
/* Reset all MAC logic */ |
||||
writel(MAC1_RESETS, ®s->mac1); |
||||
writel(COMMAND_RESETS, ®s->command); |
||||
|
||||
/* wait 10 ms for the whole I/F to reset */ |
||||
udelay(10000); |
||||
|
||||
/* must be less than sizeof(dev->name) */ |
||||
strcpy(dev->name, "eth0"); |
||||
|
||||
dev->init = (void *)lpc32xx_eth_init; |
||||
dev->halt = (void *)lpc32xx_eth_halt; |
||||
dev->send = (void *)lpc32xx_eth_send; |
||||
dev->recv = (void *)lpc32xx_eth_recv; |
||||
dev->write_hwaddr = (void *)lpc32xx_eth_write_hwaddr; |
||||
|
||||
/* Release SOFT reset to let MII talk to PHY */ |
||||
clrbits_le32(®s->mac1, MAC1_SOFT_RESET); |
||||
|
||||
/* register driver before talking to phy */ |
||||
eth_register(dev); |
||||
|
||||
#if defined(CONFIG_PHYLIB) |
||||
lpc32xx_eth_phylib_init(dev, 0); |
||||
#elif defined(CONFIG_MII) || defined(CONFIG_CMD_MII) |
||||
miiphy_register(dev->name, mii_reg_read, mii_reg_write); |
||||
#endif |
||||
|
||||
return 0; |
||||
} |
Loading…
Reference in new issue