This board is still a non-generic board. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Conn Clark <clark@esteem.com>master
Masahiro Yamada
10 years ago
committed by
Tom Rini
parent
5ec71100dc
commit
af0e35149b
@ -1,9 +0,0 @@ |
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if TARGET_ESTEEM192E |
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config SYS_BOARD |
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default "esteem192e" |
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config SYS_CONFIG_NAME |
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default "ESTEEM192E" |
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endif |
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@ -1,6 +0,0 @@ |
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ESTEEM192E BOARD |
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M: Conn Clark <clark@esteem.com> |
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S: Maintained |
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F: board/esteem192e/ |
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F: include/configs/ESTEEM192E.h |
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F: configs/ESTEEM192E_defconfig |
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@ -1,8 +0,0 @@ |
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y = esteem192e.o flash.o
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@ -1,225 +0,0 @@ |
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/*
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* (C) Copyright 2000 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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* |
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* Modified By Conn Clark to work with Esteem 192E 7/31/00 |
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*/ |
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#include <common.h> |
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#include <mpc8xx.h> |
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/* ------------------------------------------------------------------------- */ |
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#define _NOT_USED_ 0xFFFFFFFF |
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const uint sdram_table[] = { |
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/*
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* Single Read. (Offset 0 in UPMA RAM) |
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* |
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* active, NOP, read, precharge, NOP */ |
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0x0F27CC04, 0x0EAECC04, 0x00B98C04, 0x00F74C00, |
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0x11FFCC05, /* last */ |
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/*
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* SDRAM Initialization (offset 5 in UPMA RAM) |
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* |
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* This is no UPM entry point. The following definition uses |
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* the remaining space to establish an initialization |
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* sequence, which is executed by a RUN command. |
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* NOP, Program |
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*/ |
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0x0F0A8C34, 0x1F354C37, /* last */ |
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_NOT_USED_, /* Not used */ |
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/*
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* Burst Read. (Offset 8 in UPMA RAM) |
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* active, NOP, read, NOP, NOP, NOP, NOP, NOP */ |
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0x0F37CC04, 0x0EFECC04, 0x00FDCC04, 0x00FFCC00, |
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0x00FFCC00, 0x01FFCC00, 0x0FFFCC00, 0x1FFFCC05, /* last */ |
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
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/*
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* Single Write. (Offset 18 in UPMA RAM) |
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* active, NOP, write, NOP, precharge, NOP */ |
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0x0F27CC04, 0x0EAE8C00, 0x01BD4C04, 0x0FFB8C04, |
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0x0FF74C04, 0x1FFFCC05, /* last */ |
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_NOT_USED_, _NOT_USED_, |
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/*
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* Burst Write. (Offset 20 in UPMA RAM) |
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* active, NOP, write, NOP, NOP, NOP, NOP, NOP */ |
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0x0F37CC04, 0x0EFE8C00, 0x00FD4C00, 0x00FFCC00, |
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0x00FFCC00, 0x01FFCC04, 0x0FFFCC04, 0x1FFFCC05, /* last */ |
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
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/*
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* Refresh (Offset 30 in UPMA RAM) |
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* precharge, NOP, auto_ref, NOP, NOP, NOP */ |
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0x0FF74C34, 0x0FFACCB4, 0x0FF5CC34, 0x0FFFCC34, |
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0x0FFFCCB4, 0x1FFFCC35, /* last */ |
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_NOT_USED_, _NOT_USED_, |
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
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/*
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* Exception. (Offset 3c in UPMA RAM) |
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*/ |
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0x0FFB8C00, 0x1FF74C03, /* last */ |
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_NOT_USED_, _NOT_USED_ |
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}; |
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/* ------------------------------------------------------------------------- */ |
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/*
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* Check Board Identity: |
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*/ |
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int checkboard (void) |
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{ |
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puts ("Board: Esteem 192E\n"); |
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return (0); |
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} |
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/* ------------------------------------------------------------------------- */ |
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phys_size_t initdram (int board_type) |
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{ |
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; |
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volatile memctl8xx_t *memctl = &immap->im_memctl; |
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long int size_b0, size_b1; |
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/*
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* Explain frequency of refresh here |
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*/ |
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memctl->memc_mptpr = 0x0200; /* divide by 32 */ |
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memctl->memc_mamr = 0x18003112; /*CONFIG_SYS_MAMR_8COL; */ /* 0x18005112 TODO: explain here */ |
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upmconfig (UPMA, (uint *) sdram_table, |
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sizeof (sdram_table) / sizeof (uint)); |
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/*
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* Map cs 2 and 3 to the SDRAM banks 0 and 1 at |
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* preliminary addresses - these have to be modified after the |
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* SDRAM size has been determined. |
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*/ |
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memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; /* not defined yet */ |
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memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; |
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memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM; |
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memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM; |
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/* perform SDRAM initializsation sequence */ |
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memctl->memc_mar = 0x00000088; |
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memctl->memc_mcr = 0x80004830; /* SDRAM bank 0 execute 8 refresh */ |
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memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */ |
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memctl->memc_mcr = 0x80006830; /* SDRAM bank 1 execute 8 refresh */ |
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memctl->memc_mcr = 0x80006105; /* SDRAM bank 1 */ |
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memctl->memc_mamr = CONFIG_SYS_MAMR_8COL; /* 0x18803112 start refresh timer TODO: explain here */ |
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/* printf ("banks 0 and 1 are programed\n"); */ |
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/*
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* Check Bank 0 Memory Size for re-configuration |
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* |
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*/ |
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size_b0 = get_ram_size ( (long *)SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); |
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size_b1 = get_ram_size ( (long *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE); |
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printf ("\nbank 0 size %lu\nbank 1 size %lu\n", size_b0, size_b1); |
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/* printf ("bank 1 size %u\n",size_b1); */ |
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if (size_b1 == 0) { |
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/*
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* Adjust refresh rate if bank 0 isn't stuffed |
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*/ |
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memctl->memc_mptpr = 0x0400; /* divide by 64 */ |
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memctl->memc_br3 &= 0x0FFFFFFFE; |
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/*
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* Adjust OR2 for size of bank 0 |
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*/ |
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memctl->memc_or2 |= 7 * size_b0; |
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} else { |
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if (size_b0 < size_b1) { |
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memctl->memc_br2 &= 0x00007FFE; |
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memctl->memc_br3 &= 0x00007FFF; |
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/*
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* Adjust OR3 for size of bank 1 |
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*/ |
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memctl->memc_or3 |= 15 * size_b1; |
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/*
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* Adjust OR2 for size of bank 0 |
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*/ |
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memctl->memc_or2 |= 15 * size_b0; |
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memctl->memc_br2 += (size_b1 + 1); |
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} else { |
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memctl->memc_br3 &= 0x00007FFE; |
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/*
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* Adjust OR2 for size of bank 0 |
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*/ |
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memctl->memc_or2 |= 15 * size_b0; |
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/*
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* Adjust OR3 for size of bank 1 |
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*/ |
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memctl->memc_or3 |= 15 * size_b1; |
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memctl->memc_br3 += (size_b0 + 1); |
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} |
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} |
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/* before leaving set all unused i/o pins to outputs */ |
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/*
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* --*Unused Pin List*-- |
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* |
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* group/port bit number |
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* IP_B 0,1,3,4,5 Taken care of in pcmcia-cs-x.x.xx |
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* PA 5,7,8,9,14,15 |
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* PB 22,23,31 |
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* PC 4,5,6,7,10,11,12,13,14,15 |
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* PD 5,6,7 |
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* |
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*/ |
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/*
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* --*Pin Used for I/O List*-- |
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* |
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* port input bit number output bit number either |
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* PB 18,26,27 |
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* PD 3,4 8,9,10,11,12,13,14,15 |
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* |
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*/ |
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immap->im_ioport.iop_papar &= ~0x05C3; /* set pins as io */ |
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immap->im_ioport.iop_padir |= 0x05C3; /* set pins as output */ |
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immap->im_ioport.iop_paodr &= 0x0008; /* config pins 9 & 14 as normal outputs */ |
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immap->im_ioport.iop_padat |= 0x05C3; /* set unused pins as high */ |
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immap->im_cpm.cp_pbpar &= ~0x00001331; /* set unused port b pins as io */ |
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immap->im_cpm.cp_pbdir |= 0x00001331; /* set unused port b pins as output */ |
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immap->im_cpm.cp_pbodr &= ~0x00001331; /* config bits 18,22,23,26,27 & 31 as normal outputs */ |
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immap->im_cpm.cp_pbdat |= 0x00001331; /* set T/E LED, /NV_CS, & /POWER_ADJ_CS and the rest to a high */ |
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immap->im_ioport.iop_pcpar &= ~0x0F3F; /* set unused port c pins as io */ |
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immap->im_ioport.iop_pcdir |= 0x0F3F; /* set unused port c pins as output */ |
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immap->im_ioport.iop_pcso &= ~0x0F3F; /* clear special purpose bit for unused port c pins for clarity */ |
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immap->im_ioport.iop_pcdat |= 0x0F3F; /* set unused port c pins high */ |
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immap->im_ioport.iop_pdpar &= 0xE000; /* set pins as io */ |
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immap->im_ioport.iop_pddir &= 0xE000; /* set bit 3 & 4 as inputs */ |
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immap->im_ioport.iop_pddir |= 0x07FF; /* set bits 5 - 15 as outputs */ |
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immap->im_ioport.iop_pddat = 0x0055; /* set alternating pattern on test port */ |
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return (size_b0 + size_b1); |
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} |
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File diff suppressed because it is too large
Load Diff
@ -1,90 +0,0 @@ |
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/* |
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* (C) Copyright 2000-2010 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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OUTPUT_ARCH(powerpc) |
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SECTIONS |
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{ |
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/* Read-only sections, merged into text segment: */ |
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. = + SIZEOF_HEADERS; |
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.text : |
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{ |
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/* WARNING - the following is hand-optimized to fit within */ |
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/* the sector layout of our flash chips! XXX FIXME XXX */ |
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arch/powerpc/cpu/mpc8xx/start.o (.text*) |
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arch/powerpc/cpu/mpc8xx/traps.o (.text*) |
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net/built-in.o (.text*) |
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board/esteem192e/built-in.o (.text*) |
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. = env_offset; |
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common/env_embedded.o (.text*) |
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*(.text*) |
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} |
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_etext = .; |
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PROVIDE (etext = .); |
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.rodata : |
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{ |
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*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) |
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} |
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/* Read-write section, merged into data segment: */ |
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. = (. + 0x00FF) & 0xFFFFFF00; |
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_erotext = .; |
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PROVIDE (erotext = .); |
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.reloc : |
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{ |
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_GOT2_TABLE_ = .; |
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KEEP(*(.got2)) |
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KEEP(*(.got)) |
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PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); |
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_FIXUP_TABLE_ = .; |
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KEEP(*(.fixup)) |
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} |
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__got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; |
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__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
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.data : |
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{ |
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*(.data*) |
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*(.sdata*) |
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} |
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_edata = .; |
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PROVIDE (edata = .); |
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. = .; |
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. = ALIGN(4); |
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.u_boot_list : { |
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KEEP(*(SORT(.u_boot_list*))); |
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} |
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. = .; |
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__start___ex_table = .; |
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__ex_table : { *(__ex_table) } |
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__stop___ex_table = .; |
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. = ALIGN(256); |
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__init_begin = .; |
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.text.init : { *(.text.init) } |
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.data.init : { *(.data.init) } |
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. = ALIGN(256); |
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__init_end = .; |
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__bss_start = .; |
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.bss (NOLOAD) : |
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{ |
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*(.bss*) |
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*(.sbss*) |
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*(COMMON) |
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. = ALIGN(4); |
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} |
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__bss_end = . ; |
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PROVIDE (end = .); |
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} |
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@ -1,3 +0,0 @@ |
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CONFIG_PPC=y |
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CONFIG_8xx=y |
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CONFIG_TARGET_ESTEEM192E=y |
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@ -1,292 +0,0 @@ |
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/*
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* (C) Copyright 2000 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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/*
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* board/config.h - configuration options, board specific |
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*/ |
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#ifndef __CONFIG_H |
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#define __CONFIG_H |
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/*
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* High Level Configuration Options |
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* (easy to change) |
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*/ |
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#define CONFIG_MPC850 1 /* This is a MPC850 CPU */ |
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#define CONFIG_ESTEEM192E 1 /* ...on a EST ESTEEM192E */ |
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#define CONFIG_SYS_TEXT_BASE 0x40000000 |
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#define CONFIG_FLASH_16BIT 1 /* Rom 16 bit data bus */ |
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#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ |
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#undef CONFIG_8xx_CONS_SMC2 |
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#undef CONFIG_8xx_CONS_NONE |
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#define MPC8XX_FACT 10 /* Multiply by 10 */ |
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#define MPC8XX_XIN 4915200 /* 4.915200 MHz in - ??? - XXX */ |
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#define CONFIG_SYS_PLPRCR_MF ((MPC8XX_FACT-1) << 20) |
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#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT)) /* 49,152,000 Hz */ |
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#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ /* Force it - dont measure it */ |
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#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ |
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#define CONFIG_BAUDRATE 9600 |
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#if 0 |
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#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ |
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#else |
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
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#endif |
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#define CONFIG_BOOTCOMMAND "bootm 40030000" /* autoboot command */ |
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#define CONFIG_BOOTARGS "root=/dev/ram rw ramdisk=8192 " \ |
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"ip=100.100.100.21:100.100.100.14:100.100.100.1:255.0.0.0 " |
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/*
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* Miscellaneous configurable options |
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*/ |
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
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#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
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#undef CONFIG_WATCHDOG /* watchdog disabled */ |
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/*
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* BOOTP options |
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*/ |
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#define CONFIG_BOOTP_SUBNETMASK |
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#define CONFIG_BOOTP_GATEWAY |
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#define CONFIG_BOOTP_HOSTNAME |
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#define CONFIG_BOOTP_BOOTPATH |
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#define CONFIG_BOOTP_BOOTFILESIZE |
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/*
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* Command line configuration. |
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*/ |
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#include <config_cmd_default.h> |
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#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
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#define CONFIG_SYS_PROMPT "BOOT: " /* Monitor Command Prompt */ |
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
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#define CONFIG_SYS_MAXARGS 8 /* max number of command args */ |
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
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#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
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#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
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#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
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|
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/*
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* Low Level Configuration Settings |
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* (address mappings, register initial values, etc.) |
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* You should know what you are doing if you make changes here. |
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*/ |
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/*-----------------------------------------------------------------------
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* Internal Memory Mapped Register |
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*/ |
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#define CONFIG_SYS_IMMR 0xFF000000 |
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|
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in DPRAM) |
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*/ |
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#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
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#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ |
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
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|
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration |
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* (Set up by the startup code) |
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* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
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*/ |
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#define CONFIG_SYS_SDRAM_BASE 0x00000000 |
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#define CONFIG_SYS_FLASH_BASE 0x40000000 |
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#ifdef DEBUG |
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#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
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#else |
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#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ |
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#endif |
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
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#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
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|
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/*
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* For booting Linux, the board info and command line data |
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* have to be in the first 8 MB of memory, since this is |
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* the maximum mapped by the Linux kernel during initialization. |
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*/ |
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
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/*-----------------------------------------------------------------------
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* FLASH organization |
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*/ |
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#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
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#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ |
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|
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#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
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|
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#define CONFIG_ENV_IS_IN_FLASH 1 |
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#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ |
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#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ |
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/*-----------------------------------------------------------------------
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* Cache Configuration |
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*/ |
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#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
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|
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/*-----------------------------------------------------------------------
|
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* SYPCR - System Protection Control 11-9 |
||||
* SYPCR can only be written once after reset! |
||||
*----------------------------------------------------------------------- |
||||
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze |
||||
*/ |
||||
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SUMCR - SIU Module Configuration 11-6 |
||||
*----------------------------------------------------------------------- |
||||
* PCMCIA config., multi-function pin tri-state |
||||
*/ |
||||
#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) /* DBGC00 */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TBSCR - Time Base Status and Control 11-26 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Reference Interrupt Status, Timebase freezing enabled |
||||
*/ |
||||
#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE) |
||||
|
||||
/* (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) */ |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 11-31 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled |
||||
*/ |
||||
#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 |
||||
*----------------------------------------------------------------------- |
||||
* Reset PLL lock status sticky bit, timer expired status bit and timer |
||||
* interrupt status bit - leave PLL multiplication factor unchanged ! |
||||
*/ |
||||
#define CONFIG_SYS_PLPRCR (CONFIG_SYS_PLPRCR_MF | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27 |
||||
*----------------------------------------------------------------------- |
||||
* Set clock output, timebase and RTC source and divider, |
||||
* power management and some other internal clocks |
||||
*/ |
||||
#define SCCR_MASK SCCR_EBDF11 |
||||
#define CONFIG_SYS_SCCR (SCCR_TBS | \ |
||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCMCIA stuff |
||||
*----------------------------------------------------------------------- |
||||
* |
||||
*/ |
||||
#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) |
||||
#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) |
||||
#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) |
||||
#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) |
||||
#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) |
||||
#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) |
||||
#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) |
||||
#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) |
||||
|
||||
#define CONFIG_SYS_PCMCIA_INTERRUPT SIU_LEVEL6 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* |
||||
*----------------------------------------------------------------------- |
||||
* |
||||
*/ |
||||
/*#define CONFIG_SYS_DER 0x2002000F*/ |
||||
#define CONFIG_SYS_DER 0 |
||||
/*#define CONFIG_SYS_DER 0x02002000 */ |
||||
|
||||
|
||||
/*
|
||||
* Init Memory Controller: |
||||
* |
||||
* BR0/1 and OR0/1 (FLASH) |
||||
*/ |
||||
|
||||
#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ |
||||
#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ |
||||
|
||||
/* used to re-map FLASH both when starting from SRAM or FLASH:
|
||||
* restrict access enough to keep SRAM working (if any) |
||||
* but not too much to meddle with FLASH accesses |
||||
*/ |
||||
#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ |
||||
#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ |
||||
|
||||
/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ |
||||
#define CONFIG_SYS_OR_TIMING_FLASH 0x00000160 |
||||
/*(OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \
|
||||
OR_SCY_5_CLK | OR_EHTR) */ |
||||
|
||||
#define CONFIG_SYS_OR0_REMAP 0x80000160 /*(CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)*/ |
||||
#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
||||
#define CONFIG_SYS_BR0_PRELIM ( FLASH_BASE0_PRELIM | 0x00000801 ) |
||||
|
||||
#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP |
||||
#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM |
||||
#define CONFIG_SYS_BR1_PRELIM ( FLASH_BASE1_PRELIM | 0x00000801 ) |
||||
|
||||
/*
|
||||
* BR2/3 and OR2/3 (SDRAM) |
||||
* |
||||
*/ |
||||
#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ |
||||
#define SDRAM_BASE3_PRELIM 0x04000000 /* SDRAM bank #1 */ |
||||
#define SDRAM_MAX_SIZE 0x02000000 /* max 32 MB per bank */ |
||||
|
||||
/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ |
||||
#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 |
||||
|
||||
#define CONFIG_SYS_OR2_PRELIM 0xFC000E00 |
||||
#define CONFIG_SYS_BR2_PRELIM (SDRAM_BASE2_PRELIM | 0x00000081) |
||||
|
||||
#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM |
||||
#define CONFIG_SYS_BR3_PRELIM (SDRAM_BASE3_PRELIM | 0x00000081) |
||||
|
||||
|
||||
/*
|
||||
* Memory Periodic Timer Prescaler |
||||
*/ |
||||
|
||||
/* periodic timer for refresh */ |
||||
#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */ |
||||
|
||||
/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ |
||||
#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ |
||||
#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ |
||||
|
||||
/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ |
||||
#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ |
||||
#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ |
||||
|
||||
/*
|
||||
* MAMR settings for SDRAM |
||||
*/ |
||||
|
||||
/* 8 column SDRAM */ |
||||
#define CONFIG_SYS_MAMR_8COL 0x18803112 |
||||
#define CONFIG_SYS_MAMR_9COL 0x18803112 /* same as 8 column because its just easier to port with*/ |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
Loading…
Reference in new issue