Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Acked-by: Minkyu Kang <mk7.kang@samsung.com>master
Albert ARIBAUD
11 years ago
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4efd69250f
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#
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# (C) Copyright 2012
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := mini2440.o
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@ -1,118 +0,0 @@ |
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/*
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* (C) Copyright 2002 |
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
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* Marius Groeger <mgroeger@sysgo.de> |
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* |
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* (C) Copyright 2002 |
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* David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> |
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* |
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* (C) Copyright 2009 |
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* Michel Pollet <buserror@gmail.com> |
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* |
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* (C) Copyright 2012 |
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* Gabriel Huau <contact@huau-gabriel.fr> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/arch/s3c2440.h> |
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#include <asm/arch/iomux.h> |
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#include <asm/arch/gpio.h> |
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#include <asm/io.h> |
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#include <asm/gpio.h> |
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#include <netdev.h> |
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#include "mini2440.h" |
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DECLARE_GLOBAL_DATA_PTR; |
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static inline void pll_delay(unsigned long loops) |
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{ |
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__asm__ volatile ("1:\n" |
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"subs %0, %1, #1\n" |
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"bne 1b" : "=r" (loops) : "0" (loops)); |
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} |
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int board_early_init_f(void) |
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{ |
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struct s3c24x0_clock_power * const clk_power = |
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s3c24x0_get_base_clock_power(); |
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/* to reduce PLL lock time, adjust the LOCKTIME register */ |
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clk_power->locktime = 0xFFFFFF; /* Max PLL Lock time count */ |
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clk_power->clkdivn = CLKDIVN_VAL; |
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/* configure UPLL */ |
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clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV); |
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/* some delay between MPLL and UPLL */ |
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pll_delay(100); |
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/* configure MPLL */ |
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clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV); |
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/* some delay between MPLL and UPLL */ |
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pll_delay(10000); |
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return 0; |
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} |
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/*
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* Miscellaneous platform dependent initialisations |
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*/ |
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int board_init(void) |
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{ |
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struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); |
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/* IOMUX Port H : UART Configuration */ |
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gpio->gphcon = IOMUXH_nCTS0 | IOMUXH_nRTS0 | IOMUXH_TXD0 | IOMUXH_RXD0 | |
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IOMUXH_TXD1 | IOMUXH_RXD1 | IOMUXH_TXD2 | IOMUXH_RXD2; |
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gpio_direction_output(GPH8, 0); |
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gpio_direction_output(GPH9, 0); |
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gpio_direction_output(GPH10, 0); |
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/* adress of boot parameters */ |
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gd->bd->bi_boot_params = CONFIG_BOOT_PARAM_ADDR; |
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return 0; |
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} |
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int dram_init(void) |
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{ |
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struct s3c24x0_memctl *memctl = s3c24x0_get_base_memctl(); |
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/*
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* Configuring bus width and timing |
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* Initialize clocks for each bank 0..5 |
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* Bank 3 and 4 are used for DM9000 |
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*/ |
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writel(BANK_CONF, &memctl->bwscon); |
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writel(B0_CONF, &memctl->bankcon[0]); |
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writel(B1_CONF, &memctl->bankcon[1]); |
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writel(B2_CONF, &memctl->bankcon[2]); |
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writel(B3_CONF, &memctl->bankcon[3]); |
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writel(B4_CONF, &memctl->bankcon[4]); |
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writel(B5_CONF, &memctl->bankcon[5]); |
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/* Bank 6 and 7 are used for DRAM */ |
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writel(SDRAM_64MB, &memctl->bankcon[6]); |
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writel(SDRAM_64MB, &memctl->bankcon[7]); |
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writel(MEM_TIMING, &memctl->refresh); |
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writel(BANKSIZE_CONF, &memctl->banksize); |
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writel(B6_MRSR, &memctl->mrsrb6); |
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writel(B7_MRSR, &memctl->mrsrb7); |
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gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE, |
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PHYS_SDRAM_SIZE); |
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return 0; |
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} |
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int board_eth_init(bd_t *bis) |
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{ |
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#ifdef CONFIG_DRIVER_DM9000 |
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return dm9000_initialize(bis); |
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#else |
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return 0; |
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#endif |
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} |
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@ -1,144 +0,0 @@ |
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#ifndef __MINI2440_BOARD_CONF_H__ |
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#define __MINI2440_BOARD_CONF_H__ |
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/* PLL Parameters */ |
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#define CLKDIVN_VAL 7 |
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#define M_MDIV 0x7f |
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#define M_PDIV 0x2 |
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#define M_SDIV 0x1 |
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#define U_M_MDIV 0x38 |
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#define U_M_PDIV 0x2 |
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#define U_M_SDIV 0x2 |
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/* BWSCON */ |
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#define DW8 0x0 |
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#define DW16 0x1 |
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#define DW32 0x2 |
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#define WAIT (0x1<<2) |
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#define UBLB (0x1<<3) |
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#define B1_BWSCON (DW32) |
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#define B2_BWSCON (DW16) |
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#define B3_BWSCON (DW16 + WAIT + UBLB) |
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#define B4_BWSCON (DW16 + WAIT + UBLB) |
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#define B5_BWSCON (DW16) |
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#define B6_BWSCON (DW32) |
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#define B7_BWSCON (DW32) |
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/*
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* Bank Configuration |
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*/ |
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#define B0_Tacs 0x0 /* 0clk */ |
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#define B0_Tcos 0x0 /* 0clk */ |
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#define B0_Tacc 0x7 /* 14clk */ |
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#define B0_Tcoh 0x0 /* 0clk */ |
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#define B0_Tah 0x0 /* 0clk */ |
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#define B0_Tacp 0x0 /* 0clk */ |
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#define B0_PMC 0x0 /* normal */ |
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#define B1_Tacs 0x0 |
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#define B1_Tcos 0x0 |
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#define B1_Tacc 0x7 |
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#define B1_Tcoh 0x0 |
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#define B1_Tah 0x0 |
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#define B1_Tacp 0x0 |
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#define B1_PMC 0x0 |
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#define B2_Tacs 0x0 |
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#define B2_Tcos 0x0 |
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#define B2_Tacc 0x7 |
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#define B2_Tcoh 0x0 |
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#define B2_Tah 0x0 |
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#define B2_Tacp 0x0 |
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#define B2_PMC 0x0 |
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#define B3_Tacs 0x0 |
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#define B3_Tcos 0x3 /* 4clk */ |
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#define B3_Tacc 0x7 |
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#define B3_Tcoh 0x1 /* 1clk */ |
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#define B3_Tah 0x3 /* 4clk */ |
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#define B3_Tacp 0x0 |
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#define B3_PMC 0x0 |
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#define B4_Tacs 0x0 |
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#define B4_Tcos 0x3 |
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#define B4_Tacc 0x7 |
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#define B4_Tcoh 0x1 |
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#define B4_Tah 0x3 |
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#define B4_Tacp 0x0 |
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#define B4_PMC 0x0 |
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#define B5_Tacs 0x0 |
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#define B5_Tcos 0x0 |
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#define B5_Tacc 0x7 |
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#define B5_Tcoh 0x0 |
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#define B5_Tah 0x0 |
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#define B5_Tacp 0x0 |
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#define B5_PMC 0x0 |
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/*
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* SDRAM Configuration |
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*/ |
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#define SDRAM_MT 0x3 /* SDRAM */ |
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#define SDRAM_Trcd 0x0 /* 2clk */ |
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#define SDRAM_SCAN_9 0x1 /* 9bit */ |
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#define SDRAM_SCAN_10 0x2 /* 10bit */ |
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#define SDRAM_64MB ((SDRAM_MT<<15) + (SDRAM_Trcd<<2) + (SDRAM_SCAN_9)) |
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/*
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* Refresh Parameter |
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*/ |
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#define REFEN 0x1 /* Refresh enable */ |
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#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */ |
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#define Trp 0x1 /* 3clk */ |
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#define Trc 0x3 /* 7clk */ |
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#define Tchr 0x0 /* unused */ |
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#define REFCNT 1012 /* period=10.37us, HCLK=100Mhz, (2048 + 1-10.37*100) */ |
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/*
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* MRSR Parameter |
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*/ |
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#define BL 0x0 |
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#define BT 0x0 |
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#define CL 0x3 /* 3 clocks */ |
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#define TM 0x0 |
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#define WBL 0x0 |
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/*
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* BankSize Parameter |
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*/ |
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#define BK76MAP 0x2 /* 128MB/128MB */ |
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#define SCLK_EN 0x1 /* SCLK active */ |
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#define SCKE_EN 0x1 /* SDRAM power down mode enable */ |
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#define BURST_EN 0x1 /* Burst enable */ |
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/*
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* Register values |
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*/ |
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#define BANK_CONF ((0 + (B1_BWSCON<<4) + (B2_BWSCON<<8) + (B3_BWSCON<<12) + \ |
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(B4_BWSCON<<16) + (B5_BWSCON<<20) + (B6_BWSCON<<24) + \
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(B7_BWSCON<<28))) |
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#define B0_CONF ((B0_Tacs<<13) + (B0_Tcos<<11) + (B0_Tacc<<8) + \ |
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(B0_Tcoh<<6) + (B0_Tah<<4) + (B0_Tacp<<2) + (B0_PMC)) |
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#define B1_CONF ((B1_Tacs<<13) + (B1_Tcos<<11) + (B1_Tacc<<8) + \ |
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(B1_Tcoh<<6) + (B1_Tah<<4) + (B1_Tacp<<2) + (B1_PMC)) |
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#define B2_CONF ((B2_Tacs<<13) + (B2_Tcos<<11) + (B2_Tacc<<8) + \ |
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(B2_Tcoh<<6) + (B2_Tah<<4) + (B2_Tacp<<2) + (B2_PMC)) |
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#define B3_CONF ((B3_Tacs<<13) + (B3_Tcos<<11) + (B3_Tacc<<8) + \ |
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(B3_Tcoh<<6) + (B3_Tah<<4) + (B3_Tacp<<2) + (B3_PMC)) |
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#define B4_CONF ((B4_Tacs<<13) + (B4_Tcos<<11) + (B4_Tacc<<8) + \ |
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(B4_Tcoh<<6) + (B4_Tah<<4) + (B4_Tacp<<2) + (B4_PMC)) |
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#define B5_CONF ((B5_Tacs<<13) + (B5_Tcos<<11) + (B5_Tacc<<8) + \ |
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(B5_Tcoh<<6) + (B5_Tah<<4) + (B5_Tacp<<2) + (B5_PMC)) |
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#define MEM_TIMING (REFEN<<23) + (TREFMD<<22) + (Trp<<20) + \ |
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(Trc<<18) + (Tchr<<16) + REFCNT |
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#define BANKSIZE_CONF (BK76MAP) + (SCLK_EN<<4) + (SCKE_EN<<5) + (BURST_EN<<7) |
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#define B6_MRSR (CL<<4) |
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#define B7_MRSR (CL<<4) |
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#endif |
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@ -1,28 +0,0 @@ |
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U-Boot for FriendlyARM Mini2440 (s3c2440) |
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This file contains information for the port of U-Boot to FriendlyARM |
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mini2440 |
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All information about the board can be found on : |
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http://www.friendlyarm.net/products/mini2440 |
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To build u-boot : ./MAKEALL mini2440 |
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Overview : |
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-------- |
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FriendlyARM Mini 2440 SBC (Single-Board Computer) with 400 MHz Samsung S3C2440 |
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ARM9 processor. The board measures 100 x 100 mm, ideal for learning about ARM9 |
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systems. It's a low cost board. |
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Boot Methods : |
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------------ |
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Mini2440 can boot from NOR or NAND. |
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Build : |
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----- |
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./MAKEALL mini2440 |
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or |
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make mini2440_config |
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make |
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