Some Renesas SuperH have MMCIF module. This driver supports it. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Acked-by: Andy Fleming <afleming@freescale.com>master
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/*
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* MMCIF driver. |
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* |
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* Copyright (C) 2011 Renesas Solutions Corp. |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation; either version 2 of the License. |
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*/ |
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#include <config.h> |
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#include <common.h> |
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#include <watchdog.h> |
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#include <command.h> |
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#include <mmc.h> |
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#include <malloc.h> |
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#include <asm/errno.h> |
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#include <asm/io.h> |
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#include "sh_mmcif.h" |
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#define DRIVER_NAME "sh_mmcif" |
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static void *mmc_priv(struct mmc *mmc) |
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{ |
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return (void *)mmc->priv; |
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} |
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static int sh_mmcif_intr(void *dev_id) |
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{ |
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struct sh_mmcif_host *host = dev_id; |
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u32 state = 0; |
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state = sh_mmcif_read(&host->regs->ce_int); |
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state &= sh_mmcif_read(&host->regs->ce_int_mask); |
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if (state & INT_RBSYE) { |
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sh_mmcif_write(~(INT_RBSYE | INT_CRSPE), &host->regs->ce_int); |
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sh_mmcif_bitclr(MASK_MRBSYE, &host->regs->ce_int_mask); |
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goto end; |
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} else if (state & INT_CRSPE) { |
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sh_mmcif_write(~INT_CRSPE, &host->regs->ce_int); |
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sh_mmcif_bitclr(MASK_MCRSPE, &host->regs->ce_int_mask); |
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/* one more interrupt (INT_RBSYE) */ |
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if (sh_mmcif_read(&host->regs->ce_cmd_set) & CMD_SET_RBSY) |
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return -EAGAIN; |
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goto end; |
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} else if (state & INT_BUFREN) { |
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sh_mmcif_write(~INT_BUFREN, &host->regs->ce_int); |
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sh_mmcif_bitclr(MASK_MBUFREN, &host->regs->ce_int_mask); |
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goto end; |
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} else if (state & INT_BUFWEN) { |
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sh_mmcif_write(~INT_BUFWEN, &host->regs->ce_int); |
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sh_mmcif_bitclr(MASK_MBUFWEN, &host->regs->ce_int_mask); |
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goto end; |
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} else if (state & INT_CMD12DRE) { |
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sh_mmcif_write(~(INT_CMD12DRE | INT_CMD12RBE | INT_CMD12CRE | |
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INT_BUFRE), &host->regs->ce_int); |
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sh_mmcif_bitclr(MASK_MCMD12DRE, &host->regs->ce_int_mask); |
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goto end; |
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} else if (state & INT_BUFRE) { |
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sh_mmcif_write(~INT_BUFRE, &host->regs->ce_int); |
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sh_mmcif_bitclr(MASK_MBUFRE, &host->regs->ce_int_mask); |
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goto end; |
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} else if (state & INT_DTRANE) { |
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sh_mmcif_write(~INT_DTRANE, &host->regs->ce_int); |
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sh_mmcif_bitclr(MASK_MDTRANE, &host->regs->ce_int_mask); |
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goto end; |
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} else if (state & INT_CMD12RBE) { |
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sh_mmcif_write(~(INT_CMD12RBE | INT_CMD12CRE), |
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&host->regs->ce_int); |
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sh_mmcif_bitclr(MASK_MCMD12RBE, &host->regs->ce_int_mask); |
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goto end; |
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} else if (state & INT_ERR_STS) { |
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/* err interrupts */ |
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sh_mmcif_write(~state, &host->regs->ce_int); |
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sh_mmcif_bitclr(state, &host->regs->ce_int_mask); |
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goto err; |
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} else |
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return -EAGAIN; |
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err: |
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host->sd_error = 1; |
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debug("%s: int err state = %08x\n", DRIVER_NAME, state); |
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end: |
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host->wait_int = 1; |
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return 0; |
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} |
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static int mmcif_wait_interrupt_flag(struct sh_mmcif_host *host) |
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{ |
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int timeout = 10000000; |
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while (1) { |
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timeout--; |
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if (timeout < 0) { |
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printf("timeout\n"); |
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return 0; |
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} |
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if (!sh_mmcif_intr(host)) |
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break; |
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udelay(1); /* 1 usec */ |
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} |
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return 1; /* Return value: NOT 0 = complete waiting */ |
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} |
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static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk) |
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{ |
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int i; |
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sh_mmcif_bitclr(CLK_ENABLE, &host->regs->ce_clk_ctrl); |
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sh_mmcif_bitclr(CLK_CLEAR, &host->regs->ce_clk_ctrl); |
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if (!clk) |
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return; |
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if (clk == CLKDEV_EMMC_DATA) { |
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sh_mmcif_bitset(CLK_PCLK, &host->regs->ce_clk_ctrl); |
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} else { |
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for (i = 1; (unsigned int)host->clk / (1 << i) >= clk; i++) |
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; |
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sh_mmcif_bitset((i - 1) << 16, &host->regs->ce_clk_ctrl); |
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} |
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sh_mmcif_bitset(CLK_ENABLE, &host->regs->ce_clk_ctrl); |
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} |
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static void sh_mmcif_sync_reset(struct sh_mmcif_host *host) |
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{ |
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u32 tmp; |
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tmp = sh_mmcif_read(&host->regs->ce_clk_ctrl) & (CLK_ENABLE | |
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CLK_CLEAR); |
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sh_mmcif_write(SOFT_RST_ON, &host->regs->ce_version); |
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sh_mmcif_write(SOFT_RST_OFF, &host->regs->ce_version); |
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sh_mmcif_bitset(tmp | SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 | SCCSTO_29, |
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&host->regs->ce_clk_ctrl); |
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/* byte swap on */ |
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sh_mmcif_bitset(BUF_ACC_ATYP, &host->regs->ce_buf_acc); |
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} |
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static int sh_mmcif_error_manage(struct sh_mmcif_host *host) |
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{ |
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u32 state1, state2; |
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int ret, timeout = 10000000; |
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host->sd_error = 0; |
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host->wait_int = 0; |
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state1 = sh_mmcif_read(&host->regs->ce_host_sts1); |
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state2 = sh_mmcif_read(&host->regs->ce_host_sts2); |
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debug("%s: ERR HOST_STS1 = %08x\n", \
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DRIVER_NAME, sh_mmcif_read(&host->regs->ce_host_sts1)); |
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debug("%s: ERR HOST_STS2 = %08x\n", \
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DRIVER_NAME, sh_mmcif_read(&host->regs->ce_host_sts2)); |
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if (state1 & STS1_CMDSEQ) { |
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debug("%s: Forced end of command sequence\n", DRIVER_NAME); |
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sh_mmcif_bitset(CMD_CTRL_BREAK, &host->regs->ce_cmd_ctrl); |
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sh_mmcif_bitset(~CMD_CTRL_BREAK, &host->regs->ce_cmd_ctrl); |
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while (1) { |
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timeout--; |
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if (timeout < 0) { |
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printf(DRIVER_NAME": Forceed end of " \
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"command sequence timeout err\n"); |
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return -EILSEQ; |
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} |
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if (!(sh_mmcif_read(&host->regs->ce_host_sts1) |
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& STS1_CMDSEQ)) |
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break; |
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} |
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sh_mmcif_sync_reset(host); |
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return -EILSEQ; |
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} |
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if (state2 & STS2_CRC_ERR) |
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ret = -EILSEQ; |
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else if (state2 & STS2_TIMEOUT_ERR) |
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ret = TIMEOUT; |
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else |
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ret = -EILSEQ; |
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return ret; |
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} |
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static int sh_mmcif_single_read(struct sh_mmcif_host *host, |
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struct mmc_data *data) |
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{ |
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long time; |
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u32 blocksize, i; |
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unsigned long *p = (unsigned long *)data->dest; |
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if ((unsigned long)p & 0x00000001) { |
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printf("%s: The data pointer is unaligned.", __func__); |
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return -EIO; |
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} |
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host->wait_int = 0; |
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/* buf read enable */ |
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sh_mmcif_bitset(MASK_MBUFREN, &host->regs->ce_int_mask); |
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time = mmcif_wait_interrupt_flag(host); |
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if (time == 0 || host->sd_error != 0) |
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return sh_mmcif_error_manage(host); |
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host->wait_int = 0; |
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blocksize = (BLOCK_SIZE_MASK & |
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sh_mmcif_read(&host->regs->ce_block_set)) + 3; |
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for (i = 0; i < blocksize / 4; i++) |
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*p++ = sh_mmcif_read(&host->regs->ce_data); |
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/* buffer read end */ |
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sh_mmcif_bitset(MASK_MBUFRE, &host->regs->ce_int_mask); |
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time = mmcif_wait_interrupt_flag(host); |
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if (time == 0 || host->sd_error != 0) |
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return sh_mmcif_error_manage(host); |
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host->wait_int = 0; |
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return 0; |
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} |
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static int sh_mmcif_multi_read(struct sh_mmcif_host *host, |
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struct mmc_data *data) |
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{ |
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long time; |
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u32 blocksize, i, j; |
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unsigned long *p = (unsigned long *)data->dest; |
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if ((unsigned long)p & 0x00000001) { |
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printf("%s: The data pointer is unaligned.", __func__); |
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return -EIO; |
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} |
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host->wait_int = 0; |
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blocksize = BLOCK_SIZE_MASK & sh_mmcif_read(&host->regs->ce_block_set); |
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for (j = 0; j < data->blocks; j++) { |
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sh_mmcif_bitset(MASK_MBUFREN, &host->regs->ce_int_mask); |
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time = mmcif_wait_interrupt_flag(host); |
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if (time == 0 || host->sd_error != 0) |
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return sh_mmcif_error_manage(host); |
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host->wait_int = 0; |
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for (i = 0; i < blocksize / 4; i++) |
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*p++ = sh_mmcif_read(&host->regs->ce_data); |
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WATCHDOG_RESET(); |
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} |
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return 0; |
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} |
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static int sh_mmcif_single_write(struct sh_mmcif_host *host, |
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struct mmc_data *data) |
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{ |
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long time; |
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u32 blocksize, i; |
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const unsigned long *p = (unsigned long *)data->dest; |
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if ((unsigned long)p & 0x00000001) { |
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printf("%s: The data pointer is unaligned.", __func__); |
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return -EIO; |
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} |
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host->wait_int = 0; |
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sh_mmcif_bitset(MASK_MBUFWEN, &host->regs->ce_int_mask); |
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time = mmcif_wait_interrupt_flag(host); |
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if (time == 0 || host->sd_error != 0) |
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return sh_mmcif_error_manage(host); |
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host->wait_int = 0; |
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blocksize = (BLOCK_SIZE_MASK & |
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sh_mmcif_read(&host->regs->ce_block_set)) + 3; |
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for (i = 0; i < blocksize / 4; i++) |
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sh_mmcif_write(*p++, &host->regs->ce_data); |
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/* buffer write end */ |
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sh_mmcif_bitset(MASK_MDTRANE, &host->regs->ce_int_mask); |
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time = mmcif_wait_interrupt_flag(host); |
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if (time == 0 || host->sd_error != 0) |
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return sh_mmcif_error_manage(host); |
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host->wait_int = 0; |
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return 0; |
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} |
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static int sh_mmcif_multi_write(struct sh_mmcif_host *host, |
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struct mmc_data *data) |
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{ |
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long time; |
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u32 i, j, blocksize; |
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const unsigned long *p = (unsigned long *)data->dest; |
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if ((unsigned long)p & 0x00000001) { |
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printf("%s: The data pointer is unaligned.", __func__); |
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return -EIO; |
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} |
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host->wait_int = 0; |
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blocksize = BLOCK_SIZE_MASK & sh_mmcif_read(&host->regs->ce_block_set); |
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for (j = 0; j < data->blocks; j++) { |
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sh_mmcif_bitset(MASK_MBUFWEN, &host->regs->ce_int_mask); |
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time = mmcif_wait_interrupt_flag(host); |
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if (time == 0 || host->sd_error != 0) |
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return sh_mmcif_error_manage(host); |
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host->wait_int = 0; |
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for (i = 0; i < blocksize / 4; i++) |
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sh_mmcif_write(*p++, &host->regs->ce_data); |
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WATCHDOG_RESET(); |
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} |
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return 0; |
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} |
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static void sh_mmcif_get_response(struct sh_mmcif_host *host, |
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struct mmc_cmd *cmd) |
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{ |
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if (cmd->resp_type & MMC_RSP_136) { |
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cmd->response[0] = sh_mmcif_read(&host->regs->ce_resp3); |
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cmd->response[1] = sh_mmcif_read(&host->regs->ce_resp2); |
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cmd->response[2] = sh_mmcif_read(&host->regs->ce_resp1); |
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cmd->response[3] = sh_mmcif_read(&host->regs->ce_resp0); |
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debug(" RESP %08x, %08x, %08x, %08x\n", cmd->response[0], |
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cmd->response[1], cmd->response[2], cmd->response[3]); |
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} else { |
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cmd->response[0] = sh_mmcif_read(&host->regs->ce_resp0); |
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} |
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} |
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static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host, |
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struct mmc_cmd *cmd) |
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{ |
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cmd->response[0] = sh_mmcif_read(&host->regs->ce_resp_cmd12); |
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} |
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static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host, |
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struct mmc_data *data, struct mmc_cmd *cmd) |
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{ |
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u32 tmp = 0; |
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u32 opc = cmd->cmdidx; |
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/* Response Type check */ |
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switch (cmd->resp_type) { |
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case MMC_RSP_NONE: |
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tmp |= CMD_SET_RTYP_NO; |
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break; |
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case MMC_RSP_R1: |
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case MMC_RSP_R1b: |
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case MMC_RSP_R3: |
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tmp |= CMD_SET_RTYP_6B; |
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break; |
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case MMC_RSP_R2: |
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tmp |= CMD_SET_RTYP_17B; |
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break; |
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default: |
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printf(DRIVER_NAME": Not support type response.\n"); |
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break; |
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} |
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/* RBSY */ |
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if (opc == MMC_CMD_SWITCH) |
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tmp |= CMD_SET_RBSY; |
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/* WDAT / DATW */ |
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if (host->data) { |
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tmp |= CMD_SET_WDAT; |
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switch (host->bus_width) { |
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case MMC_BUS_WIDTH_1: |
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tmp |= CMD_SET_DATW_1; |
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break; |
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case MMC_BUS_WIDTH_4: |
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tmp |= CMD_SET_DATW_4; |
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break; |
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case MMC_BUS_WIDTH_8: |
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tmp |= CMD_SET_DATW_8; |
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break; |
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default: |
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printf(DRIVER_NAME": Not support bus width.\n"); |
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break; |
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} |
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} |
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/* DWEN */ |
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if (opc == MMC_CMD_WRITE_SINGLE_BLOCK || |
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opc == MMC_CMD_WRITE_MULTIPLE_BLOCK) |
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tmp |= CMD_SET_DWEN; |
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/* CMLTE/CMD12EN */ |
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if (opc == MMC_CMD_READ_MULTIPLE_BLOCK || |
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opc == MMC_CMD_WRITE_MULTIPLE_BLOCK) { |
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tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN; |
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sh_mmcif_bitset(data->blocks << 16, &host->regs->ce_block_set); |
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} |
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/* RIDXC[1:0] check bits */ |
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if (opc == MMC_CMD_SEND_OP_COND || opc == MMC_CMD_ALL_SEND_CID || |
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opc == MMC_CMD_SEND_CSD || opc == MMC_CMD_SEND_CID) |
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tmp |= CMD_SET_RIDXC_BITS; |
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/* RCRC7C[1:0] check bits */ |
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if (opc == MMC_CMD_SEND_OP_COND) |
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tmp |= CMD_SET_CRC7C_BITS; |
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/* RCRC7C[1:0] internal CRC7 */ |
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if (opc == MMC_CMD_ALL_SEND_CID || |
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opc == MMC_CMD_SEND_CSD || opc == MMC_CMD_SEND_CID) |
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tmp |= CMD_SET_CRC7C_INTERNAL; |
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return opc = ((opc << 24) | tmp); |
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} |
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static u32 sh_mmcif_data_trans(struct sh_mmcif_host *host, |
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struct mmc_data *data, u16 opc) |
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{ |
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u32 ret; |
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switch (opc) { |
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case MMC_CMD_READ_MULTIPLE_BLOCK: |
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ret = sh_mmcif_multi_read(host, data); |
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break; |
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case MMC_CMD_WRITE_MULTIPLE_BLOCK: |
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ret = sh_mmcif_multi_write(host, data); |
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break; |
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case MMC_CMD_WRITE_SINGLE_BLOCK: |
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ret = sh_mmcif_single_write(host, data); |
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break; |
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case MMC_CMD_READ_SINGLE_BLOCK: |
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case MMC_CMD_SEND_EXT_CSD: |
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ret = sh_mmcif_single_read(host, data); |
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break; |
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default: |
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printf(DRIVER_NAME": NOT SUPPORT CMD = d'%08d\n", opc); |
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ret = -EINVAL; |
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break; |
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} |
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return ret; |
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} |
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static int sh_mmcif_start_cmd(struct sh_mmcif_host *host, |
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struct mmc_data *data, struct mmc_cmd *cmd) |
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{ |
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long time; |
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int ret = 0, mask = 0; |
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u32 opc = cmd->cmdidx; |
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if (opc == MMC_CMD_STOP_TRANSMISSION) { |
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/* MMCIF sends the STOP command automatically */ |
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if (host->last_cmd == MMC_CMD_READ_MULTIPLE_BLOCK) |
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sh_mmcif_bitset(MASK_MCMD12DRE, |
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&host->regs->ce_int_mask); |
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else |
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sh_mmcif_bitset(MASK_MCMD12RBE, |
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&host->regs->ce_int_mask); |
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time = mmcif_wait_interrupt_flag(host); |
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if (time == 0 || host->sd_error != 0) |
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return sh_mmcif_error_manage(host); |
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sh_mmcif_get_cmd12response(host, cmd); |
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return 0; |
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} |
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if (opc == MMC_CMD_SWITCH) |
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mask = MASK_MRBSYE; |
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else |
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mask = MASK_MCRSPE; |
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mask |= MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR | |
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MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR | |
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MASK_MCCSTO | MASK_MCRCSTO | MASK_MWDATTO | |
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MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO; |
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if (host->data) { |
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sh_mmcif_write(0, &host->regs->ce_block_set); |
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sh_mmcif_write(data->blocksize, &host->regs->ce_block_set); |
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} |
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opc = sh_mmcif_set_cmd(host, data, cmd); |
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sh_mmcif_write(INT_START_MAGIC, &host->regs->ce_int); |
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sh_mmcif_write(mask, &host->regs->ce_int_mask); |
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debug("CMD%d ARG:%08x\n", cmd->cmdidx, cmd->cmdarg); |
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/* set arg */ |
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sh_mmcif_write(cmd->cmdarg, &host->regs->ce_arg); |
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host->wait_int = 0; |
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/* set cmd */ |
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sh_mmcif_write(opc, &host->regs->ce_cmd_set); |
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|
||||
time = mmcif_wait_interrupt_flag(host); |
||||
if (time == 0) |
||||
return sh_mmcif_error_manage(host); |
||||
|
||||
if (host->sd_error) { |
||||
switch (cmd->cmdidx) { |
||||
case MMC_CMD_ALL_SEND_CID: |
||||
case MMC_CMD_SELECT_CARD: |
||||
case MMC_CMD_APP_CMD: |
||||
ret = TIMEOUT; |
||||
break; |
||||
default: |
||||
printf(DRIVER_NAME": Cmd(d'%d) err\n", cmd->cmdidx); |
||||
ret = sh_mmcif_error_manage(host); |
||||
break; |
||||
} |
||||
host->sd_error = 0; |
||||
host->wait_int = 0; |
||||
return ret; |
||||
} |
||||
|
||||
/* if no response */ |
||||
if (!(opc & 0x00C00000)) |
||||
return 0; |
||||
|
||||
if (host->wait_int == 1) { |
||||
sh_mmcif_get_response(host, cmd); |
||||
host->wait_int = 0; |
||||
} |
||||
if (host->data) |
||||
ret = sh_mmcif_data_trans(host, data, cmd->cmdidx); |
||||
host->last_cmd = cmd->cmdidx; |
||||
|
||||
return ret; |
||||
} |
||||
|
||||
static int sh_mmcif_request(struct mmc *mmc, struct mmc_cmd *cmd, |
||||
struct mmc_data *data) |
||||
{ |
||||
struct sh_mmcif_host *host = mmc_priv(mmc); |
||||
int ret; |
||||
|
||||
WATCHDOG_RESET(); |
||||
|
||||
switch (cmd->cmdidx) { |
||||
case MMC_CMD_APP_CMD: |
||||
return TIMEOUT; |
||||
case MMC_CMD_SEND_EXT_CSD: /* = SD_SEND_IF_COND (8) */ |
||||
if (data) |
||||
/* ext_csd */ |
||||
break; |
||||
else |
||||
/* send_if_cond cmd (not support) */ |
||||
return TIMEOUT; |
||||
default: |
||||
break; |
||||
} |
||||
host->sd_error = 0; |
||||
host->data = data; |
||||
ret = sh_mmcif_start_cmd(host, data, cmd); |
||||
host->data = NULL; |
||||
|
||||
return ret; |
||||
} |
||||
|
||||
static void sh_mmcif_set_ios(struct mmc *mmc) |
||||
{ |
||||
struct sh_mmcif_host *host = mmc_priv(mmc); |
||||
|
||||
if (mmc->clock) |
||||
sh_mmcif_clock_control(host, mmc->clock); |
||||
|
||||
if (mmc->bus_width == 8) |
||||
host->bus_width = MMC_BUS_WIDTH_8; |
||||
else if (mmc->bus_width == 4) |
||||
host->bus_width = MMC_BUS_WIDTH_4; |
||||
else |
||||
host->bus_width = MMC_BUS_WIDTH_1; |
||||
|
||||
debug("clock = %d, buswidth = %d\n", mmc->clock, mmc->bus_width); |
||||
} |
||||
|
||||
static int sh_mmcif_init(struct mmc *mmc) |
||||
{ |
||||
struct sh_mmcif_host *host = mmc_priv(mmc); |
||||
|
||||
sh_mmcif_sync_reset(host); |
||||
sh_mmcif_write(MASK_ALL, &host->regs->ce_int_mask); |
||||
return 0; |
||||
} |
||||
|
||||
int mmcif_mmc_init(void) |
||||
{ |
||||
int ret = 0; |
||||
struct mmc *mmc; |
||||
struct sh_mmcif_host *host = NULL; |
||||
|
||||
mmc = malloc(sizeof(struct mmc)); |
||||
if (!mmc) |
||||
ret = -ENOMEM; |
||||
memset(mmc, 0, sizeof(*mmc)); |
||||
host = malloc(sizeof(struct sh_mmcif_host)); |
||||
if (!host) |
||||
ret = -ENOMEM; |
||||
memset(host, 0, sizeof(*host)); |
||||
|
||||
mmc->f_min = CLKDEV_MMC_INIT; |
||||
mmc->f_max = CLKDEV_EMMC_DATA; |
||||
mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; |
||||
mmc->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT | |
||||
MMC_MODE_8BIT; |
||||
memcpy(mmc->name, DRIVER_NAME, sizeof(DRIVER_NAME)); |
||||
mmc->send_cmd = sh_mmcif_request; |
||||
mmc->set_ios = sh_mmcif_set_ios; |
||||
mmc->init = sh_mmcif_init; |
||||
host->regs = (struct sh_mmcif_regs *)CONFIG_SH_MMCIF_ADDR; |
||||
host->clk = CONFIG_SH_MMCIF_CLK; |
||||
mmc->priv = host; |
||||
|
||||
mmc_register(mmc); |
||||
|
||||
return ret; |
||||
} |
@ -0,0 +1,238 @@ |
||||
/*
|
||||
* MMCIF driver. |
||||
* |
||||
* Copyright (C) 2011 Renesas Solutions Corp. |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License. |
||||
* |
||||
*/ |
||||
|
||||
#ifndef _SH_MMCIF_H_ |
||||
#define _SH_MMCIF_H_ |
||||
|
||||
struct sh_mmcif_regs { |
||||
unsigned long ce_cmd_set; |
||||
unsigned long reserved; |
||||
unsigned long ce_arg; |
||||
unsigned long ce_arg_cmd12; |
||||
unsigned long ce_cmd_ctrl; |
||||
unsigned long ce_block_set; |
||||
unsigned long ce_clk_ctrl; |
||||
unsigned long ce_buf_acc; |
||||
unsigned long ce_resp3; |
||||
unsigned long ce_resp2; |
||||
unsigned long ce_resp1; |
||||
unsigned long ce_resp0; |
||||
unsigned long ce_resp_cmd12; |
||||
unsigned long ce_data; |
||||
unsigned long reserved2[2]; |
||||
unsigned long ce_int; |
||||
unsigned long ce_int_mask; |
||||
unsigned long ce_host_sts1; |
||||
unsigned long ce_host_sts2; |
||||
unsigned long reserved3[11]; |
||||
unsigned long ce_version; |
||||
}; |
||||
|
||||
/* CE_CMD_SET */ |
||||
#define CMD_MASK 0x3f000000 |
||||
#define CMD_SET_RTYP_NO ((0 << 23) | (0 << 22)) |
||||
/* R1/R1b/R3/R4/R5 */ |
||||
#define CMD_SET_RTYP_6B ((0 << 23) | (1 << 22)) |
||||
/* R2 */ |
||||
#define CMD_SET_RTYP_17B ((1 << 23) | (0 << 22)) |
||||
/* R1b */ |
||||
#define CMD_SET_RBSY (1 << 21) |
||||
#define CMD_SET_CCSEN (1 << 20) |
||||
/* 1: on data, 0: no data */ |
||||
#define CMD_SET_WDAT (1 << 19) |
||||
/* 1: write to card, 0: read from card */ |
||||
#define CMD_SET_DWEN (1 << 18) |
||||
/* 1: multi block trans, 0: single */ |
||||
#define CMD_SET_CMLTE (1 << 17) |
||||
/* 1: CMD12 auto issue */ |
||||
#define CMD_SET_CMD12EN (1 << 16) |
||||
/* index check */ |
||||
#define CMD_SET_RIDXC_INDEX ((0 << 15) | (0 << 14)) |
||||
/* check bits check */ |
||||
#define CMD_SET_RIDXC_BITS ((0 << 15) | (1 << 14)) |
||||
/* no check */ |
||||
#define CMD_SET_RIDXC_NO ((1 << 15) | (0 << 14)) |
||||
/* 1: CRC7 check*/ |
||||
#define CMD_SET_CRC7C ((0 << 13) | (0 << 12)) |
||||
/* 1: check bits check*/ |
||||
#define CMD_SET_CRC7C_BITS ((0 << 13) | (1 << 12)) |
||||
/* 1: internal CRC7 check*/ |
||||
#define CMD_SET_CRC7C_INTERNAL ((1 << 13) | (0 << 12)) |
||||
/* 1: CRC16 check*/ |
||||
#define CMD_SET_CRC16C (1 << 10) |
||||
/* 1: not receive CRC status */ |
||||
#define CMD_SET_CRCSTE (1 << 8) |
||||
/* 1: tran mission bit "Low" */ |
||||
#define CMD_SET_TBIT (1 << 7) |
||||
/* 1: open/drain */ |
||||
#define CMD_SET_OPDM (1 << 6) |
||||
#define CMD_SET_CCSH (1 << 5) |
||||
/* 1bit */ |
||||
#define CMD_SET_DATW_1 ((0 << 1) | (0 << 0)) |
||||
/* 4bit */ |
||||
#define CMD_SET_DATW_4 ((0 << 1) | (1 << 0)) |
||||
/* 8bit */ |
||||
#define CMD_SET_DATW_8 ((1 << 1) | (0 << 0)) |
||||
|
||||
/* CE_CMD_CTRL */ |
||||
#define CMD_CTRL_BREAK (1 << 0) |
||||
|
||||
/* CE_BLOCK_SET */ |
||||
#define BLOCK_SIZE_MASK 0x0000ffff |
||||
|
||||
/* CE_CLK_CTRL */ |
||||
#define CLK_ENABLE (1 << 24) |
||||
#define CLK_CLEAR ((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16)) |
||||
#define CLK_PCLK ((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16)) |
||||
/* respons timeout */ |
||||
#define SRSPTO_256 ((1 << 13) | (0 << 12)) |
||||
/* respons busy timeout */ |
||||
#define SRBSYTO_29 ((1 << 11) | (1 << 10) | (1 << 9) | (1 << 8)) |
||||
/* read/write timeout */ |
||||
#define SRWDTO_29 ((1 << 7) | (1 << 6) | (1 << 5) | (1 << 4)) |
||||
/* ccs timeout */ |
||||
#define SCCSTO_29 ((1 << 3) | (1 << 2) | (1 << 1) | (1 << 0)) |
||||
|
||||
/* CE_BUF_ACC */ |
||||
#define BUF_ACC_DMAWEN (1 << 25) |
||||
#define BUF_ACC_DMAREN (1 << 24) |
||||
#define BUF_ACC_BUSW_32 (0 << 17) |
||||
#define BUF_ACC_BUSW_16 (1 << 17) |
||||
#define BUF_ACC_ATYP (1 << 16) |
||||
|
||||
/* CE_INT */ |
||||
#define INT_CCSDE (1 << 29) |
||||
#define INT_CMD12DRE (1 << 26) |
||||
#define INT_CMD12RBE (1 << 25) |
||||
#define INT_CMD12CRE (1 << 24) |
||||
#define INT_DTRANE (1 << 23) |
||||
#define INT_BUFRE (1 << 22) |
||||
#define INT_BUFWEN (1 << 21) |
||||
#define INT_BUFREN (1 << 20) |
||||
#define INT_CCSRCV (1 << 19) |
||||
#define INT_RBSYE (1 << 17) |
||||
#define INT_CRSPE (1 << 16) |
||||
#define INT_CMDVIO (1 << 15) |
||||
#define INT_BUFVIO (1 << 14) |
||||
#define INT_WDATERR (1 << 11) |
||||
#define INT_RDATERR (1 << 10) |
||||
#define INT_RIDXERR (1 << 9) |
||||
#define INT_RSPERR (1 << 8) |
||||
#define INT_CCSTO (1 << 5) |
||||
#define INT_CRCSTO (1 << 4) |
||||
#define INT_WDATTO (1 << 3) |
||||
#define INT_RDATTO (1 << 2) |
||||
#define INT_RBSYTO (1 << 1) |
||||
#define INT_RSPTO (1 << 0) |
||||
#define INT_ERR_STS (INT_CMDVIO | INT_BUFVIO | INT_WDATERR | \ |
||||
INT_RDATERR | INT_RIDXERR | INT_RSPERR | \
|
||||
INT_CCSTO | INT_CRCSTO | INT_WDATTO | \
|
||||
INT_RDATTO | INT_RBSYTO | INT_RSPTO) |
||||
#define INT_START_MAGIC 0xD80430C0 |
||||
|
||||
/* CE_INT_MASK */ |
||||
#define MASK_ALL 0x00000000 |
||||
#define MASK_MCCSDE (1 << 29) |
||||
#define MASK_MCMD12DRE (1 << 26) |
||||
#define MASK_MCMD12RBE (1 << 25) |
||||
#define MASK_MCMD12CRE (1 << 24) |
||||
#define MASK_MDTRANE (1 << 23) |
||||
#define MASK_MBUFRE (1 << 22) |
||||
#define MASK_MBUFWEN (1 << 21) |
||||
#define MASK_MBUFREN (1 << 20) |
||||
#define MASK_MCCSRCV (1 << 19) |
||||
#define MASK_MRBSYE (1 << 17) |
||||
#define MASK_MCRSPE (1 << 16) |
||||
#define MASK_MCMDVIO (1 << 15) |
||||
#define MASK_MBUFVIO (1 << 14) |
||||
#define MASK_MWDATERR (1 << 11) |
||||
#define MASK_MRDATERR (1 << 10) |
||||
#define MASK_MRIDXERR (1 << 9) |
||||
#define MASK_MRSPERR (1 << 8) |
||||
#define MASK_MCCSTO (1 << 5) |
||||
#define MASK_MCRCSTO (1 << 4) |
||||
#define MASK_MWDATTO (1 << 3) |
||||
#define MASK_MRDATTO (1 << 2) |
||||
#define MASK_MRBSYTO (1 << 1) |
||||
#define MASK_MRSPTO (1 << 0) |
||||
|
||||
/* CE_HOST_STS1 */ |
||||
#define STS1_CMDSEQ (1 << 31) |
||||
|
||||
/* CE_HOST_STS2 */ |
||||
#define STS2_CRCSTE (1 << 31) |
||||
#define STS2_CRC16E (1 << 30) |
||||
#define STS2_AC12CRCE (1 << 29) |
||||
#define STS2_RSPCRC7E (1 << 28) |
||||
#define STS2_CRCSTEBE (1 << 27) |
||||
#define STS2_RDATEBE (1 << 26) |
||||
#define STS2_AC12REBE (1 << 25) |
||||
#define STS2_RSPEBE (1 << 24) |
||||
#define STS2_AC12IDXE (1 << 23) |
||||
#define STS2_RSPIDXE (1 << 22) |
||||
#define STS2_CCSTO (1 << 15) |
||||
#define STS2_RDATTO (1 << 14) |
||||
#define STS2_DATBSYTO (1 << 13) |
||||
#define STS2_CRCSTTO (1 << 12) |
||||
#define STS2_AC12BSYTO (1 << 11) |
||||
#define STS2_RSPBSYTO (1 << 10) |
||||
#define STS2_AC12RSPTO (1 << 9) |
||||
#define STS2_RSPTO (1 << 8) |
||||
|
||||
#define STS2_CRC_ERR (STS2_CRCSTE | STS2_CRC16E | \ |
||||
STS2_AC12CRCE | STS2_RSPCRC7E | STS2_CRCSTEBE) |
||||
#define STS2_TIMEOUT_ERR (STS2_CCSTO | STS2_RDATTO | \ |
||||
STS2_DATBSYTO | STS2_CRCSTTO | \
|
||||
STS2_AC12BSYTO | STS2_RSPBSYTO | \
|
||||
STS2_AC12RSPTO | STS2_RSPTO) |
||||
|
||||
/* CE_VERSION */ |
||||
#define SOFT_RST_ON (1 << 31) |
||||
#define SOFT_RST_OFF (0 << 31) |
||||
|
||||
#define CLKDEV_EMMC_DATA 52000000 /* 52MHz */ |
||||
#define CLKDEV_MMC_INIT 400000 /* 100 - 400 KHz */ |
||||
|
||||
#define MMC_BUS_WIDTH_1 0 |
||||
#define MMC_BUS_WIDTH_4 2 |
||||
#define MMC_BUS_WIDTH_8 3 |
||||
|
||||
struct sh_mmcif_host { |
||||
struct mmc_data *data; |
||||
struct sh_mmcif_regs *regs; |
||||
unsigned int clk; |
||||
int bus_width; |
||||
u16 wait_int; |
||||
u16 sd_error; |
||||
u8 last_cmd; |
||||
}; |
||||
|
||||
static inline u32 sh_mmcif_read(unsigned long *reg) |
||||
{ |
||||
return readl(reg); |
||||
} |
||||
|
||||
static inline void sh_mmcif_write(u32 val, unsigned long *reg) |
||||
{ |
||||
writel(val, reg); |
||||
} |
||||
|
||||
static inline void sh_mmcif_bitset(u32 val, unsigned long *reg) |
||||
{ |
||||
sh_mmcif_write(val | sh_mmcif_read(reg), reg); |
||||
} |
||||
|
||||
static inline void sh_mmcif_bitclr(u32 val, unsigned long *reg) |
||||
{ |
||||
sh_mmcif_write(~val & sh_mmcif_read(reg), reg); |
||||
} |
||||
|
||||
#endif /* _SH_MMCIF_H_ */ |
Loading…
Reference in new issue