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@ -79,7 +79,7 @@ enum { |
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struct fdt_nand { |
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struct nand_ctlr *reg; |
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int enabled; /* 1 to enable, 0 to disable */ |
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struct fdt_gpio_state wp_gpio; /* write-protect GPIO */ |
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struct gpio_desc wp_gpio; /* write-protect GPIO */ |
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s32 width; /* bit width, normally 8 */ |
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u32 timing[FDT_NAND_TIMING_COUNT]; |
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}; |
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@ -945,8 +945,8 @@ static int fdt_decode_nand(const void *blob, int node, struct fdt_nand *config) |
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config->reg = (struct nand_ctlr *)fdtdec_get_addr(blob, node, "reg"); |
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config->enabled = fdtdec_get_is_enabled(blob, node); |
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config->width = fdtdec_get_int(blob, node, "nvidia,nand-width", 8); |
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err = fdtdec_decode_gpio(blob, node, "nvidia,wp-gpios", |
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&config->wp_gpio); |
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err = gpio_request_by_name_nodev(blob, node, "nvidia,wp-gpios", 0, |
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&config->wp_gpio, GPIOD_IS_OUT); |
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if (err) |
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return err; |
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err = fdtdec_get_int_array(blob, node, "nvidia,timing", |
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@ -1009,8 +1009,7 @@ int tegra_nand_init(struct nand_chip *nand, int devnum) |
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/* Adjust timing for NAND device */ |
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setup_timing(config->timing, info->reg); |
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fdtdec_setup_gpio(&config->wp_gpio); |
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gpio_direction_output(config->wp_gpio.gpio, 1); |
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dm_gpio_set_value(&config->wp_gpio, 1); |
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our_mtd = &nand_info[devnum]; |
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our_mtd->priv = nand; |
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