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@ -188,7 +188,7 @@ struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = { |
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.grp_b7ds = 0x00000030, |
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}; |
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/* MT41K128M16JT-125 */ |
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/* MT41K128M16JT-125 (2Gb density) */ |
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static struct mx6_ddr3_cfg mt41k128m16jt_125 = { |
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.mem_speed = 1600, |
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.density = 2, |
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@ -202,7 +202,7 @@ static struct mx6_ddr3_cfg mt41k128m16jt_125 = { |
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.trasmin = 3500, |
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}; |
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/* MT41K256M16HA-125 */ |
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/* MT41K256M16HA-125 (4Gb density) */ |
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static struct mx6_ddr3_cfg mt41k256m16ha_125 = { |
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.mem_speed = 1600, |
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.density = 4, |
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@ -297,6 +297,19 @@ static struct mx6_mmdc_calibration mx6dq_256x32_mmdc_calib = { |
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.p0_mpwrdlctl = 0x32363934, |
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}; |
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static struct mx6_mmdc_calibration mx6sdl_256x32_mmdc_calib = { |
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/* write leveling calibration determine */ |
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.p0_mpwldectrl0 = 0X00480047, |
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.p0_mpwldectrl1 = 0X003D003F, |
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/* Read DQS Gating calibration */ |
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.p0_mpdgctrl0 = 0X423E0241, |
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.p0_mpdgctrl1 = 0X022B022C, |
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/* Read Calibration: DQS delay relative to DQ read access */ |
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.p0_mprddlctl = 0X49454A4A, |
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/* Write Calibration: DQ/DM delay relative to DQS write access */ |
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.p0_mpwrdlctl = 0X2E372C32, |
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}; |
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static struct mx6_mmdc_calibration mx6dq_256x64_mmdc_calib = { |
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/* write leveling calibration determine */ |
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.p0_mpwldectrl0 = 0X00220021, |
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@ -368,6 +381,8 @@ static void spl_dram_init(int width, int size_mb, int board_model) |
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mem = &mt41k256m16ha_125; |
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if (is_cpu_type(MXC_CPU_MX6Q)) |
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calib = &mx6dq_256x32_mmdc_calib; |
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else |
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calib = &mx6sdl_256x32_mmdc_calib; |
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debug("4gB density\n"); |
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} else if (width == 64 && size_mb == 2048) { |
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mem = &mt41k256m16ha_125; |
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