Add Xianghua Xiao and Lunsheng Wang's support for the GDA MPC8540 EVAL board.master
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#
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# (C) Copyright 2001
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = lib$(BOARD).a
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OBJS := $(BOARD).o flash.o
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#OBJS := $(BOARD).o flash.o $(BOARD)_slave.o
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SOBJS := init.o
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#SOBJS :=
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$(LIB): $(OBJS) $(SOBJS) |
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$(AR) crv $@ $(OBJS)
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clean: |
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rm -f $(OBJS) $(SOBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) |
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$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
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-include .depend |
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#########################################################################
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@ -0,0 +1,34 @@ |
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# Modified by Xianghua Xiao, X.Xiao@motorola.com
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# (C) Copyright 2002,Motorola Inc.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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#
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# gda8540 board
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# default CCARBAR is at 0xff700000
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# assume U-Boot is less than 0.5MB
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#
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#TEXT_BASE = 0x1000000
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TEXT_BASE = 0xfff80000
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PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
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PLATFORM_CPPFLAGS += -DCONFIG_MPC8540=1
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PLATFORM_CPPFLAGS += -DCONFIG_E500=1
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@ -0,0 +1,892 @@ |
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/*
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* (C) Copyright 2003 Motorola Inc. |
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* Xianghua Xiao,(X.Xiao@motorola.com) |
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* |
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* (C) Copyright 2000, 2001 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com |
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* Add support the Sharp chips on the mpc8260ads. |
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* I started with board/ip860/flash.c and made changes I found in |
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* the MTD project by David Schleef. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#if !defined(CFG_NO_FLASH) |
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flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ |
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#if defined(CFG_ENV_IS_IN_FLASH) |
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# ifndef CFG_ENV_ADDR |
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# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) |
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# endif |
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# ifndef CFG_ENV_SIZE |
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# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE |
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# endif |
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# ifndef CFG_ENV_SECT_SIZE |
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# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE |
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# endif |
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#endif |
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/*
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* The variable should be in the flash info structure. Since it |
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* is only used in this board specific file it is declared here. |
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* In the future I think an endian flag should be part of the |
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* flash_info_t structure. (Ron Alder) |
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*/ |
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static ulong big_endian = 0; |
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/*-----------------------------------------------------------------------
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* Functions |
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*/ |
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static ulong flash_get_size (vu_long *addr, flash_info_t *info); |
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static int write_block (flash_info_t *info, uchar * src, ulong dest, ulong cnt); |
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static int write_short (flash_info_t *info, ulong dest, ushort data); |
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static int write_word (flash_info_t *info, ulong dest, ulong data); |
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static int clear_block_lock_bit(flash_info_t *info, vu_long * addr); |
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/*-----------------------------------------------------------------------
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*/ |
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unsigned long flash_init (void) |
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{ |
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unsigned long size; |
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int i; |
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/* Init: enable write,
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* or we cannot even write flash commands |
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*/ |
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for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { |
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flash_info[i].flash_id = FLASH_UNKNOWN; |
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/* set the default sector offset */ |
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} |
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/* Static FLASH Bank configuration here - FIXME XXX */ |
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size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); |
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if (flash_info[0].flash_id == FLASH_UNKNOWN) { |
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printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", |
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size, size<<20); |
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} |
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/* Re-do sizing to get full correct info */ |
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size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); |
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flash_info[0].size = size; |
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#if !defined(CONFIG_RAM_AS_FLASH) |
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#if CFG_MONITOR_BASE >= CFG_FLASH_BASE |
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/* monitor protection ON by default */ |
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flash_protect(FLAG_PROTECT_SET, |
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CFG_MONITOR_BASE, |
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CFG_MONITOR_BASE+monitor_flash_len-1, |
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&flash_info[0]); |
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#endif |
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#ifdef CFG_ENV_IS_IN_FLASH |
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/* ENV protection ON by default */ |
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flash_protect(FLAG_PROTECT_SET, |
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CFG_ENV_ADDR, |
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CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, |
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&flash_info[0]); |
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#endif |
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#endif |
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return (size); |
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} |
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/*-----------------------------------------------------------------------
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*/ |
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void flash_print_info (flash_info_t *info) |
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{ |
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int i; |
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if (info->flash_id == FLASH_UNKNOWN) { |
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printf ("missing or unknown FLASH type\n"); |
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return; |
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} |
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switch (info->flash_id & FLASH_VENDMASK) { |
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case FLASH_MAN_INTEL: printf ("Intel "); break; |
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case FLASH_MAN_SHARP: printf ("Sharp "); break; |
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default: printf ("Unknown Vendor "); break; |
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} |
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switch (info->flash_id & FLASH_TYPEMASK) { |
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case FLASH_28F016SV: printf ("28F016SV (16 Mbit, 32 x 64k)\n"); |
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break; |
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case FLASH_28F160S3: printf ("28F160S3 (16 Mbit, 32 x 512K)\n"); |
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break; |
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case FLASH_28F320S3: printf ("28F320S3 (32 Mbit, 64 x 512K)\n"); |
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break; |
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case FLASH_LH28F016SCT: printf ("28F016SC (16 Mbit, 32 x 64K)\n"); |
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break; |
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case FLASH_28F640J3A: printf ("28F640J3A (64 Mbit, 64 x 128K)\n"); |
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break; |
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default: printf ("Unknown Chip Type\n"); |
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break; |
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} |
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printf (" Size: %ld MB in %d Sectors\n", |
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info->size >> 20, info->sector_count); |
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printf (" Sector Start Addresses:"); |
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for (i=0; i<info->sector_count; ++i) { |
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if ((i % 5) == 0) |
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printf ("\n "); |
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printf (" %08lX%s", |
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info->start[i], |
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info->protect[i] ? " (RO)" : " " |
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); |
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} |
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printf ("\n"); |
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} |
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/* only deal with 16 bit and 32 bit port width, 16bit chip */ |
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static ulong flash_get_size (vu_long *addr, flash_info_t *info) |
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{ |
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short i; |
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ulong value,va,vb,vc,vd; |
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ulong base = (ulong)addr; |
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ulong sector_offset; |
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#ifdef DEBUG |
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printf("Check flash at 0x%08x\n",(uint)addr); |
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#endif |
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/* Write "Intelligent Identifier" command: read Manufacturer ID */ |
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*addr = 0x90909090; |
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udelay(20); |
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asm("sync"); |
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#ifndef CFG_FLASH_CFI |
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printf("Not define CFG_FLASH_CFI\n"); |
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return (0); |
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#else |
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value = addr[0]; |
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va=(value & 0xFF000000)>>24; |
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vb=(value & 0x00FF0000)>>16; |
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vc=(value & 0x0000FF00)>>8; |
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vd=(value & 0x000000FF); |
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if ((va==0) && (vb==0)) { |
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printf("cannot identify Flash\n"); |
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info->flash_id = FLASH_UNKNOWN; |
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info->sector_count = 0; |
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info->size = 0; |
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return (0); /* no or unknown flash */ |
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} |
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else if ((va==0) && (vb!=0)) { |
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big_endian = 1; |
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info->chipwidth = FLASH_CFI_BY16; |
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if(vb == vd) info->portwidth = FLASH_CFI_32BIT; |
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else info->portwidth = FLASH_CFI_16BIT; |
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} |
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else if ((va!=0) && (vb==0)) { |
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big_endian = 0; |
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info->chipwidth = FLASH_CFI_BY16; |
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if(va == vc) info->portwidth = FLASH_CFI_32BIT; |
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else info->portwidth = FLASH_CFI_16BIT; |
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} |
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else if ((va!=0) && (vb!=0)) { |
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big_endian = 1; /* no meaning for 8bit chip */ |
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info->chipwidth = FLASH_CFI_BY8; |
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if(va == vb) info->portwidth = FLASH_CFI_16BIT; |
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else info->portwidth = FLASH_CFI_8BIT; |
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} |
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#ifdef DEBUG |
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switch (info->portwidth) { |
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case FLASH_CFI_8BIT: |
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printf("port width is 8 bit.\n"); |
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break; |
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case FLASH_CFI_16BIT: |
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printf("port width is 16 bit, "); |
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break; |
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case FLASH_CFI_32BIT: |
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printf("port width is 32 bit, "); |
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break; |
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} |
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switch (info->chipwidth) { |
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case FLASH_CFI_BY16: |
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printf("chip width is 16 bit, "); |
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switch (big_endian) { |
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case 0: |
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printf("Little Endian.\n"); |
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break; |
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case 1: |
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printf("Big Endian.\n"); |
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break; |
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} |
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break; |
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} |
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#endif |
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#endif /*#ifdef CFG_FLASH_CFI*/ |
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if (big_endian==0) value = (addr[0] & 0xFF000000) >>8; |
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else value = (addr[0] & 0x00FF0000); |
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#ifdef DEBUG |
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printf("manufacturer=0x%x\n",(uint)(value>>16)); |
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#endif |
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switch (value) { |
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case MT_MANUFACT & 0xFFFF0000: /* SHARP, MT or => Intel */ |
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case INTEL_ALT_MANU & 0xFFFF0000: |
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info->flash_id = FLASH_MAN_INTEL; |
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break; |
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default: |
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printf("unknown manufacturer: %x\n", (unsigned int)value); |
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info->flash_id = FLASH_UNKNOWN; |
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info->sector_count = 0; |
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info->size = 0; |
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return (0); /* no or unknown flash */ |
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} |
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if (info->portwidth==FLASH_CFI_16BIT) { |
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switch (big_endian) { |
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case 0: |
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value = (addr[0] & 0x0000FF00)>>8; |
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break; |
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case 1: |
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value = (addr[0] & 0x000000FF); |
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break; |
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} |
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} |
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else if (info->portwidth == FLASH_CFI_32BIT) { |
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switch (big_endian) { |
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case 0: |
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value = (addr[1] & 0x0000FF00)>>8; |
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break; |
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case 1: |
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value = (addr[1] & 0x000000FF); |
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break; |
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} |
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} |
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#ifdef DEBUG |
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printf("deviceID=0x%x\n",(uint)value); |
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#endif |
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switch (value) { |
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case (INTEL_ID_28F016S & 0x0000FFFF): |
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info->flash_id += FLASH_28F016SV; |
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info->sector_count = 32; |
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sector_offset = 0x10000; |
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break; /* => 2 MB */ |
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case (INTEL_ID_28F160S3 & 0x0000FFFF): |
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info->flash_id += FLASH_28F160S3; |
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info->sector_count = 32; |
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sector_offset = 0x10000; |
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break; /* => 2 MB */ |
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case (INTEL_ID_28F320S3 & 0x0000FFFF): |
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info->flash_id += FLASH_28F320S3; |
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info->sector_count = 64; |
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sector_offset = 0x10000; |
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break; /* => 4 MB */ |
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case (INTEL_ID_28F640J3A & 0x0000FFFF): |
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info->flash_id += FLASH_28F640J3A; |
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info->sector_count = 64; |
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sector_offset = 0x20000; |
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break; /* => 8 MB */ |
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case SHARP_ID_28F016SCL & 0x0000FFFF: |
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case SHARP_ID_28F016SCZ & 0x0000FFFF: |
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info->flash_id = FLASH_MAN_SHARP | FLASH_LH28F016SCT; |
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info->sector_count = 32; |
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sector_offset = 0x10000; |
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break; /* => 2 MB */ |
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default: |
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info->flash_id = FLASH_UNKNOWN; |
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return (0); /* => no or unknown flash */ |
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} |
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sector_offset = sector_offset * (info->portwidth / info->chipwidth); |
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info->size = info->sector_count * sector_offset; |
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/* set up sector start address table */ |
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for (i = 0; i < info->sector_count; i++) { |
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info->start[i] = base; |
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base += sector_offset; |
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/* don't know how to check sector protection */ |
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info->protect[i] = 0; |
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} |
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/*
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* Prevent writes to uninitialized FLASH. |
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*/ |
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if (info->flash_id != FLASH_UNKNOWN) { |
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addr = (vu_long *)info->start[0]; |
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*addr = 0xFFFFFF; /* reset bank to read array mode */ |
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asm("sync"); |
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} |
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return (info->size); |
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} |
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/*-----------------------------------------------------------------------
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*/ |
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int flash_erase (flash_info_t *info, int s_first, int s_last) |
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{ |
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int flag, prot, sect; |
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ulong start, now, last, ready, erase_err_status; |
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if (big_endian == 1) { |
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ready = 0x0080; |
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erase_err_status = 0x00a0; |
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} |
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else { |
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ready = 0x8000; |
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erase_err_status = 0xa000; |
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} |
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if ((info->portwidth / info->chipwidth)==2) { |
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ready += (ready <<16); |
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erase_err_status += (erase_err_status <<16); |
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} |
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#ifdef DEBUG |
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printf ("\nReady flag is 0x%lx\nErase error flag is 0x%lx", ready, erase_err_status); |
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#endif |
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if ((s_first < 0) || (s_first > s_last)) { |
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if (info->flash_id == FLASH_UNKNOWN) { |
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printf ("- missing\n"); |
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} else { |
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printf ("- no sectors to erase\n"); |
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} |
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return 1; |
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} |
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if ( ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) |
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&& ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_SHARP) ) { |
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printf ("Can't erase unknown flash type %08lx - aborted\n", |
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info->flash_id); |
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return 1; |
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} |
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prot = 0; |
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for (sect=s_first; sect<=s_last; ++sect) { |
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if (info->protect[sect]) { |
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prot++; |
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} |
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} |
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if (prot) { |
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printf ("- Warning: %d protected sectors will not be erased!\n", |
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prot); |
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} else { |
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printf ("\n"); |
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} |
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#ifdef DEBUG |
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printf("\nFlash Erase:\n"); |
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#endif |
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/* Make Sure Block Lock Bit is not set. */ |
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if(clear_block_lock_bit(info, (vu_long *)(info->start[s_first]))){ |
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return 1; |
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} |
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/* Start erase on unprotected sectors */ |
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#if defined(DEBUG) |
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printf("Begin to erase now,s_first=0x%x s_last=0x%x...\n",s_first,s_last); |
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#endif |
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for (sect = s_first; sect<=s_last; sect++) { |
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if (info->protect[sect] == 0) { /* not protected */ |
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vu_short *addr16 = (vu_short *)(info->start[sect]); |
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vu_long *addr = (vu_long *)(info->start[sect]); |
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printf("."); |
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switch (info->portwidth) { |
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case FLASH_CFI_16BIT: |
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asm("sync"); |
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last = start = get_timer (0); |
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/* Disable interrupts which might cause a timeout here */ |
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flag = disable_interrupts(); |
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/* Reset Array */ |
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*addr16 = 0xffff; |
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asm("sync"); |
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/* Clear Status Register */ |
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*addr16 = 0x5050; |
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asm("sync"); |
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/* Single Block Erase Command */ |
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*addr16 = 0x2020; |
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asm("sync"); |
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/* Confirm */ |
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*addr16 = 0xD0D0; |
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asm("sync"); |
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if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) { |
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/* Resume Command, as per errata update */ |
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*addr16 = 0xD0D0; |
||||
asm("sync"); |
||||
} |
||||
/* re-enable interrupts if necessary */ |
||||
if (flag) |
||||
enable_interrupts(); |
||||
/* wait at least 80us - let's wait 1 ms */ |
||||
*addr16 = 0x7070; |
||||
udelay (1000); |
||||
while ((*addr16 & ready) != ready) { |
||||
if((*addr16 & erase_err_status)== erase_err_status){ |
||||
printf("Error in Block Erase - Lock Bit may be set!\n"); |
||||
printf("Status Register = 0x%X\n", (uint)*addr16); |
||||
*addr16 = 0xFFFF; /* reset bank */ |
||||
asm("sync"); |
||||
return 1; |
||||
} |
||||
if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { |
||||
printf ("Timeout\n"); |
||||
*addr16 = 0xFFFF; /* reset bank */ |
||||
asm("sync"); |
||||
return 1; |
||||
} |
||||
/* show that we're waiting */ |
||||
if ((now - last) > 1000) { /* every second */ |
||||
putc ('.'); |
||||
last = now; |
||||
} |
||||
} |
||||
/* reset to read mode */ |
||||
*addr16 = 0xFFFF; |
||||
asm("sync"); |
||||
break; |
||||
case FLASH_CFI_32BIT: |
||||
asm("sync"); |
||||
last = start = get_timer (0); |
||||
/* Disable interrupts which might cause a timeout here */ |
||||
flag = disable_interrupts(); |
||||
/* Reset Array */ |
||||
*addr = 0xffffffff; |
||||
asm("sync"); |
||||
/* Clear Status Register */ |
||||
*addr = 0x50505050; |
||||
asm("sync"); |
||||
/* Single Block Erase Command */ |
||||
*addr = 0x20202020; |
||||
asm("sync"); |
||||
/* Confirm */ |
||||
*addr = 0xD0D0D0D0; |
||||
asm("sync"); |
||||
if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) { |
||||
/* Resume Command, as per errata update */ |
||||
*addr = 0xD0D0D0D0; |
||||
asm("sync"); |
||||
} |
||||
/* re-enable interrupts if necessary */ |
||||
if (flag) |
||||
enable_interrupts(); |
||||
/* wait at least 80us - let's wait 1 ms */ |
||||
*addr = 0x70707070; |
||||
udelay (1000); |
||||
while ((*addr & ready) != ready) { |
||||
if((*addr & erase_err_status)==erase_err_status){ |
||||
printf("Error in Block Erase - Lock Bit may be set!\n"); |
||||
printf("Status Register = 0x%X\n", (uint)*addr); |
||||
*addr = 0xFFFFFFFF; /* reset bank */ |
||||
asm("sync"); |
||||
return 1; |
||||
} |
||||
if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { |
||||
printf ("Timeout\n"); |
||||
*addr = 0xFFFFFFFF; /* reset bank */ |
||||
asm("sync"); |
||||
return 1; |
||||
} |
||||
/* show that we're waiting */ |
||||
if ((now - last) > 1000) { /* every second */ |
||||
putc ('.'); |
||||
last = now; |
||||
} |
||||
} |
||||
/* reset to read mode */ |
||||
*addr = 0xFFFFFFFF; |
||||
asm("sync"); |
||||
break; |
||||
} /* end switch */ |
||||
} /* end if */ |
||||
} /* end for */ |
||||
|
||||
printf ("flash erase done\n"); |
||||
return 0; |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Copy memory to flash, returns: |
||||
* 0 - OK |
||||
* 1 - write timeout |
||||
* 2 - Flash not erased |
||||
*/ |
||||
|
||||
#define FLASH_BLOCK_SIZE 32 |
||||
|
||||
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) |
||||
{ |
||||
ulong cp, wp, data, count, temp; |
||||
/* ulong temp[FLASH_BLOCK_SIZE/4];*/ |
||||
int i, l, rc; |
||||
|
||||
count = cnt; |
||||
wp = (addr & ~3); /* get lower word aligned address */ |
||||
|
||||
/*
|
||||
* handle unaligned start bytes |
||||
*/ |
||||
if ((l = addr - wp) != 0) { |
||||
data = 0; |
||||
for (i=0, cp=wp; i<l; ++i, ++cp) { |
||||
data = (data << 8) | (*(uchar *)cp); |
||||
} |
||||
for (; i<4 && cnt>0; ++i) { |
||||
data = (data << 8) | *src++; |
||||
--cnt; |
||||
++cp; |
||||
} |
||||
for (; cnt==0 && i<4; ++i, ++cp) { |
||||
data = (data << 8) | (*(uchar *)cp); |
||||
} |
||||
|
||||
if ((rc = write_word(info, wp, data)) != 0) { |
||||
return (rc); |
||||
} |
||||
wp += 4; |
||||
} |
||||
|
||||
cp = wp; |
||||
/* handle unaligned block bytes , flash block size = 16bytes */ |
||||
wp = (cp+FLASH_BLOCK_SIZE-1) & ~(FLASH_BLOCK_SIZE-1); |
||||
if ((wp-cp)>=cnt) { |
||||
if ((rc = write_block(info,src,cp,wp-cp)) !=0) |
||||
return (rc); |
||||
src += wp-cp; |
||||
cnt -= wp-cp; |
||||
} |
||||
/* handle aligned block bytes */ |
||||
temp = 0; |
||||
printf("\n"); |
||||
while ( cnt >= FLASH_BLOCK_SIZE) { |
||||
if ((rc = write_block(info,src,cp,FLASH_BLOCK_SIZE)) !=0) { |
||||
return (rc); |
||||
} |
||||
src += FLASH_BLOCK_SIZE; |
||||
cp += FLASH_BLOCK_SIZE; |
||||
cnt -= FLASH_BLOCK_SIZE; |
||||
if (((count-cnt)>>10)>temp) { |
||||
temp=(count-cnt)>>10; |
||||
printf("\r%d KB",temp); |
||||
} |
||||
} |
||||
printf("\n"); |
||||
wp = cp; |
||||
/*
|
||||
* handle word aligned part |
||||
*/ |
||||
while (cnt >= 4) { |
||||
data = 0; |
||||
for (i=0; i<4; ++i) { |
||||
data = (data << 8) | *src++; |
||||
} |
||||
if ((rc = write_word(info, wp, data)) != 0) { |
||||
return (rc); |
||||
} |
||||
wp += 4; |
||||
cnt -= 4; |
||||
} |
||||
|
||||
if (cnt == 0) { |
||||
return (0); |
||||
} |
||||
|
||||
/*
|
||||
* handle unaligned tail bytes |
||||
*/ |
||||
data = 0; |
||||
for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { |
||||
data = (data << 8) | *src++; |
||||
--cnt; |
||||
} |
||||
for (; i<4; ++i, ++cp) { |
||||
data = (data << 8) | (*(uchar *)cp); |
||||
} |
||||
|
||||
return (write_word(info, wp, data)); |
||||
} |
||||
#undef FLASH_BLOCK_SIZE |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Write block to Flash, returns: |
||||
* 0 - OK |
||||
* 1 - write timeout |
||||
* 2 - Flash not erased |
||||
* -1 Error |
||||
*/ |
||||
static int write_block(flash_info_t *info, uchar * src, ulong dest, ulong cnt) |
||||
{ |
||||
vu_short *baddr, *addr = (vu_short *)dest; |
||||
ushort data; |
||||
ulong start, now, xsr,csr, ready; |
||||
int flag; |
||||
|
||||
if (cnt==0) return 0; |
||||
else if(cnt != (cnt& ~1)) return -1; |
||||
|
||||
/* Check if Flash is (sufficiently) erased */ |
||||
data = * src; |
||||
data = (data<<8) | *(src+1); |
||||
if ((*addr & data) != data) { |
||||
return (2); |
||||
} |
||||
if (big_endian == 1) { |
||||
ready = 0x0080; |
||||
} |
||||
else { |
||||
ready = 0x8000; |
||||
} |
||||
/* Disable interrupts which might cause a timeout here */ |
||||
flag = disable_interrupts(); |
||||
|
||||
do { |
||||
/* Write Command */ |
||||
*addr = 0xe8e8; |
||||
asm("sync"); |
||||
xsr = *addr; |
||||
asm("sync"); |
||||
} while (!(xsr & ready)); /*wait until read */ |
||||
/*write count=BLOCK SIZE -1 */ |
||||
data=(cnt>>1)-1; |
||||
data=(data<<8)|data; |
||||
*addr = data; /* word mode, cnt/2 */ |
||||
asm("sync"); |
||||
baddr = addr; |
||||
while(cnt) { |
||||
data = * src++; |
||||
data = (data<<8) | *src++; |
||||
asm("sync"); |
||||
*baddr = data; |
||||
asm("sync"); |
||||
++baddr; |
||||
cnt = cnt -2; |
||||
} |
||||
*addr = 0xd0d0; /* confirm write */ |
||||
start = get_timer(0); |
||||
asm("sync"); |
||||
if (flag) |
||||
enable_interrupts(); |
||||
/* data polling for D7 */ |
||||
flag = 0; |
||||
while (((csr = *addr) & ready) != ready) { |
||||
if ((now=get_timer(start)) > CFG_FLASH_WRITE_TOUT) { |
||||
flag = 1; |
||||
break; |
||||
} |
||||
} |
||||
if (csr & 0x4040) { |
||||
printf ("CSR indicates write error (%04x) at %08lx\n", csr, (ulong)addr); |
||||
flag = 1; |
||||
} |
||||
/* Clear Status Registers Command */ |
||||
*addr = 0x5050; |
||||
asm("sync"); |
||||
/* Reset to read array mode */ |
||||
*addr = 0xFFFF; |
||||
asm("sync"); |
||||
return (flag); |
||||
} |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Write a short word to Flash, returns: |
||||
* 0 - OK |
||||
* 1 - write timeout |
||||
* 2 - Flash not erased |
||||
*/ |
||||
static int write_short (flash_info_t *info, ulong dest, ushort data) |
||||
{ |
||||
vu_short *addr = (vu_short *)dest; |
||||
ulong start, now, csr, ready; |
||||
int flag; |
||||
|
||||
/* Check if Flash is (sufficiently) erased */ |
||||
if ((*addr & data) != data) { |
||||
return (2); |
||||
} |
||||
/* Disable interrupts which might cause a timeout here */ |
||||
flag = disable_interrupts(); |
||||
|
||||
/* Write Command */ |
||||
*addr = 0x1010; |
||||
start = get_timer (0); |
||||
asm("sync"); |
||||
/* Write Data */ |
||||
*addr = data; |
||||
asm("sync"); |
||||
/* re-enable interrupts if necessary */ |
||||
if (flag) |
||||
enable_interrupts(); |
||||
if (big_endian == 1) { |
||||
ready = 0x0080; |
||||
} |
||||
else { |
||||
ready = 0x8000; |
||||
} |
||||
/* data polling for D7 */ |
||||
flag = 0; |
||||
while (((csr = *addr) & ready) != ready) { |
||||
if ((now=get_timer(start)) > CFG_FLASH_WRITE_TOUT) { |
||||
flag = 1; |
||||
break; |
||||
} |
||||
} |
||||
if (csr & 0x4040) { |
||||
printf ("CSR indicates write error (%04x) at %08lx\n", csr, (ulong)addr); |
||||
flag = 1; |
||||
} |
||||
/* Clear Status Registers Command */ |
||||
*addr = 0x5050; |
||||
asm("sync"); |
||||
/* Reset to read array mode */ |
||||
*addr = 0xFFFF; |
||||
asm("sync"); |
||||
return (flag); |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Write a word to Flash, returns: |
||||
* 0 - OK |
||||
* 1 - write timeout |
||||
* 2 - Flash not erased |
||||
*/ |
||||
static int write_word (flash_info_t *info, ulong dest, ulong data) |
||||
{ |
||||
vu_long *addr = (vu_long *)dest; |
||||
ulong start, csr, ready; |
||||
int flag=0; |
||||
|
||||
switch (info->portwidth) { |
||||
case FLASH_CFI_32BIT: |
||||
/* Check if Flash is (sufficiently) erased */ |
||||
if ((*addr & data) != data) { |
||||
return (2); |
||||
} |
||||
/* Disable interrupts which might cause a timeout here */ |
||||
flag = disable_interrupts(); |
||||
|
||||
if (big_endian == 1) { |
||||
ready = 0x0080; |
||||
} |
||||
else { |
||||
ready = 0x8000; |
||||
} |
||||
if ((info->portwidth / info->chipwidth)==2) { |
||||
ready += (ready <<16); |
||||
} |
||||
else { |
||||
ready = ready << 16; |
||||
} |
||||
/* Write Command */ |
||||
*addr = 0x10101010; |
||||
asm("sync"); |
||||
/* Write Data */ |
||||
*addr = data; |
||||
/* re-enable interrupts if necessary */ |
||||
if (flag) |
||||
enable_interrupts(); |
||||
/* data polling for D7 */ |
||||
start = get_timer (0); |
||||
flag = 0; |
||||
while (((csr = *addr) & ready) != ready) { |
||||
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { |
||||
flag = 1; |
||||
break; |
||||
} |
||||
} |
||||
if (csr & 0x40404040) { |
||||
printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr); |
||||
flag = 1; |
||||
} |
||||
/* Clear Status Registers Command */ |
||||
*addr = 0x50505050; |
||||
asm("sync"); |
||||
/* Reset to read array mode */ |
||||
*addr = 0xFFFFFFFF; |
||||
asm("sync"); |
||||
break; |
||||
case FLASH_CFI_16BIT: |
||||
flag = write_short (info, dest, (unsigned short) (data>>16)); |
||||
if (flag == 0) |
||||
flag = write_short (info, dest+2, (unsigned short) (data)); |
||||
break; |
||||
} |
||||
return (flag); |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Clear Block Lock Bit, returns: |
||||
* 0 - OK |
||||
* 1 - Timeout |
||||
*/ |
||||
|
||||
static int clear_block_lock_bit(flash_info_t * info, vu_long * addr) |
||||
{ |
||||
ulong start, now, ready; |
||||
|
||||
/* Reset Array */ |
||||
*addr = 0xffffffff; |
||||
asm("sync"); |
||||
/* Clear Status Register */ |
||||
*addr = 0x50505050; |
||||
asm("sync"); |
||||
|
||||
*addr = 0x60606060; |
||||
asm("sync"); |
||||
*addr = 0xd0d0d0d0; |
||||
asm("sync"); |
||||
|
||||
|
||||
if (big_endian == 1) { |
||||
ready = 0x0080; |
||||
} |
||||
else { |
||||
ready = 0x8000; |
||||
} |
||||
if ((info->portwidth / info->chipwidth)==2) { |
||||
ready += (ready <<16); |
||||
} |
||||
else { |
||||
ready = ready << 16; |
||||
} |
||||
#ifdef DEBUG |
||||
printf ("%s: Ready flag is 0x%8lx\n", __FUNCTION__, ready); |
||||
#endif |
||||
*addr = 0x70707070; /* read status */ |
||||
start = get_timer (0); |
||||
while((*addr & ready) != ready){ |
||||
if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { |
||||
printf ("Timeout on clearing Block Lock Bit\n"); |
||||
*addr = 0xFFFFFFFF; /* reset bank */ |
||||
asm("sync"); |
||||
return 1; |
||||
} |
||||
} |
||||
return 0; |
||||
} |
||||
|
||||
#endif /* !CFG_NO_FLASH */ |
@ -0,0 +1,178 @@ |
||||
/* |
||||
* Copyright (C) 2002,2003, Motorola Inc. |
||||
* Xianghua Xiao <X.Xiao@motorola.com>
|
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <ppc_asm.tmpl> |
||||
#include <ppc_defs.h> |
||||
#include <asm/cache.h> |
||||
#include <asm/mmu.h> |
||||
#include <config.h> |
||||
#include <mpc85xx.h> |
||||
|
||||
#define entry_start \ |
||||
mflr r1 ; \
|
||||
bl 0f ;
|
||||
|
||||
#define entry_end \ |
||||
0: mflr r0 ; \
|
||||
mtlr r1 ; \
|
||||
blr ;
|
||||
|
||||
/* TLB1 entries configuration: */ |
||||
|
||||
.section .bootpg, "ax" |
||||
.globl tlb1_entry
|
||||
tlb1_entry: |
||||
entry_start |
||||
|
||||
.long 0x0a /* the following data table uses a few of 16 TLB entries */ |
||||
|
||||
.long TLB1_MAS0(1,1,0) |
||||
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M) |
||||
.long TLB1_MAS2(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,1,0,1,0) |
||||
.long TLB1_MAS3(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) |
||||
|
||||
#if defined(CFG_FLASH_PORT_WIDTH_16) |
||||
.long TLB1_MAS0(1,2,0) |
||||
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_4M) |
||||
.long TLB1_MAS2(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0) |
||||
.long TLB1_MAS3(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) |
||||
|
||||
.long TLB1_MAS0(1,3,0) |
||||
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_4M) |
||||
.long TLB1_MAS2((((CFG_FLASH_BASE+0x400000)>>12)&0xfffff),0,0,0,0,1,0,1,0) |
||||
.long TLB1_MAS3((((CFG_FLASH_BASE+0x400000)>>12)&0xfffff),0,0,0,0,0,1,0,1,0,1) |
||||
#else |
||||
.long TLB1_MAS0(1,2,0) |
||||
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16M) |
||||
.long TLB1_MAS2(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0) |
||||
.long TLB1_MAS3(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) |
||||
|
||||
.long TLB1_MAS0(1,3,0) |
||||
.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M) |
||||
.long TLB1_MAS2(0,0,0,0,0,0,0,0,0) |
||||
.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1) |
||||
#endif |
||||
|
||||
#if !defined(CONFIG_SPD_EEPROM) |
||||
.long TLB1_MAS0(1,4,0) |
||||
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M) |
||||
.long TLB1_MAS2(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0) |
||||
.long TLB1_MAS3(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) |
||||
|
||||
.long TLB1_MAS0(1,5,0) |
||||
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M) |
||||
.long TLB1_MAS2((((CFG_DDR_SDRAM_BASE+0x4000000)>>12) & 0xfffff),0,0,0,0,0,0,0,0) |
||||
.long TLB1_MAS3((((CFG_DDR_SDRAM_BASE+0x4000000)>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) |
||||
#else |
||||
.long TLB1_MAS0(1,4,0) |
||||
.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M) |
||||
.long TLB1_MAS2(0,0,0,0,0,0,0,0,0) |
||||
.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1) |
||||
|
||||
.long TLB1_MAS0(1,5,0) |
||||
.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M) |
||||
.long TLB1_MAS2(0,0,0,0,0,0,0,0,0) |
||||
.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1) |
||||
#endif |
||||
|
||||
.long TLB1_MAS0(1,6,0) |
||||
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M) |
||||
#if defined(CONFIG_RAM_AS_FLASH) |
||||
.long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0) |
||||
#else |
||||
.long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0) |
||||
#endif |
||||
.long TLB1_MAS3(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) |
||||
|
||||
.long TLB1_MAS0(1,7,0) |
||||
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K) |
||||
#ifdef CONFIG_L2_INIT_RAM |
||||
.long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,1,0,0,0,0) |
||||
#else |
||||
.long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,0,0,0) |
||||
#endif |
||||
.long TLB1_MAS3(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) |
||||
|
||||
.long TLB1_MAS0(1,8,0) |
||||
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M) |
||||
.long TLB1_MAS2(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0) |
||||
.long TLB1_MAS3(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) |
||||
|
||||
.long TLB1_MAS0(1,9,0) |
||||
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K) |
||||
.long TLB1_MAS2(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,1,0,1,0) |
||||
.long TLB1_MAS3(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) |
||||
|
||||
#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) |
||||
.long TLB1_MAS0(1,15,0) |
||||
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M) |
||||
.long TLB1_MAS2(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,1,0,1,0) |
||||
.long TLB1_MAS3(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) |
||||
#else |
||||
.long TLB1_MAS0(1,15,0) |
||||
.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M) |
||||
.long TLB1_MAS2(0,0,0,0,0,0,0,0,0) |
||||
.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1) |
||||
#endif |
||||
entry_end |
||||
|
||||
/* LAW(Local Access Window) configuration: |
||||
* 0000_0000-0800_0000: DDR(128M) -or- larger |
||||
* f000_0000-f3ff_ffff: PCI(256M) |
||||
* f400_0000-f7ff_ffff: RapidIO(128M) |
||||
* f800_0000-ffff_ffff: localbus(128M) |
||||
* f800_0000-fbff_ffff: LBC SDRAM(64M) |
||||
* fc00_0000-fdef_ffff: LBC BCSR,RTC,etc(31M) |
||||
* fdf0_0000-fdff_ffff: CCSRBAR(1M) |
||||
* fe00_0000-ffff_ffff: Flash(32M) |
||||
* Note: CCSRBAR and L2-as-SRAM don't need configure Local Access |
||||
* Window. |
||||
* Note: If flash is 8M at default position(last 8M),no LAW needed. |
||||
*/ |
||||
|
||||
#if !defined(CONFIG_SPD_EEPROM) |
||||
#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff) |
||||
#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) |
||||
#else |
||||
#define LAWBAR0 0 |
||||
#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) |
||||
#endif |
||||
|
||||
#define LAWBAR1 ((CFG_PCI_MEM_BASE>>12) & 0xfffff) |
||||
#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_256M)) |
||||
|
||||
#if !defined(CONFIG_RAM_AS_FLASH) |
||||
#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) |
||||
#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M)) |
||||
#else |
||||
#define LAWBAR2 0 |
||||
#define LAWAR2 ((LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) |
||||
#endif |
||||
|
||||
.section .bootpg, "ax" |
||||
.globl law_entry
|
||||
law_entry: |
||||
entry_start |
||||
.long 0x03
|
||||
.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2 |
||||
entry_end |
@ -0,0 +1,271 @@ |
||||
/*
|
||||
* (C) Copyright 2002,2003, Motorola Inc. |
||||
* Xianghua Xiao, (X.Xiao@motorola.com) |
||||
* |
||||
* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
|
||||
extern long int spd_sdram (void); |
||||
|
||||
#include <common.h> |
||||
#include <asm/processor.h> |
||||
#include <asm/immap_85xx.h> |
||||
#include <spd.h> |
||||
|
||||
|
||||
|
||||
long int fixed_sdram (void); |
||||
|
||||
/* MPC8540ADS Board Status & Control Registers */ |
||||
#if 0 |
||||
typedef struct bscr_ { |
||||
unsigned long bcsr0; |
||||
unsigned long bcsr1; |
||||
unsigned long bcsr2; |
||||
unsigned long bcsr3; |
||||
unsigned long bcsr4; |
||||
unsigned long bcsr5; |
||||
unsigned long bcsr6; |
||||
unsigned long bcsr7; |
||||
} bcsr_t; |
||||
#endif |
||||
|
||||
|
||||
|
||||
int board_pre_init (void) |
||||
{ |
||||
#if defined(CONFIG_PCI) |
||||
volatile immap_t *immr = (immap_t *)CFG_IMMR; |
||||
volatile ccsr_pcix_t *pci = &immr->im_pcix; |
||||
|
||||
pci->peer &= 0xffffffdf; /* disable master abort */ |
||||
#endif |
||||
return 0; |
||||
} |
||||
|
||||
int checkboard (void) |
||||
{ |
||||
sys_info_t sysinfo; |
||||
|
||||
get_sys_info (&sysinfo); |
||||
|
||||
printf ("Board: Freescale MPC8540EVAL Board\n"); |
||||
printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000); |
||||
printf ("\tCCB: %lu MHz\n", sysinfo.freqSystemBus / 1000000); |
||||
printf ("\tDDR: %lu MHz\n", sysinfo.freqSystemBus / 2000000); |
||||
if((CFG_LBC_LCRR & 0x0f) == 2 || (CFG_LBC_LCRR & 0x0f) == 4 \
|
||||
|| (CFG_LBC_LCRR & 0x0f) == 8) { |
||||
printf ("\tLBC: %lu MHz\n", sysinfo.freqSystemBus / 1000000 /(CFG_LBC_LCRR & 0x0f)); |
||||
} else { |
||||
printf("\tLBC: unknown\n"); |
||||
} |
||||
printf("L1 D-cache 32KB, L1 I-cache 32KB enabled.\n"); |
||||
return (0); |
||||
} |
||||
|
||||
long int initdram (int board_type) |
||||
{ |
||||
long dram_size = 0; |
||||
extern long spd_sdram (void); |
||||
volatile immap_t *immap = (immap_t *)CFG_IMMR; |
||||
#if !defined(CONFIG_RAM_AS_FLASH) |
||||
volatile ccsr_lbc_t *lbc= &immap->im_lbc; |
||||
sys_info_t sysinfo; |
||||
uint temp_lbcdll = 0; |
||||
#endif |
||||
#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL) |
||||
volatile ccsr_gur_t *gur= &immap->im_gur; |
||||
#endif |
||||
|
||||
#if defined(CONFIG_DDR_DLL) |
||||
uint temp_ddrdll = 0; |
||||
|
||||
/* Work around to stabilize DDR DLL */ |
||||
temp_ddrdll = gur->ddrdllcr; |
||||
gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000; |
||||
asm("sync;isync;msync"); |
||||
#endif |
||||
|
||||
#if defined(CONFIG_SPD_EEPROM) |
||||
dram_size = spd_sdram (); |
||||
#else |
||||
dram_size = fixed_sdram (); |
||||
#endif |
||||
|
||||
#if defined(CFG_RAMBOOT) |
||||
return dram_size; |
||||
#endif |
||||
|
||||
#if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus is not emulating flash */ |
||||
get_sys_info(&sysinfo); |
||||
/* if localbus freq is less than 66Mhz,we use bypass mode,otherwise use DLL */ |
||||
if(sysinfo.freqSystemBus/(CFG_LBC_LCRR & 0x0f) < 66000000) { |
||||
lbc->lcrr = (CFG_LBC_LCRR & 0x0fffffff)| 0x80000000; |
||||
} else { |
||||
lbc->lcrr = CFG_LBC_LCRR & 0x7fffffff; |
||||
udelay(200); |
||||
temp_lbcdll = gur->lbcdllcr; |
||||
gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000; |
||||
asm("sync;isync;msync"); |
||||
} |
||||
lbc->or2 = CFG_OR2_PRELIM; /* 64MB SDRAM */ |
||||
lbc->br2 = CFG_BR2_PRELIM; |
||||
lbc->lbcr = CFG_LBC_LBCR; |
||||
lbc->lsdmr = CFG_LBC_LSDMR_1; |
||||
asm("sync"); |
||||
* (ulong *)0 = 0x000000ff; |
||||
lbc->lsdmr = CFG_LBC_LSDMR_2; |
||||
asm("sync"); |
||||
* (ulong *)0 = 0x000000ff; |
||||
lbc->lsdmr = CFG_LBC_LSDMR_3; |
||||
asm("sync"); |
||||
* (ulong *)0 = 0x000000ff; |
||||
lbc->lsdmr = CFG_LBC_LSDMR_4; |
||||
asm("sync"); |
||||
* (ulong *)0 = 0x000000ff; |
||||
lbc->lsdmr = CFG_LBC_LSDMR_5; |
||||
asm("sync"); |
||||
lbc->lsrt = CFG_LBC_LSRT; |
||||
asm("sync"); |
||||
lbc->mrtpr = CFG_LBC_MRTPR; |
||||
asm("sync"); |
||||
#endif |
||||
|
||||
#if defined(CONFIG_DDR_ECC) |
||||
{ |
||||
/* Initialize all of memory for ECC, then
|
||||
* enable errors */ |
||||
uint *p = 0; |
||||
uint i = 0; |
||||
volatile immap_t *immap = (immap_t *)CFG_IMMR; |
||||
volatile ccsr_ddr_t *ddr= &immap->im_ddr; |
||||
dma_init(); |
||||
for (*p = 0; p < (uint *)(8 * 1024); p++) { |
||||
if (((unsigned int)p & 0x1f) == 0) { dcbz(p); } |
||||
*p = (unsigned int)0xdeadbeef; |
||||
if (((unsigned int)p & 0x1c) == 0x1c) { dcbf(p); } |
||||
} |
||||
|
||||
/* 8K */ |
||||
dma_xfer((uint *)0x2000,0x2000,(uint *)0); |
||||
/* 16K */ |
||||
dma_xfer((uint *)0x4000,0x4000,(uint *)0); |
||||
/* 32K */ |
||||
dma_xfer((uint *)0x8000,0x8000,(uint *)0); |
||||
/* 64K */ |
||||
dma_xfer((uint *)0x10000,0x10000,(uint *)0); |
||||
/* 128k */ |
||||
dma_xfer((uint *)0x20000,0x20000,(uint *)0); |
||||
/* 256k */ |
||||
dma_xfer((uint *)0x40000,0x40000,(uint *)0); |
||||
/* 512k */ |
||||
dma_xfer((uint *)0x80000,0x80000,(uint *)0); |
||||
/* 1M */ |
||||
dma_xfer((uint *)0x100000,0x100000,(uint *)0); |
||||
/* 2M */ |
||||
dma_xfer((uint *)0x200000,0x200000,(uint *)0); |
||||
/* 4M */ |
||||
dma_xfer((uint *)0x400000,0x400000,(uint *)0); |
||||
|
||||
for (i = 1; i < dram_size / 0x800000; i++) { |
||||
dma_xfer((uint *)(0x800000*i),0x800000,(uint *)0); |
||||
} |
||||
|
||||
/* Enable errors for ECC */ |
||||
ddr->err_disable = 0x00000000; |
||||
asm("sync;isync;msync"); |
||||
} |
||||
#endif |
||||
|
||||
return dram_size; |
||||
} |
||||
|
||||
|
||||
#if defined(CFG_DRAM_TEST) |
||||
int testdram (void) |
||||
{ |
||||
uint *pstart = (uint *) CFG_MEMTEST_START; |
||||
uint *pend = (uint *) CFG_MEMTEST_END; |
||||
uint *p; |
||||
|
||||
printf("SDRAM test phase 1:\n"); |
||||
for (p = pstart; p < pend; p++) |
||||
*p = 0xaaaaaaaa; |
||||
|
||||
for (p = pstart; p < pend; p++) { |
||||
if (*p != 0xaaaaaaaa) { |
||||
printf ("SDRAM test fails at: %08x\n", (uint) p); |
||||
return 1; |
||||
} |
||||
} |
||||
|
||||
printf("SDRAM test phase 2:\n"); |
||||
for (p = pstart; p < pend; p++) |
||||
*p = 0x55555555; |
||||
|
||||
for (p = pstart; p < pend; p++) { |
||||
if (*p != 0x55555555) { |
||||
printf ("SDRAM test fails at: %08x\n", (uint) p); |
||||
return 1; |
||||
} |
||||
} |
||||
|
||||
printf("SDRAM test passed.\n"); |
||||
return 0; |
||||
} |
||||
#endif |
||||
|
||||
|
||||
#if !defined(CONFIG_SPD_EEPROM) |
||||
/*************************************************************************
|
||||
* fixed sdram init -- doesn't use serial presence detect. |
||||
************************************************************************/ |
||||
long int fixed_sdram (void) |
||||
{ |
||||
#ifndef CFG_RAMBOOT |
||||
volatile immap_t *immap = (immap_t *)CFG_IMMR; |
||||
volatile ccsr_ddr_t *ddr= &immap->im_ddr; |
||||
|
||||
ddr->cs0_bnds = CFG_DDR_CS0_BNDS; |
||||
ddr->cs0_config = CFG_DDR_CS0_CONFIG; |
||||
ddr->timing_cfg_1 = CFG_DDR_TIMING_1; |
||||
ddr->timing_cfg_2 = CFG_DDR_TIMING_2; |
||||
ddr->sdram_mode = CFG_DDR_MODE; |
||||
ddr->sdram_interval = CFG_DDR_INTERVAL; |
||||
#if defined (CONFIG_DDR_ECC) |
||||
ddr->err_disable = 0x0000000D; |
||||
ddr->err_sbe = 0x00ff0000; |
||||
#endif |
||||
asm("sync;isync;msync"); |
||||
udelay(500); |
||||
#if defined (CONFIG_DDR_ECC) |
||||
/* Enable ECC checking */ |
||||
ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000); |
||||
#else |
||||
ddr->sdram_cfg = CFG_DDR_CONTROL; |
||||
#endif |
||||
asm("sync; isync; msync"); |
||||
udelay(500); |
||||
#endif |
||||
return (CFG_SDRAM_SIZE * 1024 * 1024); |
||||
} |
||||
#endif /* !defined(CONFIG_SPD_EEPROM) */ |
@ -0,0 +1,152 @@ |
||||
/* |
||||
* (C) Copyright 2002,2003, Motorola,Inc. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/* Assumes that the size of u-boot is less than 512K and the |
||||
* start address is aligned on a 512K block. |
||||
* Boot page and reset vector is put at that end of the 512K block. */ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); |
||||
/* Do we need any of these for elf? |
||||
__DYNAMIC = 0; */ |
||||
SECTIONS |
||||
{ |
||||
/* Read-only sections, merged into text segment: */ |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
cpu/mpc85xx/start.o (.text) |
||||
board/mpc8540eval/init.o (.text) |
||||
cpu/mpc85xx/traps.o (.text) |
||||
cpu/mpc85xx/interrupts.o (.text) |
||||
cpu/mpc85xx/cpu_init.o (.text) |
||||
cpu/mpc85xx/cpu.o (.text) |
||||
cpu/mpc85xx/speed.o (.text) |
||||
cpu/mpc85xx/pci.o (.text) |
||||
common/dlmalloc.o (.text) |
||||
lib_generic/crc32.o (.text) |
||||
lib_ppc/extable.o (.text) |
||||
lib_generic/zlib.o (.text) |
||||
*(.text) |
||||
*(.fixup) |
||||
*(.got1) |
||||
} |
||||
_etext = .; |
||||
PROVIDE (etext = .); |
||||
.rodata : |
||||
{ |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
*(.rodata.str1.4) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x00FF) & 0xFFFFFF00; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_) >> 2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(256); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(256); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
} |
||||
_end = . ; |
||||
PROVIDE (end = .); |
||||
|
||||
. = (. & 0xFFF80000) + 0x0007F000; |
||||
.bootpg : |
||||
{ |
||||
cpu/mpc85xx/start.o (.bootpg) |
||||
board/mpc8540eval/init.o (.bootpg) |
||||
} = 0xffff |
||||
|
||||
. = (. & 0xFFF80000) + 0x0007FFFC; |
||||
.resetvec : |
||||
{ |
||||
*(.resetvec) |
||||
} = 0xffff |
||||
|
||||
} |
@ -0,0 +1,342 @@ |
||||
/*
|
||||
* (C) Copyright 2002,2003 Motorola,Inc. |
||||
* Modified by Lunsheng Wang, lunsheng@sohu.com |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/* mpc8540eval board configuration file */ |
||||
/* please refer to doc/README.mpc85xxads for more info */ |
||||
/* make sure you change the MAC address and other network params first,
|
||||
* search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
/* High Level Configuration Options */ |
||||
#define CONFIG_BOOKE 1 /* BOOKE */ |
||||
#define CONFIG_E500 1 /* BOOKE e500 family */ |
||||
#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ |
||||
#define CONFIG_MPC8540 1 /* MPC8540 specific */ |
||||
#define CONFIG_MPC8540EVAL 1 /* MPC8540EVAL board specific */ |
||||
|
||||
#undef CONFIG_PCI /* pci ethernet support */ |
||||
#define CONFIG_TSEC_ENET /* tsec ethernet support */ |
||||
#define CONFIG_ENV_OVERWRITE |
||||
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ |
||||
#undef CONFIG_DDR_ECC /* only for ECC DDR module */ |
||||
#define CONFIG_DDR_DLL /* possible DLL fix needed */ |
||||
|
||||
/* Using Localbus SDRAM to emulate flash before we can program the flash,
|
||||
* normally you only need a flash-boot image(u-boot.bin),if unsure undef this. |
||||
* Not availabe for EVAL board |
||||
*/ |
||||
#undef CONFIG_RAM_AS_FLASH |
||||
|
||||
/* sysclk for MPC8540EVAL */ |
||||
#if defined(CONFIG_SYSCLK_66M) |
||||
#define CONFIG_SYS_CLK_FREQ 66000000 /* the oscillator on board is 66Mhz */ |
||||
/* can also get 66M clock from external PCI */ |
||||
#else |
||||
#define CONFIG_SYS_CLK_FREQ 33000000 /* most pci cards are 33Mhz */ |
||||
#endif |
||||
|
||||
/* below can be toggled for performance analysis. otherwise use default */ |
||||
#define CONFIG_L2_CACHE /* toggle L2 cache */ |
||||
#undef CONFIG_BTB /* toggle branch predition */ |
||||
#undef CONFIG_ADDR_STREAMING /* toggle addr streaming */ |
||||
|
||||
#define CONFIG_BOARD_PRE_INIT 1 /* Call board_pre_init */ |
||||
|
||||
#undef CFG_DRAM_TEST /* memory test, takes time */ |
||||
#define CFG_MEMTEST_START 0x00200000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x00400000 |
||||
|
||||
#if defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) |
||||
#error "You can only use either PCI Ethernet Card or TSEC Ethernet, not both." |
||||
#endif |
||||
|
||||
/*
|
||||
* Base addresses -- Note these are effective addresses where the |
||||
* actual resources get mapped (not physical addresses) |
||||
*/ |
||||
#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ |
||||
#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ |
||||
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ |
||||
|
||||
#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ |
||||
#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE |
||||
#define CFG_SDRAM_SIZE 256 /* DDR is now 256MB */ |
||||
|
||||
#if defined(CONFIG_RAM_AS_FLASH) |
||||
#define CFG_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */ |
||||
#else |
||||
#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ |
||||
#endif |
||||
#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 0MB */ |
||||
|
||||
#if defined(CONFIG_RAM_AS_FLASH) |
||||
#define CFG_FLASH_BASE 0xf8000000 /* start of FLASH 16M */ |
||||
#define CFG_BR0_PRELIM 0xf8001801 /* port size 32bit */ |
||||
#else /* Boot from real Flash */ |
||||
#define CFG_FLASH_BASE 0xff800000 /* start of FLASH 8M */ |
||||
#define CFG_BR0_PRELIM 0xff801001 /* port size 16bit */ |
||||
#endif |
||||
|
||||
#define CFG_OR0_PRELIM 0xff806f67 /* 8MB Flash */ |
||||
#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ |
||||
#define CFG_MAX_FLASH_SECT 64 /* sectors per device */ |
||||
#undef CFG_FLASH_CHECKSUM |
||||
#define CFG_FLASH_ERASE_TOUT 60000 /* Timeout for Flash Erase (in ms)*/ |
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms)*/ |
||||
#define CFG_FLASH_CFI 1 |
||||
|
||||
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ |
||||
|
||||
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) |
||||
#define CFG_RAMBOOT |
||||
#else |
||||
#undef CFG_RAMBOOT |
||||
#endif |
||||
|
||||
#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ |
||||
|
||||
/* Here some DDR setting should be added */ |
||||
|
||||
|
||||
#undef CONFIG_CLOCKS_IN_MHZ |
||||
|
||||
/* local bus definitions */ |
||||
#define CFG_BR2_PRELIM 0xf0001861 /* 64MB localbus SDRAM */ |
||||
#define CFG_OR2_PRELIM 0xfc006901 |
||||
#define CFG_LBC_LCRR 0x00030004 /* local bus freq divider*/ |
||||
#define CFG_LBC_LBCR 0x00000000 |
||||
#define CFG_LBC_LSRT 0x20000000 |
||||
#define CFG_LBC_MRTPR 0x20000000 |
||||
#define CFG_LBC_LSDMR_1 0x2861b723 |
||||
#define CFG_LBC_LSDMR_2 0x0861b723 |
||||
#define CFG_LBC_LSDMR_3 0x0861b723 |
||||
#define CFG_LBC_LSDMR_4 0x1861b723 |
||||
#define CFG_LBC_LSDMR_5 0x4061b723 |
||||
|
||||
#if defined(CONFIG_RAM_AS_FLASH) |
||||
#define CFG_BR4_PRELIM 0xf8000801 /* 32KB, 8-bit wide for ADS config reg */ |
||||
#else |
||||
#define CFG_BR4_PRELIM 0xf8000801 /* 32KB, 8-bit wide for ADS config reg */ |
||||
#endif |
||||
#define CFG_OR4_PRELIM 0xffffe1f1 |
||||
#define CFG_BCSR (CFG_BR4_PRELIM & 0xffff8000) |
||||
|
||||
#define CONFIG_L1_INIT_RAM |
||||
#define CFG_INIT_RAM_LOCK 1 |
||||
#define CFG_INIT_RAM_ADDR 0x40000000 /* Initial RAM address */ |
||||
#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ |
||||
|
||||
#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
||||
#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ |
||||
|
||||
/* Serial Port */ |
||||
#define CONFIG_CONS_INDEX 1 |
||||
#undef CONFIG_SERIAL_SOFTWARE_FIFO |
||||
#define CFG_NS16550 |
||||
#define CFG_NS16550_SERIAL |
||||
#define CFG_NS16550_REG_SIZE 1 |
||||
#define CFG_NS16550_CLK get_bus_freq(0) |
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
#define CFG_BAUDRATE_TABLE \ |
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
||||
|
||||
#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) |
||||
#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) |
||||
|
||||
/* Use the HUSH parser */ |
||||
#define CFG_HUSH_PARSER |
||||
#ifdef CFG_HUSH_PARSER |
||||
#define CFG_PROMPT_HUSH_PS2 "> " |
||||
#endif |
||||
|
||||
/* I2C */ |
||||
#define CONFIG_HARD_I2C /* I2C with hardware support*/ |
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ |
||||
#define CFG_I2C_SLAVE 0x7F |
||||
#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ |
||||
|
||||
/* General PCI */ |
||||
#define CFG_PCI_MEM_BASE 0x80000000 |
||||
#define CFG_PCI_MEM_PHYS 0x80000000 |
||||
#define CFG_PCI_MEM_SIZE 0x20000000 |
||||
#define CFG_PCI_IO_BASE 0xe2000000 |
||||
|
||||
#if defined(CONFIG_PCI) |
||||
#define CONFIG_NET_MULTI |
||||
#undef CONFIG_EEPRO100 |
||||
#define CONFIG_TULIP |
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */ |
||||
#if !defined(CONFIG_PCI_PNP) |
||||
#define PCI_ENET0_IOADDR 0xe0000000 |
||||
#define PCI_ENET0_MEMADDR 0xe0000000 |
||||
#define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/ |
||||
#endif |
||||
#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ |
||||
#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ |
||||
#define CFG_PCI_SUBSYS_DEVICEID 0x0008 |
||||
#elif defined(CONFIG_TSEC_ENET) |
||||
#define CONFIG_NET_MULTI 1 |
||||
#define CONFIG_MII 1 /* MII PHY management */ |
||||
#define CONFIG_MPC85XX_TSEC1 1 |
||||
#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" |
||||
#define CONFIG_MPC85XX_TSEC2 1 |
||||
#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" |
||||
#define CONFIG_MPC85XX_FEC 1 |
||||
#define CONFIG_MPC85XX_FEC_NAME "FEC" |
||||
#define TSEC1_PHY_ADDR 7 |
||||
#define TSEC2_PHY_ADDR 4 |
||||
#define FEC_PHY_ADDR 2 |
||||
#define TSEC1_PHYIDX 0 |
||||
#define TSEC2_PHYIDX 0 |
||||
#define FEC_PHYIDX 0 |
||||
/* Options are: TSEC[0-1], FEC */ |
||||
#define CONFIG_ETHPRIME "TSEC0" |
||||
|
||||
#define CONFIG_PHY_M88E1011 1 /* GigaBit Ether PHY */ |
||||
#define INTEL_LXT971_PHY 1 /* on EVAL board. It is Davicom 9161 on ADS. */ |
||||
#endif |
||||
|
||||
#undef DEBUG |
||||
|
||||
/* Environment */ |
||||
#ifndef CFG_RAMBOOT |
||||
#if defined(CONFIG_RAM_AS_FLASH) |
||||
#define CFG_ENV_IS_NOWHERE |
||||
#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x100000) |
||||
#define CFG_ENV_SIZE 0x2000 |
||||
#else |
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) |
||||
#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ |
||||
#endif |
||||
#define CFG_ENV_SIZE 0x2000 |
||||
#else |
||||
/* #define CFG_NO_FLASH 1 */ /* Flash is not usable now */ |
||||
#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) |
||||
#define CFG_ENV_SIZE 0x2000 |
||||
#endif |
||||
|
||||
/*#define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=192.168.1.10:/tftproot/192.168.1.11 ip=192.168.1.11:192.168.1.10:192.168.1.0:255.255.255.0:mpc8540ads-003:eth0:off console=ttyS0,115200"*/ |
||||
#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200" |
||||
#define CONFIG_BOOTCOMMAND "bootm 0xff800000 0xffa00000" |
||||
#define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */ |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
||||
|
||||
#if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH) |
||||
#if defined(CONFIG_PCI) |
||||
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING | CFG_CMD_PCI | CFG_CMD_I2C ) & \ |
||||
~(CFG_CMD_ENV | CFG_CMD_LOADS )) |
||||
#else |
||||
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING | CFG_CMD_I2C ) & \ |
||||
~(CFG_CMD_ENV | \
|
||||
CFG_CMD_LOADS )) |
||||
#endif |
||||
#else |
||||
#if defined(CONFIG_PCI) |
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_PING | CFG_CMD_I2C ) |
||||
#else |
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING | CFG_CMD_I2C ) |
||||
#endif |
||||
#endif |
||||
#include <cmd_confdefs.h> |
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_LOAD_ADDR 0x2000000 /* default load address */ |
||||
#define CFG_PROMPT "MPC8540EVAL=> "/* Monitor Command Prompt */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
/* Cache Configuration */ |
||||
#define CFG_DCACHE_SIZE 32768 |
||||
#define CFG_CACHELINE_SIZE 32 |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
||||
#endif |
||||
|
||||
/*****************************/ |
||||
/* Environment Configuration */ |
||||
/*****************************/ |
||||
/* The mac addresses for all ethernet interface */ |
||||
/* NOTE: change below for your network setting!!! */ |
||||
#if defined(CONFIG_TSEC_ENET) |
||||
#define CONFIG_ETHADDR 00:01:af:07:9b:8a |
||||
#define CONFIG_ETH1ADDR 00:01:af:07:9b:8b |
||||
#define CONFIG_ETH2ADDR 00:01:af:07:9b:8c |
||||
#endif |
||||
|
||||
#define CONFIG_ROOTPATH /nfsroot |
||||
#define CONFIG_BOOTFILE your.uImage |
||||
|
||||
#define CONFIG_SERVERIP 192.168.101.1 |
||||
#define CONFIG_IPADDR 192.168.101.11 |
||||
#define CONFIG_GATEWAYIP 192.168.101.0 |
||||
#define CONFIG_NETMASK 255.255.255.0 |
||||
|
||||
#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ |
||||
|
||||
#define CONFIG_HOSTNAME MPC8540EVAL |
||||
|
||||
#endif /* __CONFIG_H */ |
Loading…
Reference in new issue