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@ -1,6 +1,6 @@ |
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/*
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* SuperH SCIF device driver. |
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* Copyright (c) 2007 Nobuhiro Iwamatsu |
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* Copyright (c) 2007,2008 Nobuhiro Iwamatsu |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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@ -36,7 +36,7 @@ |
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#define SCSCR (vu_short *)(SCIF_BASE + 0x8) |
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#define SCFCR (vu_short *)(SCIF_BASE + 0x18) |
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#define SCFDR (vu_short *)(SCIF_BASE + 0x1C) |
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#ifdef CONFIG_SH7720 /* SH7720 specific */ |
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#ifdef CONFIG_CPU_SH7720 /* SH7720 specific */ |
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#define SCFSR (vu_short *)(SCIF_BASE + 0x14) /* SCSSR */ |
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#define SCFTDR (vu_char *)(SCIF_BASE + 0x20) |
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#define SCFRDR (vu_char *)(SCIF_BASE + 0x24) |
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@ -57,12 +57,19 @@ |
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#define SCLSR (vu_short *)(SCIF_BASE + 0x24) |
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#define LSR_ORER 1 |
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#elif defined (CONFIG_SH3) |
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#ifdef CONFIG_SH7720 /* SH7720 specific */ |
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# define SCLSR SCFSR /* SCSSR */ |
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#ifdef CONFIG_CPU_SH7720 /* SH7720 specific */ |
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#define SCLSR (vu_short *)(SCIF_BASE + 0x24) |
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#define LSR_ORER 0x0200 |
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#else |
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# define SCLSR (vu_short *)(SCIF_BASE + 0x24) |
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#define SCLSR SCFSR /* SCSSR */ |
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#define LSR_ORER 1 |
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#endif |
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#define LSR_ORER 0x0200 |
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#endif |
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#if defined(CONFIG_CPU_SH7720) |
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#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1) |
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#else /* Generic SuperH */ |
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#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) |
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#endif |
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#define SCR_RE (1 << 4) |
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@ -82,18 +89,7 @@ |
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void serial_setbrg (void) |
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{ |
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DECLARE_GLOBAL_DATA_PTR; |
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#if defined(CONFIG_CPU_SH7720) |
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int divisor = gd->baudrate * 16; |
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*SCBRR = (CONFIG_SYS_CLK_FREQ * 2 + (divisor / 2)) / |
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(gd->baudrate * 32) - 1; |
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#else |
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int divisor = gd->baudrate * 32; |
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*SCBRR = (CONFIG_SYS_CLK_FREQ + (divisor / 2)) / |
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(gd->baudrate * 32) - 1; |
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#endif |
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*SCBRR = SCBRR_VALUE(gd->baudrate,CONFIG_SYS_CLK_FREQ); |
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} |
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int serial_init (void) |
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