This patch adds SPL support to the Marvell Armada-XP. With this addition the bin_hdr integration is not needed any more. The SPL will first initialize the serdes/PHY and the call the DDR setup and training code now integrated into mainline U-Boot. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>master
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/* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <config.h> |
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#include <version.h> |
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#include <linux/linkage.h> |
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ENTRY(save_boot_params) |
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bx lr |
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ENDPROC(save_boot_params) |
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/* |
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* cache_inv - invalidate Cache line |
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* r0 - dest |
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*/ |
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.global cache_inv
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.type cache_inv, %function |
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cache_inv: |
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stmfd sp!, {r1-r12} |
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mcr p15, 0, r0, c7, c6, 1 |
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ldmfd sp!, {r1-r12} |
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bx lr |
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/* |
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* flush_l1_v6 - l1 cache clean invalidate |
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* r0 - dest |
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*/ |
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.global flush_l1_v6
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.type flush_l1_v6, %function |
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flush_l1_v6: |
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stmfd sp!, {r1-r12} |
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mcr p15, 0, r0, c7, c10, 5 /* @ data memory barrier */
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mcr p15, 0, r0, c7, c14, 1 /* @ clean & invalidate D line */
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mcr p15, 0, r0, c7, c10, 4 /* @ data sync barrier */
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ldmfd sp!, {r1-r12} |
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bx lr |
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/* |
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* flush_l1_v7 - l1 cache clean invalidate |
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* r0 - dest |
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*/ |
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.global flush_l1_v7
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.type flush_l1_v7, %function |
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flush_l1_v7: |
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stmfd sp!, {r1-r12} |
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dmb /* @data memory barrier */
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mcr p15, 0, r0, c7, c14, 1 /* @ clean & invalidate D line */
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dsb /* @data sync barrier */
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ldmfd sp!, {r1-r12} |
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bx lr |
@ -0,0 +1,38 @@ |
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/*
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* Copyright (C) 2014 Stefan Roese <sr@denx.de> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <spl.h> |
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#include <asm/io.h> |
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#include <asm/arch/cpu.h> |
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#include <asm/arch/soc.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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u32 spl_boot_device(void) |
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{ |
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/* Right now only booting via SPI NOR flash is supported */ |
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return BOOT_DEVICE_SPI; |
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} |
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void board_init_f(ulong dummy) |
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{ |
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/* Set global data pointer */ |
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gd = &gdata; |
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/* Linux expects the internal registers to be at 0xf1000000 */ |
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arch_cpu_init(); |
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preloader_console_init(); |
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/* First init the serdes PHY's */ |
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serdes_phy_config(); |
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/* Setup DDR */ |
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ddr3_init(); |
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board_init_r(NULL, 0); |
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} |
@ -0,0 +1,57 @@ |
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/* |
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* (C) Copyright 2002 |
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* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> |
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* |
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* (C) Copyright 2010 |
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* Texas Instruments, <www.ti.com> |
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* Aneesh V <aneesh@ti.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\ |
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LENGTH = CONFIG_SPL_MAX_SIZE } |
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MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \ |
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LENGTH = CONFIG_SPL_BSS_MAX_SIZE } |
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OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") |
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OUTPUT_ARCH(arm) |
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ENTRY(_start) |
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SECTIONS |
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{ |
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.text : |
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{ |
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__start = .; |
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arch/arm/cpu/armv7/start.o (.text*) |
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*(.text*) |
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*(.vectors) |
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} >.sram |
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. = ALIGN(4); |
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.rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram |
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. = ALIGN(4); |
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.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram |
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. = ALIGN(4); |
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.u_boot_list : { |
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KEEP(*(SORT(.u_boot_list*_i2c_*))); |
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} >.sram |
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. = ALIGN(4); |
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__image_copy_end = .; |
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.end : |
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{ |
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*(.__end) |
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} |
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.bss : |
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{ |
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. = ALIGN(4); |
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__bss_start = .; |
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*(.bss*) |
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. = ALIGN(4); |
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__bss_end = .; |
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} >.sdram |
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} |
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