This patch adds support for the Armada XP (MV78260) based theadorable board. Its equipped with onboard DDR3, UART, ethernet, I2C, SPI NOR, LCD and SATA (SSD) interfaces / devices. Two defconfigs are added: theadorable_defconfig: The production U-Boot version with a stripped down drivers and feature list. This removes networking, USB and PCI support. theadorable_debug_defconfig: The debugging / testing U-Boot version with full support for all drivers. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Signed-off-by: Stefan Roese <sr@denx.de>master
Stefan Roese
9 years ago
parent
9e4de7fd4a
commit
b20c38a973
@ -0,0 +1,143 @@ |
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/* |
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* Device Tree file for Marvell Armada XP theadorable board |
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* |
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* Copyright (C) 2013-2014 Marvell |
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* |
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* Lior Amsalem <alior@marvell.com> |
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* Gregory CLEMENT <gregory.clement@free-electrons.com> |
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com> |
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* |
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* This file is dual-licensed: you can use it either under the terms |
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* of the GPL or the X11 license, at your option. Note that this dual |
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* licensing only applies to this file, and not this project as a |
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* whole. |
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* |
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* a) This file is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of the |
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* License, or (at your option) any later version. |
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* |
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* This file is distributed in the hope that it will be useful |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* Or, alternatively |
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* |
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* b) Permission is hereby granted, free of charge, to any person |
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* obtaining a copy of this software and associated documentation |
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* files (the "Software"), to deal in the Software without |
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* restriction, including without limitation the rights to use |
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* copy, modify, merge, publish, distribute, sublicense, and/or |
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* sell copies of the Software, and to permit persons to whom the |
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* Software is furnished to do so, subject to the following |
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* conditions: |
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* |
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* The above copyright notice and this permission notice shall be |
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* included in all copies or substantial portions of the Software. |
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* |
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* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND |
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES |
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT |
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY |
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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* OTHER DEALINGS IN THE SOFTWARE. |
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* |
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* Note: this Device Tree assumes that the bootloader has remapped the |
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* internal registers to 0xf1000000 (instead of the default |
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* 0xd0000000). The 0xf1000000 is the default used by the recent, |
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* DT-capable, U-Boot bootloaders provided by Marvell. Some earlier |
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* boards were delivered with an older version of the bootloader that |
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* left internal registers mapped at 0xd0000000. If you are in this |
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* situation, you should either update your bootloader (preferred |
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* solution) or the below Device Tree should be adjusted. |
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*/ |
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|
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/dts-v1/; |
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#include <dt-bindings/gpio/gpio.h> |
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#include "armada-xp-mv78260.dtsi" |
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|
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/ { |
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model = "Marvell Armada XP theadorable"; |
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compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp"; |
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|
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chosen { |
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stdout-path = "serial0:115200n8"; |
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}; |
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|
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aliases { |
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spi0 = &spi0; |
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ethernet0 = ð0; |
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}; |
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|
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memory { |
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device_type = "memory"; |
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reg = <0x00000000 0x00000000 0x00000000 0x80000000>; |
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}; |
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|
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soc { |
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ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000 |
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MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000 |
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MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>; |
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|
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internal-regs { |
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serial@12000 { |
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status = "okay"; |
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u-boot,dm-pre-reloc; |
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}; |
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|
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serial@12100 { |
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status = "okay"; |
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}; |
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|
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serial@12200 { |
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status = "okay"; |
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}; |
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|
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serial@12300 { |
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status = "okay"; |
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}; |
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|
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sata@a0000 { |
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nr-ports = <2>; |
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status = "okay"; |
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}; |
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|
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mdio { |
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phy0: ethernet-phy@0 { |
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reg = <0>; |
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}; |
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}; |
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|
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ethernet@70000 { |
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status = "okay"; |
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phy = <&phy0>; |
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phy-mode = "sgmii"; |
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}; |
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|
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usb@50000 { |
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status = "okay"; |
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}; |
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|
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usb@51000 { |
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status = "okay"; |
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}; |
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|
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spi0: spi@10600 { |
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status = "okay"; |
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u-boot,dm-pre-reloc; |
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|
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spi-flash@0 { |
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u-boot,dm-pre-reloc; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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compatible = "n25q128a13", "jedec,spi-nor"; |
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reg = <0>; /* Chip select 0 */ |
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spi-max-frequency = <27777777>; |
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}; |
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}; |
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}; |
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}; |
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}; |
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@ -0,0 +1,7 @@ |
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THEADORABLE BOARD |
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M: Stefan Roese <sr@denx.de> |
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S: Maintained |
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F: board/theadorable/ |
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F: include/configs/theadorable.h |
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F: configs/theadorable_debug_defconfig |
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F: configs/theadorable_defconfig |
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@ -0,0 +1,7 @@ |
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#
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# Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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|
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obj-y := theadorable.o
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@ -0,0 +1,12 @@ |
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# |
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# Copyright (C) 2015-2016 Stefan Roese <sr@denx.de> |
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# |
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|
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# Armada XP uses version 1 image format |
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VERSION 1 |
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# Boot Media configurations |
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BOOT_FROM spi |
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# Binary Header (bin_hdr) with DDR3 training code |
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BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068 |
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@ -0,0 +1,171 @@ |
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/*
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* Copyright (C) 2015-2016 Stefan Roese <sr@denx.de> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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#include <common.h> |
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#include <asm/io.h> |
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#include <asm/arch/cpu.h> |
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#include <asm/arch/soc.h> |
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#ifdef CONFIG_NET |
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#include <netdev.h> |
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#endif |
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|
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#include "../drivers/ddr/marvell/axp/ddr3_hw_training.h" |
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#include "../arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h" |
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DECLARE_GLOBAL_DATA_PTR; |
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#define THEADORABLE_GPP_OUT_ENA_LOW 0x00336780 |
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#define THEADORABLE_GPP_OUT_ENA_MID 0x00003cf0 |
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#define THEADORABLE_GPP_OUT_ENA_HIGH (~(0x0)) |
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#define THEADORABLE_GPP_OUT_VAL_LOW 0x2c0c983f |
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#define THEADORABLE_GPP_OUT_VAL_MID 0x0007000c |
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#define THEADORABLE_GPP_OUT_VAL_HIGH 0x00000000 |
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|
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/* DDR3 static configuration */ |
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static MV_DRAM_MC_INIT ddr3_theadorable[MV_MAX_DDR3_STATIC_SIZE] = { |
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{0x00001400, 0x7301ca28}, /* DDR SDRAM Configuration Register */ |
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{0x00001404, 0x30000800}, /* Dunit Control Low Register */ |
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{0x00001408, 0x44149887}, /* DDR SDRAM Timing (Low) Register */ |
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{0x0000140C, 0x38d93fc7}, /* DDR SDRAM Timing (High) Register */ |
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{0x00001410, 0x1b100001}, /* DDR SDRAM Address Control Register */ |
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{0x00001424, 0x0000f3ff}, /* Dunit Control High Register */ |
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{0x00001428, 0x000f8830}, /* ODT Timing (Low) Register */ |
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{0x0000142C, 0x014c50f4}, /* DDR3 Timing Register */ |
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{0x0000147C, 0x0000c671}, /* ODT Timing (High) Register */ |
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|
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{0x00001494, 0x00010000}, /* DDR SDRAM ODT Control (Low) Reg */ |
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{0x0000149C, 0x00000001}, /* DDR Dunit ODT Control Register */ |
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{0x000014A0, 0x00000001}, /* DRAM FIFO Control Register */ |
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{0x000014A8, 0x00000101}, /* AXI Control Register */ |
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|
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/*
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* DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the |
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* training sequence |
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*/ |
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{0x000200e8, 0x3fff0e01}, |
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{0x00020184, 0x3fffffe0}, /* Close fast path Window to - 2G */ |
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{0x0001504, 0x7fffffe1}, /* CS0 Size */ |
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{0x000150C, 0x00000000}, /* CS1 Size */ |
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{0x0001514, 0x00000000}, /* CS2 Size */ |
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{0x000151C, 0x00000000}, /* CS3 Size */ |
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{0x00020220, 0x00000007}, /* Reserved */ |
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{0x00001538, 0x00000009}, /* Read Data Sample Delays Register */ |
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{0x0000153C, 0x00000009}, /* Read Data Ready Delay Register */ |
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{0x000015D0, 0x00000650}, /* MR0 */ |
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{0x000015D4, 0x00000044}, /* MR1 */ |
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{0x000015D8, 0x00000010}, /* MR2 */ |
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{0x000015DC, 0x00000000}, /* MR3 */ |
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{0x000015E0, 0x00000001}, |
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{0x000015E4, 0x00203c18}, /* ZQDS Configuration Register */ |
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{0x000015EC, 0xf800a225}, /* DDR PHY */ |
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/* Recommended Settings from Marvell for 4 x 16 bit devices: */ |
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{0x000014C0, 0x192424c9}, /* DRAM addr and Ctrl Driving Strenght*/ |
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{0x000014C4, 0x0aaa24c9}, /* DRAM Data and DQS Driving Strenght */ |
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{0x0, 0x0} |
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}; |
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static MV_DRAM_MODES board_ddr_modes[MV_DDR3_MODES_NUMBER] = { |
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{"theadorable_1333-667", 0x3, 0x5, 0x0, A0, ddr3_theadorable, NULL}, |
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}; |
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extern MV_SERDES_CHANGE_M_PHY serdes_change_m_phy[]; |
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/*
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* Lane0 - PCIE0.0 X1 (to WIFI Module) |
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* Lane5 - SATA0 |
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* Lane6 - SATA1 |
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* Lane7 - SGMII0 (to Ethernet Phy) |
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* Lane8-11 - PCIE2.0 X4 (to PEX Switch) |
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* all other lanes are disabled |
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*/ |
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MV_BIN_SERDES_CFG theadorable_serdes_cfg[] = { |
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{ MV_PEX_ROOT_COMPLEX, 0x22200001, 0x00001111, |
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{ PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, |
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PEX_BUS_DISABLED }, |
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0x0060, serdes_change_m_phy |
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}, |
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}; |
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MV_DRAM_MODES *ddr3_get_static_ddr_mode(void) |
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{ |
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/* Only one mode supported for this board */ |
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return &board_ddr_modes[0]; |
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} |
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MV_BIN_SERDES_CFG *board_serdes_cfg_get(u8 pex_mode) |
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{ |
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return &theadorable_serdes_cfg[0]; |
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} |
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int board_early_init_f(void) |
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{ |
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/* Configure MPP */ |
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writel(0x00000000, MVEBU_MPP_BASE + 0x00); |
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writel(0x03300000, MVEBU_MPP_BASE + 0x04); |
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writel(0x00000033, MVEBU_MPP_BASE + 0x08); |
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writel(0x00000000, MVEBU_MPP_BASE + 0x0c); |
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writel(0x11110000, MVEBU_MPP_BASE + 0x10); |
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writel(0x00221100, MVEBU_MPP_BASE + 0x14); |
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writel(0x00000000, MVEBU_MPP_BASE + 0x18); |
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writel(0x00000000, MVEBU_MPP_BASE + 0x1c); |
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writel(0x00000000, MVEBU_MPP_BASE + 0x20); |
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/* Configure GPIO */ |
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writel(THEADORABLE_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00); |
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writel(THEADORABLE_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04); |
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writel(THEADORABLE_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00); |
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writel(THEADORABLE_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04); |
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writel(THEADORABLE_GPP_OUT_VAL_HIGH, MVEBU_GPIO2_BASE + 0x00); |
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writel(THEADORABLE_GPP_OUT_ENA_HIGH, MVEBU_GPIO2_BASE + 0x04); |
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return 0; |
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} |
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int board_init(void) |
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{ |
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/* adress of boot parameters */ |
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gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; |
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return 0; |
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} |
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int checkboard(void) |
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{ |
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puts("Board: theadorable\n"); |
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return 0; |
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} |
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#ifdef CONFIG_NET |
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int board_eth_init(bd_t *bis) |
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{ |
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cpu_eth_init(bis); /* Built in controller(s) come first */ |
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return pci_eth_init(bis); |
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} |
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#endif |
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int board_video_init(void) |
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{ |
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struct mvebu_lcd_info lcd_info; |
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/* Reserved memory area via CONFIG_SYS_MEM_TOP_HIDE */ |
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lcd_info.fb_base = gd->ram_size; |
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lcd_info.x_res = 240; |
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lcd_info.x_fp = 1; |
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lcd_info.x_bp = 45; |
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lcd_info.y_res = 320; |
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lcd_info.y_fp = 1; |
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lcd_info.y_bp = 3; |
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return mvebu_lcd_register_init(&lcd_info); |
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} |
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@ -0,0 +1,28 @@ |
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CONFIG_ARM=y |
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CONFIG_ARCH_MVEBU=y |
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CONFIG_SYS_MALLOC_F_LEN=0x2000 |
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CONFIG_TARGET_THEADORABLE=y |
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CONFIG_DEFAULT_DEVICE_TREE="armada-xp-theadorable" |
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# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set |
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CONFIG_SPL=y |
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# CONFIG_CMD_IMLS is not set |
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# CONFIG_CMD_FLASH is not set |
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CONFIG_CMD_SF=y |
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CONFIG_CMD_USB=y |
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# CONFIG_CMD_FPGA is not set |
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# CONFIG_CMD_SETEXPR is not set |
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CONFIG_NET_RANDOM_ETHADDR=y |
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CONFIG_SPL_OF_TRANSLATE=y |
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CONFIG_SPI_FLASH=y |
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CONFIG_SPI_FLASH_MACRONIX=y |
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CONFIG_SPI_FLASH_STMICRO=y |
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CONFIG_DEBUG_UART=y |
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CONFIG_DEBUG_UART_BASE=0xd0012000 |
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CONFIG_DEBUG_UART_CLOCK=250000000 |
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CONFIG_DEBUG_UART_SHIFT=2 |
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CONFIG_SYS_NS16550=y |
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CONFIG_USB=y |
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CONFIG_DM_USB=y |
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CONFIG_USB_EHCI_HCD=y |
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CONFIG_USB_STORAGE=y |
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CONFIG_VIDEO_MVEBU=y |
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@ -0,0 +1,26 @@ |
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CONFIG_ARM=y |
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CONFIG_ARCH_MVEBU=y |
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CONFIG_SYS_MALLOC_F_LEN=0x2000 |
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CONFIG_TARGET_THEADORABLE=y |
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CONFIG_DEFAULT_DEVICE_TREE="armada-xp-theadorable" |
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# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set |
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CONFIG_SPL=y |
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# CONFIG_CMD_IMLS is not set |
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# CONFIG_CMD_FLASH is not set |
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CONFIG_CMD_SF=y |
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# CONFIG_CMD_FPGA is not set |
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# CONFIG_CMD_SETEXPR is not set |
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# CONFIG_CMD_NET is not set |
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# CONFIG_CMD_NFS is not set |
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CONFIG_SPL_OF_TRANSLATE=y |
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CONFIG_SPI_FLASH=y |
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CONFIG_SPI_FLASH_MACRONIX=y |
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CONFIG_SPI_FLASH_STMICRO=y |
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CONFIG_DEBUG_UART=y |
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CONFIG_DEBUG_UART_BASE=0xd0012000 |
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CONFIG_DEBUG_UART_CLOCK=250000000 |
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CONFIG_DEBUG_UART_SHIFT=2 |
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CONFIG_SYS_NS16550=y |
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CONFIG_VIDEO_MVEBU=y |
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CONFIG_REGEX=y |
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CONFIG_LIB_RAND=y |
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@ -0,0 +1,170 @@ |
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/*
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* Copyright (C) 2015-2016 Stefan Roese <sr@denx.de> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef _CONFIG_THEADORABLE_H |
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#define _CONFIG_THEADORABLE_H |
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/*
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* High Level Configuration Options (easy to change) |
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*/ |
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#define CONFIG_DISPLAY_BOARDINFO_LATE |
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/*
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* TEXT_BASE needs to be below 16MiB, since this area is scrubbed |
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* for DDR ECC byte filling in the SPL before loading the main |
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* U-Boot into it. |
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*/ |
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#define CONFIG_SYS_TEXT_BASE 0x00800000 |
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#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ |
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/*
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* Commands configuration |
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*/ |
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#define CONFIG_CMD_BOOTZ |
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#define CONFIG_CMD_CACHE |
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#define CONFIG_CMD_ENV |
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#define CONFIG_CMD_EXT2 |
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#define CONFIG_CMD_EXT4 |
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#define CONFIG_CMD_FAT |
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#define CONFIG_CMD_FS_GENERIC |
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#define CONFIG_CMD_I2C |
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#define CONFIG_CMD_SATA |
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#define CONFIG_CMD_TIME |
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/*
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* The debugging version enables USB support via defconfig. |
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* This version should also enable all other non-production |
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* interfaces / features. |
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*/ |
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#ifdef CONFIG_USB |
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#define CONFIG_CMD_DHCP |
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#define CONFIG_CMD_PCI |
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#define CONFIG_CMD_PING |
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#define CONFIG_CMD_SPI |
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#define CONFIG_CMD_TFTPPUT |
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#endif |
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|
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/* I2C */ |
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#define CONFIG_SYS_I2C |
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#define CONFIG_SYS_I2C_MVTWSI |
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#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE |
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#define CONFIG_SYS_I2C_SLAVE 0x0 |
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#define CONFIG_SYS_I2C_SPEED 100000 |
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/* USB/EHCI configuration */ |
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#define CONFIG_EHCI_IS_TDI |
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 |
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#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ |
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/* SPI NOR flash default params, used by sf commands */ |
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#define CONFIG_SF_DEFAULT_SPEED 27777777 /* for fast SPL booting */ |
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#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 |
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/* Environment in SPI NOR flash */ |
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#define CONFIG_ENV_IS_IN_SPI_FLASH |
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#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ |
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#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ |
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#define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */ |
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#define CONFIG_ENV_OVERWRITE |
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#define CONFIG_PHY_MARVELL /* there is a marvell phy */ |
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#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ |
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#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */ |
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#define CONFIG_SYS_ALT_MEMTEST |
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#define CONFIG_PREBOOT |
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#define CONFIG_FIT |
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#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */ |
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " |
||||
|
||||
/* Keep device tree and initrd in lower memory so the kernel can access them */ |
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"fdt_high=0x10000000\0" \
|
||||
"initrd_high=0x10000000\0" |
||||
|
||||
/* SATA support */ |
||||
#define CONFIG_SYS_SATA_MAX_DEVICE 1 |
||||
#define CONFIG_SATA_MV |
||||
#define CONFIG_LIBATA |
||||
#define CONFIG_LBA48 |
||||
#define CONFIG_EFI_PARTITION |
||||
#define CONFIG_DOS_PARTITION |
||||
|
||||
/* Additional FS support/configuration */ |
||||
#define CONFIG_SUPPORT_VFAT |
||||
|
||||
/* PCIe support */ |
||||
#ifdef CONFIG_CMD_PCI |
||||
#ifndef CONFIG_SPL_BUILD |
||||
#define CONFIG_PCI |
||||
#define CONFIG_PCI_MVEBU |
||||
#define CONFIG_PCI_PNP |
||||
#endif |
||||
#endif |
||||
|
||||
/* Enable LCD and reserve 512KB from top of memory*/ |
||||
#define CONFIG_SYS_MEM_TOP_HIDE 0x80000 |
||||
|
||||
#define CONFIG_VIDEO |
||||
#define CONFIG_CFB_CONSOLE |
||||
#define CONFIG_VGA_AS_SINGLE_DEVICE |
||||
#define CONFIG_CMD_BMP |
||||
|
||||
/*
|
||||
* mv-common.h should be defined after CMD configs since it used them |
||||
* to enable certain macros |
||||
*/ |
||||
#include "mv-common.h" |
||||
|
||||
/*
|
||||
* Memory layout while starting into the bin_hdr via the |
||||
* BootROM: |
||||
* |
||||
* 0x4000.4000 - 0x4003.4000 headers space (192KiB) |
||||
* 0x4000.4030 bin_hdr start address |
||||
* 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) |
||||
* 0x4007.fffc BootROM stack top |
||||
* |
||||
* The address space between 0x4007.fffc and 0x400f.fff is not locked in |
||||
* L2 cache thus cannot be used. |
||||
*/ |
||||
|
||||
/* SPL */ |
||||
/* Defines for SPL */ |
||||
#define CONFIG_SPL_FRAMEWORK |
||||
#define CONFIG_SPL_TEXT_BASE 0x40004030 |
||||
#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) |
||||
|
||||
#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) |
||||
#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) |
||||
|
||||
#ifdef CONFIG_SPL_BUILD |
||||
#define CONFIG_SYS_MALLOC_SIMPLE |
||||
#endif |
||||
|
||||
#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) |
||||
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) |
||||
|
||||
#define CONFIG_SPL_LIBCOMMON_SUPPORT |
||||
#define CONFIG_SPL_LIBGENERIC_SUPPORT |
||||
#define CONFIG_SPL_SERIAL_SUPPORT |
||||
#define CONFIG_SPL_I2C_SUPPORT |
||||
|
||||
/* SPL related SPI defines */ |
||||
#define CONFIG_SPL_SPI_SUPPORT |
||||
#define CONFIG_SPL_SPI_FLASH_SUPPORT |
||||
#define CONFIG_SPL_SPI_LOAD |
||||
#define CONFIG_SPL_SPI_BUS 0 |
||||
#define CONFIG_SPL_SPI_CS 0 |
||||
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x1a000 |
||||
#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS |
||||
|
||||
/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ |
||||
#define CONFIG_DDR_FIXED_SIZE (2 << 20) /* 2GiB */ |
||||
|
||||
#endif /* _CONFIG_THEADORABLE_H */ |
||||
Loading…
Reference in new issue