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rockchip: rk3288: Convert clock driver to use shifted masks

Browse Source 
Shifted masks are the standard approach with rockchip since it allows
use of the mask without shifting it each time. Update the definitions and
the driver to match.

Signed-off-by: Simon Glass <sjg@chromium.org>
master
Simon Glass 7 years ago
parent ed54b1918e
commit b223c1aead
2 changed files with 90 additions and 105 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
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  1. 74
      arch/arm/include/asm/arch-rockchip/cru_rk3288.h
  2. 121
      drivers/clk/rockchip/clk_rk3288.c

74
arch/arm/include/asm/arch-rockchip/cru_rk3288.h
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@ -64,135 +64,137 @@ check_member(rk3288_cru, cru_emmc_con[1], 0x021c);
/* CRU_CLKSEL11_CON */
enum {
HSICPHY_DIV_SHIFT = 8,
HSICPHY_DIV_MASK = 0x3f,
HSICPHY_DIV_MASK = 0x3f << HSICPHY_DIV_SHIFT,
MMC0_PLL_SHIFT = 6,
MMC0_PLL_MASK = 3,
MMC0_PLL_MASK = 3 << MMC0_PLL_SHIFT,
MMC0_PLL_SELECT_CODEC = 0,
MMC0_PLL_SELECT_GENERAL,
MMC0_PLL_SELECT_24MHZ,
MMC0_DIV_SHIFT = 0,
MMC0_DIV_MASK = 0x3f,
MMC0_DIV_MASK = 0x3f << MMC0_DIV_SHIFT,
};
/* CRU_CLKSEL12_CON */
enum {
EMMC_PLL_SHIFT = 0xe,
EMMC_PLL_MASK = 3,
EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT,
EMMC_PLL_SELECT_CODEC = 0,
EMMC_PLL_SELECT_GENERAL,
EMMC_PLL_SELECT_24MHZ,
EMMC_DIV_SHIFT = 8,
EMMC_DIV_MASK = 0x3f,
EMMC_DIV_MASK = 0x3f < EMMC_DIV_SHIFT,
SDIO0_PLL_SHIFT = 6,
SDIO0_PLL_MASK = 3,
SDIO0_PLL_MASK = 3 << SDIO0_PLL_SHIFT,
SDIO0_PLL_SELECT_CODEC = 0,
SDIO0_PLL_SELECT_GENERAL,
SDIO0_PLL_SELECT_24MHZ,
SDIO0_DIV_SHIFT = 0,
SDIO0_DIV_MASK = 0x3f,
SDIO0_DIV_MASK = 0x3f << SDIO0_DIV_SHIFT,
};
/* CRU_CLKSEL21_CON */
enum {
MAC_DIV_CON_SHIFT = 0xf,
MAC_DIV_CON_MASK = 0x1f,
MAC_DIV_CON_SHIFT = 0xf,
MAC_DIV_CON_MASK = 0x1f << MAC_DIV_CON_SHIFT,
RMII_EXTCLK_SHIFT = 4,
RMII_EXTCLK_MASK = 1,
RMII_EXTCLK_SHIFT = 4,
RMII_EXTCLK_MASK = 1 << RMII_EXTCLK_SHIFT,
RMII_EXTCLK_SELECT_INT_DIV_CLK = 0,
RMII_EXTCLK_SELECT_EXT_CLK = 1,
EMAC_PLL_SHIFT = 0,
EMAC_PLL_MASK = 0x3,
EMAC_PLL_SELECT_NEW = 0x0,
EMAC_PLL_SELECT_CODEC = 0x1,
EMAC_PLL_SELECT_GENERAL = 0x2,
EMAC_PLL_SHIFT = 0,
EMAC_PLL_MASK = 0x3 << EMAC_PLL_SHIFT,
EMAC_PLL_SELECT_NEW = 0x0,
EMAC_PLL_SELECT_CODEC = 0x1,
EMAC_PLL_SELECT_GENERAL = 0x2,
};
/* CRU_CLKSEL25_CON */
enum {
SPI1_PLL_SHIFT = 0xf,
SPI1_PLL_MASK = 1,
SPI1_PLL_MASK = 1 << SPI1_PLL_SHIFT,
SPI1_PLL_SELECT_CODEC = 0,
SPI1_PLL_SELECT_GENERAL,
SPI1_DIV_SHIFT = 8,
SPI1_DIV_MASK = 0x7f,
SPI1_DIV_MASK = 0x7f << SPI1_DIV_SHIFT,
SPI0_PLL_SHIFT = 7,
SPI0_PLL_MASK = 1,
SPI0_PLL_MASK = 1 << SPI0_PLL_SHIFT,
SPI0_PLL_SELECT_CODEC = 0,
SPI0_PLL_SELECT_GENERAL,
SPI0_DIV_SHIFT = 0,
SPI0_DIV_MASK = 0x7f,
SPI0_DIV_MASK = 0x7f << SPI0_DIV_SHIFT,
};
/* CRU_CLKSEL37_CON */
enum {
PCLK_CORE_DBG_DIV_SHIFT = 9,
PCLK_CORE_DBG_DIV_MASK = 0x1f,
PCLK_CORE_DBG_DIV_MASK = 0x1f << PCLK_CORE_DBG_DIV_SHIFT,
ATCLK_CORE_DIV_CON_SHIFT = 4,
ATCLK_CORE_DIV_CON_MASK = 0x1f,
ATCLK_CORE_DIV_CON_MASK = 0x1f << ATCLK_CORE_DIV_CON_SHIFT,
CLK_L2RAM_DIV_SHIFT = 0,
CLK_L2RAM_DIV_MASK = 7,
CLK_L2RAM_DIV_MASK = 7 << CLK_L2RAM_DIV_SHIFT,
};
/* CRU_CLKSEL39_CON */
enum {
ACLK_HEVC_PLL_SHIFT = 0xe,
ACLK_HEVC_PLL_MASK = 3,
ACLK_HEVC_PLL_MASK = 3 << ACLK_HEVC_PLL_SHIFT,
ACLK_HEVC_PLL_SELECT_CODEC = 0,
ACLK_HEVC_PLL_SELECT_GENERAL,
ACLK_HEVC_PLL_SELECT_NEW,
ACLK_HEVC_DIV_SHIFT = 8,
ACLK_HEVC_DIV_MASK = 0x1f,
ACLK_HEVC_DIV_MASK = 0x1f << ACLK_HEVC_DIV_SHIFT,
SPI2_PLL_SHIFT = 7,
SPI2_PLL_MASK = 1,
SPI2_PLL_MASK = 1 << SPI2_PLL_SHIFT,
SPI2_PLL_SELECT_CODEC = 0,
SPI2_PLL_SELECT_GENERAL,
SPI2_DIV_SHIFT = 0,
SPI2_DIV_MASK = 0x7f,
SPI2_DIV_MASK = 0x7f << SPI2_DIV_SHIFT,
};
/* CRU_MODE_CON */
enum {
CRU_MODE_MASK = 3,
NPLL_MODE_SHIFT = 0xe,
NPLL_MODE_MASK = 3,
NPLL_MODE_MASK = CRU_MODE_MASK << NPLL_MODE_SHIFT,
NPLL_MODE_SLOW = 0,
NPLL_MODE_NORMAL,
NPLL_MODE_DEEP,
GPLL_MODE_SHIFT = 0xc,
GPLL_MODE_MASK = 3,
GPLL_MODE_MASK = CRU_MODE_MASK << GPLL_MODE_SHIFT,
GPLL_MODE_SLOW = 0,
GPLL_MODE_NORMAL,
GPLL_MODE_DEEP,
CPLL_MODE_SHIFT = 8,
CPLL_MODE_MASK = 3,
CPLL_MODE_MASK = CRU_MODE_MASK << CPLL_MODE_SHIFT,
CPLL_MODE_SLOW = 0,
CPLL_MODE_NORMAL,
CPLL_MODE_DEEP,
DPLL_MODE_SHIFT = 4,
DPLL_MODE_MASK = 3,
DPLL_MODE_MASK = CRU_MODE_MASK << DPLL_MODE_SHIFT,
DPLL_MODE_SLOW = 0,
DPLL_MODE_NORMAL,
DPLL_MODE_DEEP,
APLL_MODE_SHIFT = 0,
APLL_MODE_MASK = 3,
APLL_MODE_MASK = CRU_MODE_MASK << APLL_MODE_SHIFT,
APLL_MODE_SLOW = 0,
APLL_MODE_NORMAL,
APLL_MODE_DEEP,
@ -201,21 +203,21 @@ enum {
/* CRU_APLL_CON0 */
enum {
CLKR_SHIFT = 8,
CLKR_MASK = 0x3f,
CLKR_MASK = 0x3f << CLKR_SHIFT,
CLKOD_SHIFT = 0,
CLKOD_MASK = 0xf,
CLKOD_MASK = 0xf << CLKOD_SHIFT,
};
/* CRU_APLL_CON1 */
enum {
LOCK_SHIFT = 0x1f,
LOCK_MASK = 1,
LOCK_MASK = 1 << LOCK_SHIFT,
LOCK_UNLOCK = 0,
LOCK_LOCK,
CLKF_SHIFT = 0,
CLKF_MASK = 0x1fff,
CLKF_MASK = 0x1fff << CLKF_SHIFT,
};
#endif

121
drivers/clk/rockchip/clk_rk3288.c
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@ -59,14 +59,14 @@ enum {
PLL_RESET_SHIFT = 5,
/* CLKSEL0 */
CORE_SEL_PLL_MASK = 1,
CORE_SEL_PLL_SHIFT = 15,
A17_DIV_MASK = 0x1f,
CORE_SEL_PLL_MASK = 1 << CORE_SEL_PLL_SHIFT,
A17_DIV_SHIFT = 8,
MP_DIV_MASK = 0xf,
A17_DIV_MASK = 0x1f << A17_DIV_SHIFT,
MP_DIV_SHIFT = 4,
M0_DIV_MASK = 0xf,
MP_DIV_MASK = 0xf << MP_DIV_SHIFT,
M0_DIV_SHIFT = 0,
M0_DIV_MASK = 0xf << M0_DIV_SHIFT,
/* CLKSEL1: pd bus clk pll sel: codec or general */
PD_BUS_SEL_PLL_MASK = 15,
@ -75,41 +75,41 @@ enum {
/* pd bus pclk div: pclk = pd_bus_aclk /(div + 1) */
PD_BUS_PCLK_DIV_SHIFT = 12,
PD_BUS_PCLK_DIV_MASK = 7,
PD_BUS_PCLK_DIV_MASK = 7 << PD_BUS_PCLK_DIV_SHIFT,
/* pd bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */
PD_BUS_HCLK_DIV_SHIFT = 8,
PD_BUS_HCLK_DIV_MASK = 3,
PD_BUS_HCLK_DIV_MASK = 3 << PD_BUS_HCLK_DIV_SHIFT,
/* pd bus aclk div: pd_bus_aclk = pd_bus_src_clk /(div0 * div1) */
PD_BUS_ACLK_DIV0_SHIFT = 3,
PD_BUS_ACLK_DIV0_MASK = 0x1f,
PD_BUS_ACLK_DIV0_MASK = 0x1f << PD_BUS_ACLK_DIV0_SHIFT,
PD_BUS_ACLK_DIV1_SHIFT = 0,
PD_BUS_ACLK_DIV1_MASK = 0x7,
PD_BUS_ACLK_DIV1_MASK = 0x7 << PD_BUS_ACLK_DIV1_SHIFT,
/*
* CLKSEL10
* peripheral bus pclk div:
* aclk_bus: pclk_bus = 1:1 or 2:1 or 4:1 or 8:1
*/
PERI_SEL_PLL_MASK = 1,
PERI_SEL_PLL_SHIFT = 15,
PERI_SEL_PLL_MASK = 1 << PERI_SEL_PLL_SHIFT,
PERI_SEL_CPLL = 0,
PERI_SEL_GPLL,
PERI_PCLK_DIV_SHIFT = 12,
PERI_PCLK_DIV_MASK = 3,
PERI_PCLK_DIV_MASK = 3 << PERI_PCLK_DIV_SHIFT,
/* peripheral bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */
PERI_HCLK_DIV_SHIFT = 8,
PERI_HCLK_DIV_MASK = 3,
PERI_HCLK_DIV_MASK = 3 << PERI_HCLK_DIV_SHIFT,
/*
* peripheral bus aclk div:
* aclk_periph = periph_clk_src / (peri_aclk_div_con + 1)
*/
PERI_ACLK_DIV_SHIFT = 0,
PERI_ACLK_DIV_MASK = 0x1f,
PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT,
SOCSTS_DPLL_LOCK = 1 << 5,
SOCSTS_APLL_LOCK = 1 << 6,
@ -154,8 +154,7 @@ static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id,
/* enter reset */
rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT);
rk_clrsetreg(&pll->con0,
CLKR_MASK << CLKR_SHIFT | PLL_OD_MASK,
rk_clrsetreg(&pll->con0, CLKR_MASK | PLL_OD_MASK,
((div->nr - 1) << CLKR_SHIFT) | (div->no - 1));
rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1);
rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1);
@ -198,7 +197,7 @@ static int rkclk_configure_ddr(struct rk3288_cru *cru, struct rk3288_grf *grf,
}
/* pll enter slow-mode */
rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT,
rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
DPLL_MODE_SLOW << DPLL_MODE_SHIFT);
rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg]);
@ -208,7 +207,7 @@ static int rkclk_configure_ddr(struct rk3288_cru *cru, struct rk3288_grf *grf,
udelay(1);
/* PLL enter normal-mode */
rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT,
rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
DPLL_MODE_NORMAL << DPLL_MODE_SHIFT);
return 0;
@ -296,7 +295,7 @@ static int rockchip_mac_set_clk(struct rk3288_cru *cru,
{
/* Assuming mac_clk is fed by an external clock */
rk_clrsetreg(&cru->cru_clksel_con[21],
RMII_EXTCLK_MASK << RMII_EXTCLK_SHIFT,
RMII_EXTCLK_MASK,
RMII_EXTCLK_SELECT_EXT_CLK << RMII_EXTCLK_SHIFT);
return 0;
@ -313,7 +312,7 @@ static int rockchip_vop_set_clk(struct rk3288_cru *cru, struct rk3288_grf *grf,
if (ret)
return ret;
rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK << NPLL_MODE_SHIFT,
rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK,
NPLL_MODE_SLOW << NPLL_MODE_SHIFT);
rkclk_set_pll(cru, CLK_NEW, &npll_config);
@ -324,7 +323,7 @@ static int rockchip_vop_set_clk(struct rk3288_cru *cru, struct rk3288_grf *grf,
udelay(1);
}
rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK << NPLL_MODE_SHIFT,
rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK,
NPLL_MODE_NORMAL << NPLL_MODE_SHIFT);
/* vop dclk source clk: npll,dclk_div: 1 */
@ -352,8 +351,7 @@ static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf)
/* pll enter slow-mode */
rk_clrsetreg(&cru->cru_mode_con,
GPLL_MODE_MASK << GPLL_MODE_SHIFT |
CPLL_MODE_MASK << CPLL_MODE_SHIFT,
GPLL_MODE_MASK | CPLL_MODE_MASK,
GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
CPLL_MODE_SLOW << CPLL_MODE_SHIFT);
@ -382,10 +380,8 @@ static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf)
PD_BUS_ACLK_HZ && pclk_div < 0x7);
rk_clrsetreg(&cru->cru_clksel_con[1],
PD_BUS_PCLK_DIV_MASK << PD_BUS_PCLK_DIV_SHIFT |
PD_BUS_HCLK_DIV_MASK << PD_BUS_HCLK_DIV_SHIFT |
PD_BUS_ACLK_DIV0_MASK << PD_BUS_ACLK_DIV0_SHIFT |
PD_BUS_ACLK_DIV1_MASK << PD_BUS_ACLK_DIV1_SHIFT,
PD_BUS_PCLK_DIV_MASK | PD_BUS_HCLK_DIV_MASK |
PD_BUS_ACLK_DIV0_MASK | PD_BUS_ACLK_DIV1_MASK,
pclk_div << PD_BUS_PCLK_DIV_SHIFT |
hclk_div << PD_BUS_HCLK_DIV_SHIFT |
aclk_div << PD_BUS_ACLK_DIV0_SHIFT |
@ -407,9 +403,8 @@ static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf)
PERI_ACLK_HZ && (pclk_div < 0x4));
rk_clrsetreg(&cru->cru_clksel_con[10],
PERI_PCLK_DIV_MASK << PERI_PCLK_DIV_SHIFT |
PERI_HCLK_DIV_MASK << PERI_HCLK_DIV_SHIFT |
PERI_ACLK_DIV_MASK << PERI_ACLK_DIV_SHIFT,
PERI_PCLK_DIV_MASK | PERI_HCLK_DIV_MASK |
PERI_ACLK_DIV_MASK,
PERI_SEL_GPLL << PERI_SEL_PLL_SHIFT |
pclk_div << PERI_PCLK_DIV_SHIFT |
hclk_div << PERI_HCLK_DIV_SHIFT |
@ -417,8 +412,7 @@ static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf)
/* PLL enter normal-mode */
rk_clrsetreg(&cru->cru_mode_con,
GPLL_MODE_MASK << GPLL_MODE_SHIFT |
CPLL_MODE_MASK << CPLL_MODE_SHIFT,
GPLL_MODE_MASK | CPLL_MODE_MASK,
GPLL_MODE_NORMAL << GPLL_MODE_SHIFT |
CPLL_MODE_NORMAL << CPLL_MODE_SHIFT);
}
@ -427,8 +421,7 @@ static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf)
void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf)
{
/* pll enter slow-mode */
rk_clrsetreg(&cru->cru_mode_con,
APLL_MODE_MASK << APLL_MODE_SHIFT,
rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK,
APLL_MODE_SLOW << APLL_MODE_SHIFT);
rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
@ -444,10 +437,8 @@ void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf)
* arm clk = 1800MHz, mpclk = 450MHz, m0clk = 900MHz
*/
rk_clrsetreg(&cru->cru_clksel_con[0],
CORE_SEL_PLL_MASK << CORE_SEL_PLL_SHIFT |
A17_DIV_MASK << A17_DIV_SHIFT |
MP_DIV_MASK << MP_DIV_SHIFT |
M0_DIV_MASK << M0_DIV_SHIFT,
CORE_SEL_PLL_MASK | A17_DIV_MASK | MP_DIV_MASK |
M0_DIV_MASK,
0 << A17_DIV_SHIFT |
3 << MP_DIV_SHIFT |
1 << M0_DIV_SHIFT);
@ -457,16 +448,14 @@ void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf)
* l2ramclk = 900MHz, atclk = 450MHz, pclk_dbg = 450MHz
*/
rk_clrsetreg(&cru->cru_clksel_con[37],
CLK_L2RAM_DIV_MASK << CLK_L2RAM_DIV_SHIFT |
ATCLK_CORE_DIV_CON_MASK << ATCLK_CORE_DIV_CON_SHIFT |
PCLK_CORE_DBG_DIV_MASK >> PCLK_CORE_DBG_DIV_SHIFT,
CLK_L2RAM_DIV_MASK | ATCLK_CORE_DIV_CON_MASK |
PCLK_CORE_DBG_DIV_MASK,
1 << CLK_L2RAM_DIV_SHIFT |
3 << ATCLK_CORE_DIV_CON_SHIFT |
3 << PCLK_CORE_DBG_DIV_SHIFT);
/* PLL enter normal-mode */
rk_clrsetreg(&cru->cru_mode_con,
APLL_MODE_MASK << APLL_MODE_SHIFT,
rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK,
APLL_MODE_NORMAL << APLL_MODE_SHIFT);
}
@ -486,16 +475,16 @@ static uint32_t rkclk_pll_get_rate(struct rk3288_cru *cru,
con = readl(&cru->cru_mode_con);
shift = clk_shift[clk_id];
switch ((con >> shift) & APLL_MODE_MASK) {
switch ((con >> shift) & CRU_MODE_MASK) {
case APLL_MODE_SLOW:
return OSC_HZ;
case APLL_MODE_NORMAL:
/* normal mode */
con = readl(&pll->con0);
no = ((con >> CLKOD_SHIFT) & CLKOD_MASK) + 1;
nr = ((con >> CLKR_SHIFT) & CLKR_MASK) + 1;
no = ((con & CLKOD_MASK) >> CLKOD_SHIFT) + 1;
nr = ((con & CLKR_MASK) >> CLKR_SHIFT) + 1;
con = readl(&pll->con1);
nf = ((con >> CLKF_SHIFT) & CLKF_MASK) + 1;
nf = ((con & CLKF_MASK) >> CLKF_SHIFT) + 1;
return (24 * nf / (nr * no)) * 1000000;
case APLL_MODE_DEEP:
@ -515,20 +504,20 @@ static ulong rockchip_mmc_get_clk(struct rk3288_cru *cru, uint gclk_rate,
case HCLK_EMMC:
case SCLK_EMMC:
con = readl(&cru->cru_clksel_con[12]);
mux = (con >> EMMC_PLL_SHIFT) & EMMC_PLL_MASK;
div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK;
mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT;
div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT;
break;
case HCLK_SDMMC:
case SCLK_SDMMC:
con = readl(&cru->cru_clksel_con[11]);
mux = (con >> MMC0_PLL_SHIFT) & MMC0_PLL_MASK;
div = (con >> MMC0_DIV_SHIFT) & MMC0_DIV_MASK;
mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT;
div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT;
break;
case HCLK_SDIO0:
case SCLK_SDIO0:
con = readl(&cru->cru_clksel_con[12]);
mux = (con >> SDIO0_PLL_SHIFT) & SDIO0_PLL_MASK;
div = (con >> SDIO0_DIV_SHIFT) & SDIO0_DIV_MASK;
mux = (con & SDIO0_PLL_MASK) >> SDIO0_PLL_SHIFT;
div = (con & SDIO0_DIV_MASK) >> SDIO0_DIV_SHIFT;
break;
default:
return -EINVAL;
@ -561,24 +550,21 @@ static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate,
case HCLK_EMMC:
case SCLK_EMMC:
rk_clrsetreg(&cru->cru_clksel_con[12],
EMMC_PLL_MASK << EMMC_PLL_SHIFT |
EMMC_DIV_MASK << EMMC_DIV_SHIFT,
EMMC_PLL_MASK | EMMC_DIV_MASK,
mux << EMMC_PLL_SHIFT |
(src_clk_div - 1) << EMMC_DIV_SHIFT);
break;
case HCLK_SDMMC:
case SCLK_SDMMC:
rk_clrsetreg(&cru->cru_clksel_con[11],
MMC0_PLL_MASK << MMC0_PLL_SHIFT |
MMC0_DIV_MASK << MMC0_DIV_SHIFT,
MMC0_PLL_MASK | MMC0_DIV_MASK,
mux << MMC0_PLL_SHIFT |
(src_clk_div - 1) << MMC0_DIV_SHIFT);
break;
case HCLK_SDIO0:
case SCLK_SDIO0:
rk_clrsetreg(&cru->cru_clksel_con[12],
SDIO0_PLL_MASK << SDIO0_PLL_SHIFT |
SDIO0_DIV_MASK << SDIO0_DIV_SHIFT,
SDIO0_PLL_MASK | SDIO0_DIV_MASK,
mux << SDIO0_PLL_SHIFT |
(src_clk_div - 1) << SDIO0_DIV_SHIFT);
break;
@ -598,18 +584,18 @@ static ulong rockchip_spi_get_clk(struct rk3288_cru *cru, uint gclk_rate,
switch (periph) {
case SCLK_SPI0:
con = readl(&cru->cru_clksel_con[25]);
mux = (con >> SPI0_PLL_SHIFT) & SPI0_PLL_MASK;
div = (con >> SPI0_DIV_SHIFT) & SPI0_DIV_MASK;
mux = (con & SPI0_PLL_MASK) >> SPI0_PLL_SHIFT;
div = (con & SPI0_DIV_MASK) >> SPI0_DIV_SHIFT;
break;
case SCLK_SPI1:
con = readl(&cru->cru_clksel_con[25]);
mux = (con >> SPI1_PLL_SHIFT) & SPI1_PLL_MASK;
div = (con >> SPI1_DIV_SHIFT) & SPI1_DIV_MASK;
mux = (con & SPI1_PLL_MASK) >> SPI1_PLL_SHIFT;
div = (con & SPI1_DIV_MASK) >> SPI1_DIV_SHIFT;
break;
case SCLK_SPI2:
con = readl(&cru->cru_clksel_con[39]);
mux = (con >> SPI2_PLL_SHIFT) & SPI2_PLL_MASK;
div = (con >> SPI2_DIV_SHIFT) & SPI2_DIV_MASK;
mux = (con & SPI2_PLL_MASK) >> SPI2_PLL_SHIFT;
div = (con & SPI2_DIV_MASK) >> SPI2_DIV_SHIFT;
break;
default:
return -EINVAL;
@ -629,22 +615,19 @@ static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate,
switch (periph) {
case SCLK_SPI0:
rk_clrsetreg(&cru->cru_clksel_con[25],
SPI0_PLL_MASK << SPI0_PLL_SHIFT |
SPI0_DIV_MASK << SPI0_DIV_SHIFT,
SPI0_PLL_MASK | SPI0_DIV_MASK,
SPI0_PLL_SELECT_GENERAL << SPI0_PLL_SHIFT |
src_clk_div << SPI0_DIV_SHIFT);
break;
case SCLK_SPI1:
rk_clrsetreg(&cru->cru_clksel_con[25],
SPI1_PLL_MASK << SPI1_PLL_SHIFT |
SPI1_DIV_MASK << SPI1_DIV_SHIFT,
SPI1_PLL_MASK | SPI1_DIV_MASK,
SPI1_PLL_SELECT_GENERAL << SPI1_PLL_SHIFT |
src_clk_div << SPI1_DIV_SHIFT);
break;
case SCLK_SPI2:
rk_clrsetreg(&cru->cru_clksel_con[39],
SPI2_PLL_MASK << SPI2_PLL_SHIFT |
SPI2_DIV_MASK << SPI2_DIV_SHIFT,
SPI2_PLL_MASK | SPI2_DIV_MASK,
SPI2_PLL_SELECT_GENERAL << SPI2_PLL_SHIFT |
src_clk_div << SPI2_DIV_SHIFT);
break;

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