This board is based on the Atmel sama5d3 eval boards. Supporting the following features: - Boot from NAND Flash - Ethernet - FIT - SPL Signed-off-by: Ben Whitten <ben.whitten@lairdtech.com> Signed-off-by: Dan Kephart <dan.kephart@lairdtech.com>master
Ben Whitten
7 years ago
committed by
Tom Rini
parent
5aaef60077
commit
b2e01ff543
@ -0,0 +1,12 @@ |
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if TARGET_WB50N |
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config SYS_BOARD |
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default "wb50n" |
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config SYS_VENDOR |
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default "laird" |
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config SYS_CONFIG_NAME |
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default "wb50n" |
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endif |
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@ -0,0 +1,6 @@ |
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WB50N CPU MODULE |
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M: Ben Whitten <ben.whitten@lairdtech.com> |
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S: Maintained |
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F: board/laird/wb50n/ |
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F: include/configs/wb50n.h |
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F: configs/wb50n_defconfig |
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@ -0,0 +1,6 @@ |
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#
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += wb50n.o
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@ -0,0 +1,206 @@ |
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/*
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/io.h> |
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#include <asm/arch/sama5_sfr.h> |
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#include <asm/arch/sama5d3_smc.h> |
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#include <asm/arch/at91_common.h> |
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#include <asm/arch/at91_pmc.h> |
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#include <asm/arch/at91_rstc.h> |
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#include <asm/arch/gpio.h> |
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#include <asm/arch/clk.h> |
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#include <micrel.h> |
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#include <net.h> |
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#include <netdev.h> |
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#include <spl.h> |
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#include <asm/arch/atmel_mpddrc.h> |
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#include <asm/arch/at91_wdt.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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/* ------------------------------------------------------------------------- */ |
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/*
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* Miscelaneous platform dependent initialisations |
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*/ |
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void wb50n_nand_hw_init(void) |
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{ |
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struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; |
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at91_periph_clk_enable(ATMEL_ID_SMC); |
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/* Configure SMC CS3 for NAND/SmartMedia */ |
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writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(1) | |
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AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(1), |
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&smc->cs[3].setup); |
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writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) | |
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AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(5), |
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&smc->cs[3].pulse); |
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writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8), |
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&smc->cs[3].cycle); |
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writel(AT91_SMC_TIMINGS_TCLR(3) | AT91_SMC_TIMINGS_TADL(10) | |
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AT91_SMC_TIMINGS_TAR(3) | AT91_SMC_TIMINGS_TRR(4) | |
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AT91_SMC_TIMINGS_TWB(5) | AT91_SMC_TIMINGS_RBNSEL(3) | |
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AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings); |
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writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | |
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AT91_SMC_MODE_EXNW_DISABLE | |
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AT91_SMC_MODE_DBW_8 | |
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AT91_SMC_MODE_TDF_CYCLE(3), &smc->cs[3].mode); |
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/* Disable Flash Write Protect Line */ |
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at91_set_pio_output(AT91_PIO_PORTE, 14, 1); |
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} |
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int board_early_init_f(void) |
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{ |
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at91_periph_clk_enable(ATMEL_ID_PIOA); |
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at91_periph_clk_enable(ATMEL_ID_PIOB); |
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at91_periph_clk_enable(ATMEL_ID_PIOC); |
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at91_periph_clk_enable(ATMEL_ID_PIOD); |
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at91_periph_clk_enable(ATMEL_ID_PIOE); |
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at91_seriald_hw_init(); |
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return 0; |
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} |
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int board_init(void) |
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{ |
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/* adress of boot parameters */ |
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; |
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wb50n_nand_hw_init(); |
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at91_macb_hw_init(); |
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return 0; |
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} |
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int dram_init(void) |
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{ |
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gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, |
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CONFIG_SYS_SDRAM_SIZE); |
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return 0; |
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} |
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int board_phy_config(struct phy_device *phydev) |
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{ |
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/* rx data delay */ |
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ksz9021_phy_extended_write(phydev, |
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MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x2222); |
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/* tx data delay */ |
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ksz9021_phy_extended_write(phydev, |
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MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x2222); |
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/* rx/tx clock delay */ |
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ksz9021_phy_extended_write(phydev, |
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MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf2f4); |
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return 0; |
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} |
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int board_eth_init(bd_t *bis) |
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{ |
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int rc = 0; |
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rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00); |
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return rc; |
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} |
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#ifdef CONFIG_BOARD_LATE_INIT |
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#include <linux/ctype.h> |
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int board_late_init(void) |
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{ |
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#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG |
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const char *LAIRD_NAME = "lrd_name"; |
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char name[32], *p; |
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strcpy(name, get_cpu_name()); |
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for (p = name; *p != '\0'; *p = tolower(*p), p++) |
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; |
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strcat(name, "-wb50n"); |
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env_set(LAIRD_NAME, name); |
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#endif |
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return 0; |
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} |
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#endif |
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/* SPL */ |
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#ifdef CONFIG_SPL_BUILD |
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void spl_board_init(void) |
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{ |
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wb50n_nand_hw_init(); |
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} |
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static void ddr2_conf(struct atmel_mpddrc_config *ddr2) |
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{ |
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ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_LPDDR_SDRAM); |
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ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_9 | |
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ATMEL_MPDDRC_CR_NR_ROW_13 | |
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ATMEL_MPDDRC_CR_CAS_DDR_CAS3 | |
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ATMEL_MPDDRC_CR_NDQS_DISABLED | |
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ATMEL_MPDDRC_CR_DECOD_INTERLEAVED | |
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ATMEL_MPDDRC_CR_UNAL_SUPPORTED); |
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ddr2->rtr = 0x411; |
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ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | |
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2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET | |
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2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | |
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8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | |
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2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | |
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2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | |
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2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | |
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2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); |
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ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | |
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200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | |
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19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | |
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18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET); |
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ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | |
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2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | |
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3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | |
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7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | |
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2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET); |
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} |
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void mem_init(void) |
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{ |
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struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR; |
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struct atmel_mpddrc_config ddr2; |
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ddr2_conf(&ddr2); |
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writel(ATMEL_SFR_DDRCFG_FDQIEN | ATMEL_SFR_DDRCFG_FDQSIEN, |
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&sfr->ddrcfg); |
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/* enable MPDDR clock */ |
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at91_periph_clk_enable(ATMEL_ID_MPDDRC); |
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at91_system_clk_enable(AT91_PMC_DDR); |
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/* DDRAM2 Controller initialize */ |
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ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2); |
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} |
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void at91_pmc_init(void) |
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{ |
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u32 tmp; |
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tmp = AT91_PMC_PLLAR_29 | |
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AT91_PMC_PLLXR_PLLCOUNT(0x3f) | |
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AT91_PMC_PLLXR_MUL(43) | AT91_PMC_PLLXR_DIV(1); |
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at91_plla_init(tmp); |
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at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x3)); |
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tmp = AT91_PMC_MCKR_MDIV_4 | AT91_PMC_MCKR_CSS_PLLA; |
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at91_mck_init(tmp); |
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} |
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#endif |
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@ -0,0 +1,30 @@ |
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CONFIG_ARM=y |
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CONFIG_ARCH_AT91=y |
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CONFIG_TARGET_WB50N=y |
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CONFIG_SPL_GPIO_SUPPORT=y |
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CONFIG_SPL_LIBCOMMON_SUPPORT=y |
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CONFIG_SPL_LIBGENERIC_SUPPORT=y |
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CONFIG_SPL_SERIAL_SUPPORT=y |
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CONFIG_SPL_NAND_SUPPORT=y |
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CONFIG_FIT=y |
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CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_NANDFLASH" |
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CONFIG_BOOTDELAY=3 |
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CONFIG_SPL=y |
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CONFIG_HUSH_PARSER=y |
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CONFIG_CMD_BOOTZ=y |
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CONFIG_CMD_MEMTEST=y |
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# CONFIG_CMD_FLASH is not set |
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# CONFIG_CMD_FPGA is not set |
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# CONFIG_CMD_LOADS is not set |
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CONFIG_CMD_NAND=y |
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CONFIG_CMD_NAND_TRIMFFS=y |
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CONFIG_CMD_DHCP=y |
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CONFIG_CMD_MII=y |
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CONFIG_CMD_PING=y |
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CONFIG_ENV_IS_IN_NAND=y |
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CONFIG_PHYLIB=y |
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CONFIG_PHY_MICREL=y |
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CONFIG_PHY_MICREL_KSZ90X1=y |
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CONFIG_NETDEVICES=y |
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CONFIG_LZMA=y |
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CONFIG_OF_LIBFDT=y |
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@ -0,0 +1,139 @@ |
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/*
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* Configuation settings for the WB50N CPU Module. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef __CONFIG_H |
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#define __CONFIG_H |
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#include <asm/hardware.h> |
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#define CONFIG_SYS_TEXT_BASE 0x23f00000 |
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/* ARM asynchronous clock */ |
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#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 |
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#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ |
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#define CONFIG_ARCH_CPU_INIT |
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#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ |
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#define CONFIG_SETUP_MEMORY_TAGS |
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#define CONFIG_INITRD_TAG |
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#ifndef CONFIG_SPL_BUILD |
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#define CONFIG_SKIP_LOWLEVEL_INIT |
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#endif |
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#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG |
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#define CONFIG_IMAGE_FORMAT_LEGACY |
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/* general purpose I/O */ |
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#define CONFIG_AT91_GPIO |
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/* serial console */ |
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#define CONFIG_ATMEL_USART |
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#define CONFIG_USART_BASE ATMEL_BASE_DBGU |
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#define CONFIG_USART_ID ATMEL_ID_DBGU |
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/*
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* BOOTP options |
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*/ |
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#define CONFIG_BOOTP_BOOTFILESIZE |
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#define CONFIG_BOOTP_BOOTPATH |
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#define CONFIG_BOOTP_GATEWAY |
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#define CONFIG_BOOTP_HOSTNAME |
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/* SDRAM */ |
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#define CONFIG_NR_DRAM_BANKS 1 |
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#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS |
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#define CONFIG_SYS_SDRAM_SIZE 0x04000000 |
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#ifdef CONFIG_SPL_BUILD |
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#define CONFIG_SYS_INIT_SP_ADDR 0x310000 |
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#else |
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#define CONFIG_SYS_INIT_SP_ADDR \ |
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(CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) |
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#endif |
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#define CONFIG_SYS_MEMTEST_START 0x21000000 |
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#define CONFIG_SYS_MEMTEST_END 0x22000000 |
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#define CONFIG_SYS_ALT_MEMTEST |
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/* NAND flash */ |
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#define CONFIG_NAND_ATMEL |
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#define CONFIG_SYS_MAX_NAND_DEVICE 1 |
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#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 |
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/* our ALE is AD21 */ |
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#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) |
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/* our CLE is AD22 */ |
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#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) |
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#define CONFIG_SYS_NAND_ONFI_DETECTION |
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/* PMECC & PMERRLOC */ |
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#define CONFIG_ATMEL_NAND_HWECC |
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#define CONFIG_ATMEL_NAND_HW_PMECC |
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#define CONFIG_PMECC_CAP 8 |
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#define CONFIG_PMECC_SECTOR_SIZE 512 |
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/* Ethernet Hardware */ |
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#define CONFIG_MACB |
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#define CONFIG_RMII |
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#define CONFIG_NET_RETRY_COUNT 20 |
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#define CONFIG_MACB_SEARCH_PHY |
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#define CONFIG_RGMII |
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#define CONFIG_ETHADDR C0:EE:40:00:00:00 |
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#define CONFIG_ENV_OVERWRITE 1 |
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#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ |
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#define CONFIG_EXTRA_ENV_SETTINGS \ |
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"autoload=no\0" \
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"autostart=no\0" |
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/* bootstrap + u-boot + env in nandflash */ |
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#define CONFIG_ENV_OFFSET 0xA0000 |
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#define CONFIG_ENV_OFFSET_REDUND 0xC0000 |
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#define CONFIG_ENV_SIZE 0x20000 |
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#define CONFIG_BOOTCOMMAND \ |
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"nand read 0x22000000 0x000e0000 0x500000; " \
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"bootm" |
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#define CONFIG_BOOTARGS \ |
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"rw rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs" |
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#define CONFIG_BAUDRATE 115200 |
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#define CONFIG_SYS_CBSIZE 1024 |
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#define CONFIG_SYS_MAXARGS 16 |
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#define CONFIG_SYS_PBSIZE \ |
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(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) |
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#define CONFIG_SYS_LONGHELP |
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#define CONFIG_CMDLINE_EDITING |
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#define CONFIG_AUTO_COMPLETE |
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/* Size of malloc() pool */ |
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#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024) |
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/* SPL */ |
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#define CONFIG_SPL_FRAMEWORK |
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#define CONFIG_SPL_TEXT_BASE 0x300000 |
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#define CONFIG_SPL_MAX_SIZE 0x10000 |
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#define CONFIG_SPL_BSS_START_ADDR 0x20000000 |
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#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 |
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#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 |
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#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 |
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#define CONFIG_SYS_MONITOR_LEN (512 << 10) |
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#define CONFIG_SPL_NAND_DRIVERS |
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#define CONFIG_SPL_NAND_BASE |
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 |
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#define CONFIG_SYS_NAND_5_ADDR_CYCLE |
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#define CONFIG_SYS_NAND_PAGE_SIZE 0x800 |
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#define CONFIG_SYS_NAND_PAGE_COUNT 64 |
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#define CONFIG_SYS_NAND_OOBSIZE 64 |
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#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 |
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#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 |
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#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER |
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#endif |
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