This board has not been converted to generic board by the deadline. Remove it. Signed-off-by: Simon Glass <sjg@chromium.org>master
Simon Glass
9 years ago
committed by
Tom Rini
parent
d7e8b2b98a
commit
b352182a00
@ -1,12 +0,0 @@ |
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if TARGET_WIRELESS_SPACE |
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config SYS_BOARD |
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default "wireless_space" |
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config SYS_VENDOR |
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default "LaCie" |
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config SYS_CONFIG_NAME |
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default "wireless_space" |
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endif |
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@ -1,6 +0,0 @@ |
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WIRELESS_SPACE BOARD |
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M: Albert ARIBAUD <albert.u.boot@aribaud.net> |
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S: Maintained |
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F: board/LaCie/wireless_space/ |
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F: include/configs/wireless_space.h |
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F: configs/wireless_space_defconfig |
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@ -1,12 +0,0 @@ |
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#
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# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
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#
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# Based on Kirkwood support:
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# (C) Copyright 2009
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# Marvell Semiconductor <www.marvell.com>
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# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := wireless_space.o ../common/common.o
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@ -1,71 +0,0 @@ |
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# |
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# Copyright (C) 2012 Albert ARIBAUD <albert.u.boot@aribaud.net> |
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# |
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# Based on netspace_v2 kwbimage.cfg: |
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# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com> |
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# |
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# Based on Kirkwood support: |
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# (C) Copyright 2009 |
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# Marvell Semiconductor <www.marvell.com> |
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# Written-by: Prafulla Wadaskar <prafulla@marvell.com> |
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# |
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# SPDX-License-Identifier: GPL-2.0+ |
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# |
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# Refer doc/README.kwbimage for more details about how-to configure |
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# and create kirkwood boot image |
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# |
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|
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# Boot Media configurations |
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BOOT_FROM nand # Boot from NAND flash |
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NAND_PAGE_SIZE 800 |
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# SOC registers configuration using bootrom header extension |
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# Maximum KWBIMAGE_MAX_CONFIG configurations allowed |
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# Values taken from image original LaCie U-Boot header dump! |
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# Configure RGMII-0 interface pad voltage to 1.8V |
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DATA 0xFFD100e0 0x1B1B1B9B |
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#Dram initalization for SINGLE x16 CL=5 @ 400MHz |
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DATA 0xFFD01400 0x43000c30 # DDR Configuration register |
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DATA 0xFFD01404 0x37743000 # DDR Controller Control Low |
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DATA 0xFFD01408 0x11012228 # DDR Timing (Low) (active cycles value +1) |
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DATA 0xFFD0140C 0x00000A19 # DDR Timing (High) |
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DATA 0xFFD01410 0x0000CCCC # DDR Address Control |
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DATA 0xFFD01414 0x00000000 # DDR Open Pages Control |
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DATA 0xFFD01418 0x00000000 # DDR Operation |
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DATA 0xFFD0141C 0x00000662 # DDR Mode |
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DATA 0xFFD01420 0x00000004 # DDR Extended Mode |
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DATA 0xFFD01424 0x0000F07F # DDR Controller Control High |
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DATA 0xFFD01428 0x00096630 # DDR2 ODT Read Timing (default values) |
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DATA 0xFFD0147C 0x00009663 # DDR2 ODT Write Timing (default values) |
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DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size |
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DATA 0xFFD01508 0x00000000 # CS[1]n Base address to 0x0 |
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DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled |
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DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled |
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DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled |
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DATA 0xFFD01494 0x00120012 # DDR ODT Control (Low) |
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DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) |
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DATA 0xFFD0149C 0x0000E40F # CPU ODT Control |
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DATA 0xFFD01480 0x00000001 # DDR Initialization Control |
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DATA 0xFFD20134 0x66666666 |
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DATA 0xFFD20138 0x66666666 |
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DATA 0xFFD10000 0x01112222 |
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DATA 0xFFD1000C 0x00000000 |
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DATA 0xFFD10104 0x00000000 |
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DATA 0xFFD10100 0x40000000 |
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# End of Header extension |
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DATA 0x0 0x0 |
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@ -1,165 +0,0 @@ |
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/*
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* Copyright (C) 2011 Simon Guinot <sguinot@lacie.com> |
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* |
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* Based on Kirkwood support: |
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* (C) Copyright 2009 |
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* Marvell Semiconductor <www.marvell.com> |
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <command.h> |
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#include <asm/arch/cpu.h> |
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#include <asm/arch/soc.h> |
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#include <asm/arch/mpp.h> |
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#include <asm/arch/gpio.h> |
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#include "../common/common.h" |
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#include "netdev.h" |
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DECLARE_GLOBAL_DATA_PTR; |
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/* GPIO configuration: start FAN at low speed, USB and HDD */ |
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#define WIRELESS_SPACE_OE_LOW 0xFF006808 |
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#define WIRELESS_SPACE_OE_HIGH 0x0000F989 |
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#define WIRELESS_SPACE_OE_VAL_LOW 0x00010080 |
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#define WIRELESS_SPACE_OE_VAL_HIGH 0x00000240 |
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#define WIRELESS_SPACE_REAR_BUTTON 13 |
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#define WIRELESS_SPACE_FRONT_BUTTON 43 |
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const u32 kwmpp_config[] = { |
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MPP0_NF_IO2, |
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MPP1_NF_IO3, |
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MPP2_NF_IO4, |
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MPP3_NF_IO5, |
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MPP4_NF_IO6, |
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MPP5_NF_IO7, |
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MPP6_SYSRST_OUTn, |
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MPP7_GPO, /* Fan speed (bit 1) */ |
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MPP8_TW_SDA, |
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MPP9_TW_SCK, |
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MPP10_UART0_TXD, |
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MPP11_UART0_RXD, |
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MPP13_GPIO, /* Red led */ |
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MPP14_GPIO, /* USB fuse */ |
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MPP15_SATA0_ACTn, |
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MPP16_GPIO, /* SATA 0 power */ |
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MPP17_GPIO, /* SATA 1 power */ |
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MPP18_NF_IO0, |
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MPP19_NF_IO1, |
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MPP20_GE1_0, /* Gigabit Ethernet 1 */ |
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MPP21_GE1_1, |
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MPP22_GE1_2, |
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MPP23_GE1_3, |
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MPP24_GE1_4, |
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MPP25_GE1_5, |
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MPP26_GE1_6, |
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MPP27_GE1_7, |
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MPP28_GE1_8, |
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MPP29_GE1_9, |
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MPP30_GE1_10, |
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MPP31_GE1_11, |
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MPP32_GE1_12, |
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MPP33_GE1_13, |
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MPP34_GE1_14, |
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MPP35_GE1_15, |
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MPP36_GPIO, /* Fan speed (bit 2) */ |
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MPP37_GPIO, /* Fan speed (bit 0) */ |
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MPP38_GPIO, /* Fan power */ |
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MPP39_GPIO, /* Fan rotation fail */ |
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MPP40_GPIO, /* Ethernet switch link */ |
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MPP41_GPIO, /* USB enable host vbus */ |
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MPP42_GPIO, /* LED clock control */ |
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MPP43_GPIO, /* WPS button (0=Pushed, 1=Released) */ |
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MPP44_GPIO, /* Red LED on/off */ |
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MPP45_GPIO, /* Red LED timer blink (on=off=100ms) */ |
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MPP46_GPIO, /* Green LED on/off */ |
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MPP47_GPIO, /* LED (blue, green) SATA activity blink */ |
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MPP48_GPIO, /* Blue LED on/off */ |
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0 |
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}; |
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struct mv88e61xx_config swcfg = { |
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.name = "egiga0", |
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.vlancfg = MV88E61XX_VLANCFG_ROUTER, |
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.rgmii_delay = MV88E61XX_RGMII_DELAY_EN, |
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.led_init = MV88E61XX_LED_INIT_EN, |
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.mdip = MV88E61XX_MDIP_NOCHANGE, |
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.portstate = MV88E61XX_PORTSTT_FORWARDING, |
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.cpuport = 0x20, |
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.ports_enabled = 0x3F, |
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}; |
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int board_early_init_f(void) |
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{ |
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/* Gpio configuration */ |
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mvebu_config_gpio(WIRELESS_SPACE_OE_VAL_LOW, WIRELESS_SPACE_OE_VAL_HIGH, |
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WIRELESS_SPACE_OE_LOW, WIRELESS_SPACE_OE_HIGH); |
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/* Multi-Purpose Pins Functionality configuration */ |
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kirkwood_mpp_conf(kwmpp_config, NULL); |
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return 0; |
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} |
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int board_init(void) |
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{ |
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/* Machine number */ |
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gd->bd->bi_arch_number = CONFIG_MACH_TYPE; |
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/* Boot parameters address */ |
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gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; |
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return 0; |
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} |
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#if defined(CONFIG_MISC_INIT_R) |
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int misc_init_r(void) |
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{ |
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#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR) |
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if (!getenv("ethaddr")) { |
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uchar mac[6]; |
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if (lacie_read_mac_address(mac) == 0) |
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eth_setenv_enetaddr("ethaddr", mac); |
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} |
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#endif |
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return 0; |
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} |
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#endif |
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#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R) |
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/* Configure and initialize PHY */ |
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void reset_phy(void) |
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{ |
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/* configure switch on egiga0 */ |
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mv88e61xx_switch_initialize(&swcfg); |
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} |
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#endif |
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#if defined(CONFIG_KIRKWOOD_GPIO) && defined(CONFIG_WIRELESS_SPACE_CMD) |
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/* Return GPIO button status */ |
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static int |
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do_ws(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
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{ |
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if (strcmp(argv[1], "button") == 0) { |
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if (strcmp(argv[2], "rear") == 0) |
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/* invert GPIO result for intuitive while/until use */ |
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return !kw_gpio_get_value(WIRELESS_SPACE_REAR_BUTTON); |
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else if (strcmp(argv[2], "front") == 0) |
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return kw_gpio_get_value(WIRELESS_SPACE_FRONT_BUTTON); |
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else |
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return -1; |
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} else { |
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return -1; |
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} |
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} |
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U_BOOT_CMD(ws, 3, 0, do_ws, |
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"Return GPIO button status 0=off 1=on", |
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"- ws button rear|front: test buttons' states\n" |
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); |
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#endif |
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@ -1,6 +0,0 @@ |
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CONFIG_ARM=y |
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CONFIG_KIRKWOOD=y |
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CONFIG_TARGET_WIRELESS_SPACE=y |
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# CONFIG_CMD_IMLS is not set |
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# CONFIG_CMD_FLASH is not set |
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# CONFIG_CMD_SETEXPR is not set |
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@ -1,179 +0,0 @@ |
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/*
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* Copyright (C) 2011 Albert ARIBAUD <albert.u.boot@aribaud.net> |
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* |
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* Based on the netspace_v2 code which is |
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* Copyright (C) 2011 Simon Guinot <sguinot@lacie.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef _CONFIG_WIRELESS_SPACE_H |
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#define _CONFIG_WIRELESS_SPACE_H |
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/*
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* Machine number definition |
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*/ |
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#define MACH_TYPE_WIRELESS_SPACE 2500 /* is missing in mach-types.h */ |
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#define CONFIG_MACH_TYPE MACH_TYPE_WIRELESS_SPACE |
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#define CONFIG_IDENT_STRING " Wireless Space" |
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/*
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* High Level Configuration Options (easy to change) |
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*/ |
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#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ |
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/* SoC name */ |
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#define CONFIG_KW88F6281 |
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#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ |
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/*
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* Commands configuration |
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*/ |
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#define CONFIG_SYS_NO_FLASH /* no NOR or SPI flash */ |
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#define CONFIG_CMD_ENV |
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#define CONFIG_CMD_DHCP |
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#define CONFIG_CMD_PING |
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#define CONFIG_CMD_NAND |
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#define CONFIG_CMD_I2C |
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#define CONFIG_CMD_IDE |
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#define CONFIG_CMD_USB |
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/*
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* Core clock definition |
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*/ |
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#define CONFIG_SYS_TCLK 166000000 /* 166MHz */ |
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/*
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* SDRAM configuration |
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*/ |
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#define CONFIG_NR_DRAM_BANKS 1 |
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/*
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* Different SDRAM configuration and size for some of the boards derived |
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* from the Network Space v2 |
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*/ |
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/*
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* mv-common.h should be defined after CMD configs since it used them |
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* to enable certain macros |
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*/ |
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#include "mv-common.h" |
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/* Remove or override few declarations from mv-common.h */ |
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#undef CONFIG_RBTREE |
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#undef CONFIG_SYS_IDE_MAXBUS |
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#undef CONFIG_SYS_IDE_MAXDEVICE |
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#define CONFIG_SYS_IDE_MAXBUS 1 |
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#define CONFIG_SYS_IDE_MAXDEVICE 1 |
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/*
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* Ethernet Driver configuration |
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*/ |
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#ifdef CONFIG_CMD_NET |
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#define CONFIG_MISC_INIT_R /* misc_init_r() initializes MAC address */ |
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#define CONFIG_MVGBE_PORTS {1, 0} /* enable only egiga0... */ |
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#define PORT_SERIAL_CONTROL_VALUE 0x00A4260E /* ... tied to the switch... */ |
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#define CONFIG_PHY_BASE_ADR 0xa /* ... through a 'fake' PHY */ |
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#define CONFIG_MII |
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#undef CONFIG_SYS_FAULT_ECHO_LINK_DOWN |
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#define CONFIG_NETCONSOLE |
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#define CONFIG_MV88E61XX_SWITCH |
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#define CONFIG_MV88E61XX_MULTICHIP_ADRMODE |
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#define CONFIG_MV88E61XX_CMD |
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#define CONFIG_CMD_TFTPPUT |
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#endif /* CONFIG_CMD_NET */ |
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/*
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* SATA Driver configuration |
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*/ |
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#ifdef CONFIG_MVSATA_IDE |
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#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET |
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#endif /* CONFIG_MVSATA_IDE */ |
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/*
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* Enable GPI0 support |
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*/ |
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#define CONFIG_KIRKWOOD_GPIO |
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/*
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* Enable I2C support |
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*/ |
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#ifdef CONFIG_CMD_I2C |
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/* I2C EEPROM HT24LC04 (512B - 32 pages of 16 Bytes) */ |
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#define CONFIG_CMD_EEPROM |
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 |
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16-byte page size */ |
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* 8-bit device address */ |
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#endif /* CONFIG_CMD_I2C */ |
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/*
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* Partition support |
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*/ |
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#define CONFIG_DOS_PARTITION |
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#define CONFIG_EFI_PARTITION |
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/*
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* File systems support |
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*/ |
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#define CONFIG_CMD_EXT2 |
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#define CONFIG_CMD_FAT |
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/*
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* Use the HUSH parser |
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*/ |
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#define CONFIG_SYS_HUSH_PARSER |
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/*
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* Console configuration |
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*/ |
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#define CONFIG_CONSOLE_MUX |
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#define CONFIG_SYS_CONSOLE_IS_IN_ENV |
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/*
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* Enable device tree support |
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*/ |
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#define CONFIG_OF_LIBFDT |
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/*
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* Environment variables configurations |
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*/ |
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#define CONFIG_ENV_IS_IN_NAND |
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#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128KB */ |
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#define CONFIG_ENV_SIZE 0x20000 /* 128KB */ |
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#define CONFIG_ENV_OFFSET 0x80000 /* env starts here */ |
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/*
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* Board-specific command to make using buttons etc easier |
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*/ |
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#define CONFIG_WIRELESS_SPACE_CMD |
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/*
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* Default environment variables |
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*/ |
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#define CONFIG_PREBOOT |
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#define CONFIG_BOOTARGS "console=ttyS0,115200" |
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#define CONFIG_BOOTCOMMAND \ |
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"if run usbload || run diskload; then bootm; fi" |
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#define CONFIG_EXTRA_ENV_SETTINGS \ |
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"stdin=serial\0" \
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"stdout=serial\0" \
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"stderr=serial\0" \
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"bootfile=uImage\0" \
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"loadaddr=0x800000\0" \
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"autoload=no\0" \
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"netconsole=" \
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"set stdin $stdin,nc; " \
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"set stdout $stdout,nc; " \
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"set stderr $stderr,nc;\0" \
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"diskload=ide reset && " \
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"ext2load ide 0:1 $loadaddr /boot/$bootfile\0" \
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"usbload=usb start && " \
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"fatload usb 0:1 $loadaddr /boot/$bootfile\0" \
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"preboot=" \
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"dhcp && run netconsole\0" |
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#endif /* _CONFIG_WIRELESS_SPACE_H */ |
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Reference in new issue