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arm: socfpga: mcvevk: Adding handoff for SDRAM ctrlcfg.extratime1

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Adding new handoff for SDRAM ctrcfg.extratime1 which is
required for stable LPDDR2 operation. Since the board is
using DDR3, the handoff is set to default value 0.

Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
master
Chin Liang See 8 years ago committed by Marek Vasut
parent 0db1ac47ee
commit b38c1d2f6b
1 changed files with 3 additions and 0 deletions
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  1. 3
      board/denx/mcvevk/qts/sdram_config.h

3
board/denx/mcvevk/qts/sdram_config.h
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@ -49,6 +49,9 @@
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 5
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0

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