This patch add support for rockchip dwc3 controller, which corresponding to the two type-C port on rk3399 evb. Only support usb2.0 currently for we have not enable the usb3.0 phy driver and PD(fusb302) driver. Signed-off-by: MengDongyang <daniel.meng@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>master
MengDongyang
8 years ago
committed by
Simon Glass
parent
aa89b554b7
commit
b44566c4ce
@ -0,0 +1,211 @@ |
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/*
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* Copyright (c) 2016 Rockchip, Inc. |
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* Authors: Daniel Meng <daniel.meng@rock-chips.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <dm.h> |
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#include <fdtdec.h> |
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#include <libfdt.h> |
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#include <malloc.h> |
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#include <usb.h> |
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#include <watchdog.h> |
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#include <asm/gpio.h> |
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#include <asm-generic/errno.h> |
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#include <linux/compat.h> |
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#include <linux/usb/dwc3.h> |
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#include "xhci.h" |
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DECLARE_GLOBAL_DATA_PTR; |
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struct rockchip_xhci_platdata { |
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fdt_addr_t hcd_base; |
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fdt_addr_t phy_base; |
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struct gpio_desc vbus_gpio; |
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}; |
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/*
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* Contains pointers to register base addresses |
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* for the usb controller. |
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*/ |
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struct rockchip_xhci { |
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struct usb_platdata usb_plat; |
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struct xhci_ctrl ctrl; |
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struct xhci_hccr *hcd; |
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struct dwc3 *dwc3_reg; |
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}; |
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static int xhci_usb_ofdata_to_platdata(struct udevice *dev) |
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{ |
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struct rockchip_xhci_platdata *plat = dev_get_platdata(dev); |
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struct udevice *child; |
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int ret = 0; |
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/*
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* Get the base address for XHCI controller from the device node |
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*/ |
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plat->hcd_base = dev_get_addr(dev); |
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if (plat->hcd_base == FDT_ADDR_T_NONE) { |
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debug("Can't get the XHCI register base address\n"); |
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return -ENXIO; |
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} |
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/* Get the base address for usbphy from the device node */ |
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for (device_find_first_child(dev, &child); child; |
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device_find_next_child(&child)) { |
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if (!of_device_is_compatible(child, "rockchip,rk3399-usb3-phy")) |
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continue; |
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plat->phy_base = dev_get_addr(child); |
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break; |
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} |
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if (plat->phy_base == FDT_ADDR_T_NONE) { |
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debug("Can't get the usbphy register address\n"); |
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return -ENXIO; |
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} |
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/* Vbus gpio */ |
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ret = gpio_request_by_name(dev, "rockchip,vbus-gpio", 0, |
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&plat->vbus_gpio, GPIOD_IS_OUT); |
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if (ret) |
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debug("rockchip,vbus-gpio node missing!"); |
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return 0; |
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} |
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/*
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* rockchip_dwc3_phy_setup() - Configure USB PHY Interface of DWC3 Core |
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* @dwc: Pointer to our controller context structure |
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* @dev: Pointer to ulcass device |
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*/ |
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static void rockchip_dwc3_phy_setup(struct dwc3 *dwc3_reg, |
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struct udevice *dev) |
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{ |
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u32 reg; |
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const void *blob = gd->fdt_blob; |
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u32 utmi_bits; |
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/* Set dwc3 usb2 phy config */ |
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reg = readl(&dwc3_reg->g_usb2phycfg[0]); |
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if (fdtdec_get_bool(blob, dev->of_offset, |
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"snps,dis-enblslpm-quirk")) |
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reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; |
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utmi_bits = fdtdec_get_int(blob, dev->of_offset, |
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"snps,phyif-utmi-bits", -1); |
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if (utmi_bits == 16) { |
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reg |= DWC3_GUSB2PHYCFG_PHYIF; |
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reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK; |
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reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT; |
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} else if (utmi_bits == 8) { |
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reg &= ~DWC3_GUSB2PHYCFG_PHYIF; |
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reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK; |
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reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_8BIT; |
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} |
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if (fdtdec_get_bool(blob, dev->of_offset, |
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"snps,dis-u2-freeclk-exists-quirk")) |
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reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS; |
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if (fdtdec_get_bool(blob, dev->of_offset, |
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"snps,dis-u2-susphy-quirk")) |
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reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; |
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writel(reg, &dwc3_reg->g_usb2phycfg[0]); |
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} |
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static int rockchip_xhci_core_init(struct rockchip_xhci *rkxhci, |
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struct udevice *dev) |
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{ |
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int ret; |
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ret = dwc3_core_init(rkxhci->dwc3_reg); |
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if (ret) { |
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debug("failed to initialize core\n"); |
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return ret; |
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} |
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rockchip_dwc3_phy_setup(rkxhci->dwc3_reg, dev); |
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/* We are hard-coding DWC3 core to Host Mode */ |
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dwc3_set_mode(rkxhci->dwc3_reg, DWC3_GCTL_PRTCAP_HOST); |
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return 0; |
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} |
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static int rockchip_xhci_core_exit(struct rockchip_xhci *rkxhci) |
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{ |
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return 0; |
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} |
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static int xhci_usb_probe(struct udevice *dev) |
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{ |
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struct rockchip_xhci_platdata *plat = dev_get_platdata(dev); |
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struct rockchip_xhci *ctx = dev_get_priv(dev); |
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struct xhci_hcor *hcor; |
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int ret; |
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ctx->hcd = (struct xhci_hccr *)plat->hcd_base; |
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ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET); |
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hcor = (struct xhci_hcor *)((uint64_t)ctx->hcd + |
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HC_LENGTH(xhci_readl(&ctx->hcd->cr_capbase))); |
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/* setup the Vbus gpio here */ |
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if (dm_gpio_is_valid(&plat->vbus_gpio)) |
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dm_gpio_set_value(&plat->vbus_gpio, 1); |
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ret = rockchip_xhci_core_init(ctx, dev); |
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if (ret) { |
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debug("XHCI: failed to initialize controller\n"); |
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return ret; |
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} |
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return xhci_register(dev, ctx->hcd, hcor); |
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} |
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static int xhci_usb_remove(struct udevice *dev) |
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{ |
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struct rockchip_xhci *ctx = dev_get_priv(dev); |
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int ret; |
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ret = xhci_deregister(dev); |
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if (ret) |
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return ret; |
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ret = rockchip_xhci_core_exit(ctx); |
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if (ret) |
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return ret; |
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return 0; |
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} |
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static const struct udevice_id xhci_usb_ids[] = { |
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{ .compatible = "rockchip,rk3399-xhci" }, |
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{ } |
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}; |
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U_BOOT_DRIVER(usb_xhci) = { |
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.name = "xhci_rockchip", |
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.id = UCLASS_USB, |
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.of_match = xhci_usb_ids, |
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.ofdata_to_platdata = xhci_usb_ofdata_to_platdata, |
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.probe = xhci_usb_probe, |
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.remove = xhci_usb_remove, |
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.ops = &xhci_usb_ops, |
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.bind = dm_scan_fdt_dev, |
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.platdata_auto_alloc_size = sizeof(struct rockchip_xhci_platdata), |
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.priv_auto_alloc_size = sizeof(struct rockchip_xhci), |
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.flags = DM_FLAG_ALLOC_PRIV_DMA, |
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}; |
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static const struct udevice_id usb_phy_ids[] = { |
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{ .compatible = "rockchip,rk3399-usb3-phy" }, |
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{ } |
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}; |
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U_BOOT_DRIVER(usb_phy) = { |
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.name = "usb_phy_rockchip", |
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.of_match = usb_phy_ids, |
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}; |
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