This adds functions to enable/disable clocks and reset to on-chip peripherals. Signed-off-by: Simon Glass <sjg@chromium.org>master
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/*
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* Copyright (c) 2011 The Chromium OS Authors. |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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/* Tegra2 Clock control functions */ |
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#include <asm/io.h> |
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#include <asm/arch/clk_rst.h> |
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#include <asm/arch/clock.h> |
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#include <asm/arch/timer.h> |
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#include <asm/arch/tegra2.h> |
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#include <common.h> |
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#ifdef DEBUG |
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#define assert(x) \ |
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({ if (!(x)) printf("Assertion failure '%s' %s line %d\n", \
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#x, __FILE__, __LINE__); }) |
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#else |
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#define assert(x) |
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#endif |
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/*
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* Get the oscillator frequency, from the corresponding hardware configuration |
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* field. |
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*/ |
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enum clock_osc_freq clock_get_osc_freq(void) |
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{ |
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struct clk_rst_ctlr *clkrst = |
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(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; |
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u32 reg; |
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reg = readl(&clkrst->crc_osc_ctrl); |
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return (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT; |
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} |
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unsigned long clock_start_pll(enum clock_pll_id clkid, u32 divm, u32 divn, |
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u32 divp, u32 cpcon, u32 lfcon) |
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{ |
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struct clk_rst_ctlr *clkrst = |
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(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; |
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u32 data; |
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struct clk_pll *pll; |
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assert(clock_pll_id_isvalid(clkid)); |
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pll = &clkrst->crc_pll[clkid]; |
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/*
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* We cheat by treating all PLL (except PLLU) in the same fashion. |
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* This works only because: |
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* - same fields are always mapped at same offsets, except DCCON |
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* - DCCON is always 0, doesn't conflict |
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* - M,N, P of PLLP values are ignored for PLLP |
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*/ |
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data = (cpcon << PLL_CPCON_SHIFT) | (lfcon << PLL_LFCON_SHIFT); |
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writel(data, &pll->pll_misc); |
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data = (divm << PLL_DIVM_SHIFT) | (divn << PLL_DIVN_SHIFT) | |
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(0 << PLL_BYPASS_SHIFT) | (1 << PLL_ENABLE_SHIFT); |
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if (clkid == CLOCK_PLL_ID_USB) |
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data |= divp << PLLU_VCO_FREQ_SHIFT; |
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else |
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data |= divp << PLL_DIVP_SHIFT; |
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writel(data, &pll->pll_base); |
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/* calculate the stable time */ |
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return timer_get_us() + CLOCK_PLL_STABLE_DELAY_US; |
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} |
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void clock_set_enable(enum periph_id periph_id, int enable) |
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{ |
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struct clk_rst_ctlr *clkrst = |
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(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; |
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u32 *clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)]; |
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u32 reg; |
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/* Enable/disable the clock to this peripheral */ |
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assert(clock_periph_id_isvalid(periph_id)); |
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reg = readl(clk); |
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if (enable) |
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reg |= PERIPH_MASK(periph_id); |
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else |
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reg &= ~PERIPH_MASK(periph_id); |
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writel(reg, clk); |
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} |
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void clock_enable(enum periph_id clkid) |
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{ |
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clock_set_enable(clkid, 1); |
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} |
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void clock_disable(enum periph_id clkid) |
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{ |
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clock_set_enable(clkid, 0); |
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} |
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void reset_set_enable(enum periph_id periph_id, int enable) |
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{ |
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struct clk_rst_ctlr *clkrst = |
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(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; |
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u32 *reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)]; |
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u32 reg; |
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/* Enable/disable reset to the peripheral */ |
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assert(clock_periph_id_isvalid(periph_id)); |
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reg = readl(reset); |
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if (enable) |
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reg |= PERIPH_MASK(periph_id); |
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else |
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reg &= ~PERIPH_MASK(periph_id); |
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writel(reg, reset); |
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} |
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void reset_periph(enum periph_id periph_id, int us_delay) |
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{ |
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/* Put peripheral into reset */ |
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reset_set_enable(periph_id, 1); |
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udelay(us_delay); |
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/* Remove reset */ |
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reset_set_enable(periph_id, 0); |
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udelay(us_delay); |
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} |
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void reset_cmplx_set_enable(int cpu, int which, int reset) |
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{ |
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struct clk_rst_ctlr *clkrst = |
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(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; |
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u32 mask; |
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/* Form the mask, which depends on the cpu chosen. Tegra2 has 2 */ |
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assert(cpu >= 0 && cpu < 2); |
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mask = which << cpu; |
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/* either enable or disable those reset for that CPU */ |
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if (reset) |
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writel(mask, &clkrst->crc_cpu_cmplx_set); |
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else |
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writel(mask, &clkrst->crc_cpu_cmplx_clr); |
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} |
@ -0,0 +1,263 @@ |
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/*
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* Copyright (c) 2011 The Chromium OS Authors. |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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/* Tegra2 clock control functions */ |
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#ifndef _CLOCK_H |
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/* Set of oscillator frequencies supported in the internal API. */ |
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enum clock_osc_freq { |
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/* All in MHz, so 13_0 is 13.0MHz */ |
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CLOCK_OSC_FREQ_13_0, |
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CLOCK_OSC_FREQ_19_2, |
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CLOCK_OSC_FREQ_12_0, |
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CLOCK_OSC_FREQ_26_0, |
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CLOCK_OSC_FREQ_COUNT, |
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}; |
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/* The PLLs supported by the hardware */ |
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enum clock_pll_id { |
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CLOCK_PLL_ID_FIRST, |
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CLOCK_PLL_ID_CGENERAL = CLOCK_PLL_ID_FIRST, |
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CLOCK_PLL_ID_MEMORY, |
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CLOCK_PLL_ID_PERIPH, |
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CLOCK_PLL_ID_AUDIO, |
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CLOCK_PLL_ID_USB, |
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CLOCK_PLL_ID_DISPLAY, |
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/* now the simple ones */ |
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CLOCK_PLL_ID_FIRST_SIMPLE, |
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CLOCK_PLL_ID_XCPU = CLOCK_PLL_ID_FIRST_SIMPLE, |
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CLOCK_PLL_ID_EPCI, |
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CLOCK_PLL_ID_SFROM32KHZ, |
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CLOCK_PLL_ID_COUNT, |
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}; |
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/* The clocks supported by the hardware */ |
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enum periph_id { |
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PERIPH_ID_FIRST, |
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/* Low word: 31:0 */ |
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PERIPH_ID_CPU = PERIPH_ID_FIRST, |
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PERIPH_ID_RESERVED1, |
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PERIPH_ID_RESERVED2, |
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PERIPH_ID_AC97, |
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PERIPH_ID_RTC, |
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PERIPH_ID_TMR, |
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PERIPH_ID_UART1, |
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PERIPH_ID_UART2, |
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/* 8 */ |
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PERIPH_ID_GPIO, |
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PERIPH_ID_SDMMC2, |
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PERIPH_ID_SPDIF, |
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PERIPH_ID_I2S1, |
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PERIPH_ID_I2C1, |
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PERIPH_ID_NDFLASH, |
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PERIPH_ID_SDMMC1, |
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PERIPH_ID_SDMMC4, |
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/* 16 */ |
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PERIPH_ID_TWC, |
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PERIPH_ID_PWC, |
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PERIPH_ID_I2S2, |
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PERIPH_ID_EPP, |
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PERIPH_ID_VI, |
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PERIPH_ID_2D, |
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PERIPH_ID_USBD, |
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PERIPH_ID_ISP, |
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/* 24 */ |
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PERIPH_ID_3D, |
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PERIPH_ID_IDE, |
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PERIPH_ID_DISP2, |
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PERIPH_ID_DISP1, |
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PERIPH_ID_HOST1X, |
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PERIPH_ID_VCP, |
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PERIPH_ID_RESERVED30, |
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PERIPH_ID_CACHE2, |
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/* Middle word: 63:32 */ |
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PERIPH_ID_MEM, |
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PERIPH_ID_AHBDMA, |
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PERIPH_ID_APBDMA, |
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PERIPH_ID_RESERVED35, |
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PERIPH_ID_KBC, |
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PERIPH_ID_STAT_MON, |
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PERIPH_ID_PMC, |
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PERIPH_ID_FUSE, |
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/* 40 */ |
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PERIPH_ID_KFUSE, |
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PERIPH_ID_SBC1, |
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PERIPH_ID_SNOR, |
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PERIPH_ID_SPI1, |
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PERIPH_ID_SBC2, |
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PERIPH_ID_XIO, |
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PERIPH_ID_SBC3, |
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PERIPH_ID_DVC_I2C, |
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/* 48 */ |
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PERIPH_ID_DSI, |
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PERIPH_ID_TVO, |
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PERIPH_ID_MIPI, |
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PERIPH_ID_HDMI, |
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PERIPH_ID_CSI, |
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PERIPH_ID_TVDAC, |
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PERIPH_ID_I2C2, |
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PERIPH_ID_UART3, |
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/* 56 */ |
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PERIPH_ID_RESERVED56, |
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PERIPH_ID_EMC, |
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PERIPH_ID_USB2, |
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PERIPH_ID_USB3, |
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PERIPH_ID_MPE, |
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PERIPH_ID_VDE, |
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PERIPH_ID_BSEA, |
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PERIPH_ID_BSEV, |
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/* Upper word 95:64 */ |
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PERIPH_ID_SPEEDO, |
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PERIPH_ID_UART4, |
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PERIPH_ID_UART5, |
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PERIPH_ID_I2C3, |
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PERIPH_ID_SBC4, |
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PERIPH_ID_SDMMC3, |
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PERIPH_ID_PCIE, |
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PERIPH_ID_OWR, |
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/* 72 */ |
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PERIPH_ID_AFI, |
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PERIPH_ID_CORESIGHT, |
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PERIPH_ID_RESERVED74, |
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PERIPH_ID_AVPUCQ, |
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PERIPH_ID_RESERVED76, |
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PERIPH_ID_RESERVED77, |
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PERIPH_ID_RESERVED78, |
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PERIPH_ID_RESERVED79, |
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/* 80 */ |
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PERIPH_ID_RESERVED80, |
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PERIPH_ID_RESERVED81, |
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PERIPH_ID_RESERVED82, |
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PERIPH_ID_RESERVED83, |
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PERIPH_ID_IRAMA, |
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PERIPH_ID_IRAMB, |
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PERIPH_ID_IRAMC, |
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PERIPH_ID_IRAMD, |
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/* 88 */ |
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PERIPH_ID_CRAM2, |
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PERIPH_ID_COUNT, |
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}; |
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/* Converts a clock number to a clock register: 0=L, 1=H, 2=U */ |
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#define PERIPH_REG(id) ((id) >> 5) |
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/* Mask value for a clock (within PERIPH_REG(id)) */ |
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#define PERIPH_MASK(id) (1 << ((id) & 0x1f)) |
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/* return 1 if a PLL ID is in range */ |
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#define clock_pll_id_isvalid(id) ((id) >= CLOCK_PLL_ID_FIRST && \ |
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(id) < CLOCK_PLL_ID_COUNT) |
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/* return 1 if a peripheral ID is in range */ |
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#define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \ |
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(id) < PERIPH_ID_COUNT) |
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/* PLL stabilization delay in usec */ |
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#define CLOCK_PLL_STABLE_DELAY_US 300 |
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/* return the current oscillator clock frequency */ |
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enum clock_osc_freq clock_get_osc_freq(void); |
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/*
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* Start PLL using the provided configuration parameters. |
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* |
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* @param id clock id |
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* @param divm input divider |
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* @param divn feedback divider |
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* @param divp post divider 2^n |
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* @param cpcon charge pump setup control |
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* @param lfcon loop filter setup control |
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* |
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* @returns monotonic time in us that the PLL will be stable |
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*/ |
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unsigned long clock_start_pll(enum clock_pll_id id, u32 divm, u32 divn, |
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u32 divp, u32 cpcon, u32 lfcon); |
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/*
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* Enable a clock |
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* |
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* @param id clock id |
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*/ |
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void clock_enable(enum periph_id clkid); |
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/*
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* Set whether a clock is enabled or disabled. |
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* |
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* @param id clock id |
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* @param enable 1 to enable, 0 to disable |
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*/ |
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void clock_set_enable(enum periph_id clkid, int enable); |
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/*
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* Reset a peripheral. This puts it in reset, waits for a delay, then takes |
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* it out of reset and waits for th delay again. |
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* |
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* @param periph_id peripheral to reset |
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* @param us_delay time to delay in microseconds |
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*/ |
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void reset_periph(enum periph_id periph_id, int us_delay); |
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/*
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* Put a peripheral into or out of reset. |
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* |
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* @param periph_id peripheral to reset |
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* @param enable 1 to put into reset, 0 to take out of reset |
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*/ |
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void reset_set_enable(enum periph_id periph_id, int enable); |
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/* CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET/CLR_0 */ |
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enum crc_reset_id { |
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/* Things we can hold in reset for each CPU */ |
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crc_rst_cpu = 1, |
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crc_rst_de = 1 << 2, /* What is de? */ |
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crc_rst_watchdog = 1 << 3, |
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crc_rst_debug = 1 << 4, |
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}; |
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/*
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* Put parts of the CPU complex into or out of reset.\
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* |
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* @param cpu cpu number (0 or 1 on Tegra2) |
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* @param which which parts of the complex to affect (OR of crc_reset_id) |
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* @param reset 1 to assert reset, 0 to de-assert |
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*/ |
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void reset_cmplx_set_enable(int cpu, int which, int reset); |
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#endif |
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