The LS1046A processor is built on the QorIQ LS series architecture combining four ARM A72 processor cores with DPAA 1.0 support. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Mihai Bantea <mihai.bantea@freescale.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>master
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/*
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* Copyright 2016 Freescale Semiconductor, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/arch/fsl_serdes.h> |
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#include <asm/arch/immap_lsch2.h> |
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struct serdes_config { |
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u32 protocol; |
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u8 lanes[SRDS_MAX_LANES]; |
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}; |
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static struct serdes_config serdes1_cfg_tbl[] = { |
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/* SerDes 1 */ |
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{0x3333, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC5, |
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SGMII_FM1_DTSEC6} }, |
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{0x1133, {XFI_FM1_MAC9, XFI_FM1_MAC10, SGMII_FM1_DTSEC5, |
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SGMII_FM1_DTSEC6} }, |
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{0x1333, {XFI_FM1_MAC9, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC5, |
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SGMII_FM1_DTSEC6} }, |
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{0x2333, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC5, |
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SGMII_FM1_DTSEC6} }, |
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{0x2233, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10, |
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SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, |
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{0x1040, {XFI_FM1_MAC9, NONE, QSGMII_FM1_A, NONE} }, |
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{0x2040, {SGMII_2500_FM1_DTSEC9, NONE, QSGMII_FM1_A, NONE} }, |
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{0x1163, {XFI_FM1_MAC9, XFI_FM1_MAC10, PCIE1, SGMII_FM1_DTSEC6} }, |
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{0x2263, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10, PCIE1, |
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SGMII_FM1_DTSEC6} }, |
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{0x3363, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, PCIE1, |
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SGMII_FM1_DTSEC6} }, |
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{0x2223, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10, |
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SGMII_2500_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, |
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{} |
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}; |
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static struct serdes_config serdes2_cfg_tbl[] = { |
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/* SerDes 2 */ |
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{0x8888, {PCIE1, PCIE1, PCIE1, PCIE1} }, |
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{0x5559, {PCIE1, PCIE2, PCIE3, SATA1} }, |
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{0x5577, {PCIE1, PCIE2, PCIE3, PCIE3} }, |
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{0x5506, {PCIE1, PCIE2, NONE, PCIE3} }, |
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{0x0506, {NONE, PCIE2, NONE, PCIE3} }, |
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{0x0559, {NONE, PCIE2, PCIE3, SATA1} }, |
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{0x5A59, {PCIE1, SGMII_FM1_DTSEC2, PCIE3, SATA1} }, |
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{0x5A06, {PCIE1, SGMII_FM1_DTSEC2, NONE, PCIE3} }, |
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{} |
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}; |
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static struct serdes_config *serdes_cfg_tbl[] = { |
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serdes1_cfg_tbl, |
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serdes2_cfg_tbl, |
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}; |
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enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) |
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{ |
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struct serdes_config *ptr; |
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if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) |
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return 0; |
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ptr = serdes_cfg_tbl[serdes]; |
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while (ptr->protocol) { |
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if (ptr->protocol == cfg) |
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return ptr->lanes[lane]; |
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ptr++; |
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} |
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return 0; |
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} |
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int is_serdes_prtcl_valid(int serdes, u32 prtcl) |
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{ |
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int i; |
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struct serdes_config *ptr; |
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if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) |
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return 0; |
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ptr = serdes_cfg_tbl[serdes]; |
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while (ptr->protocol) { |
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if (ptr->protocol == prtcl) |
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break; |
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ptr++; |
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} |
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if (!ptr->protocol) |
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return 0; |
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for (i = 0; i < SRDS_MAX_LANES; i++) { |
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if (ptr->lanes[i] != NONE) |
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return 1; |
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} |
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return 0; |
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} |
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