Tom Rini
11 years ago
commit
b71bf4add6
@ -0,0 +1,11 @@ |
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#
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# (C) Copyright 2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# (C) Copyright 2013
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# Heiko Schocher, DENX Software Engineering, <hs@denx.de>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y = ids8313.o
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@ -0,0 +1,208 @@ |
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/*
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* (C) Copyright 2013 |
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* Heiko Schocher, DENX Software Engineering, hs@denx.de. |
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* |
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* Based on: |
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* Copyright (c) 2011 IDS GmbH, Germany |
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* ids8313.c - ids8313 board support. |
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* |
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* Sergej Stepanov <ste@ids.de> |
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* Based on board/freescale/mpc8313erdb/mpc8313erdb.c |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <mpc83xx.h> |
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#include <spi.h> |
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#include <libfdt.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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/** CPLD contains the info about:
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* - board type: *pCpld & 0xF0 |
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* - hw-revision: *pCpld & 0x0F |
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* - cpld-revision: *pCpld+1 |
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*/ |
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int checkboard(void) |
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{ |
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char *pcpld = (char *)CONFIG_SYS_CPLD_BASE; |
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u8 u8Vers = readb(pcpld); |
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u8 u8Revs = readb(pcpld + 1); |
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printf("Board: "); |
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switch (u8Vers & 0xF0) { |
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case '\x40': |
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printf("CU73X"); |
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break; |
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case '\x50': |
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printf("CC73X"); |
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break; |
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default: |
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printf("unknown(0x%02X, 0x%02X)\n", u8Vers, u8Revs); |
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return 0; |
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} |
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printf("\nInfo: HW-Rev: %i, CPLD-Rev: %i\n", |
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u8Vers & 0x0F, u8Revs & 0xFF); |
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return 0; |
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} |
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/*
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* fixed sdram init |
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*/ |
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int fixed_sdram(unsigned long config) |
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{ |
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immap_t *im = (immap_t *)CONFIG_SYS_IMMR; |
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u32 msize = CONFIG_SYS_DDR_SIZE << 20; |
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#ifndef CONFIG_SYS_RAMBOOT |
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u32 msize_log2 = __ilog2(msize); |
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out_be32(&im->sysconf.ddrlaw[0].bar, |
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(CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000)); |
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out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1)); |
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out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE); |
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sync(); |
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/*
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* Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg], |
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* or the DDR2 controller may fail to initialize correctly. |
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*/ |
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udelay(50000); |
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out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24); |
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out_be32(&im->ddr.cs_config[0], config); |
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/* currently we use only one CS, so disable the other banks */ |
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out_be32(&im->ddr.cs_config[1], 0); |
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out_be32(&im->ddr.cs_config[2], 0); |
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out_be32(&im->ddr.cs_config[3], 0); |
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out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); |
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out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); |
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out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); |
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out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); |
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out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_SDRAM_CFG); |
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out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_SDRAM_CFG2); |
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out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE); |
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out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE_2); |
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out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL); |
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out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL); |
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sync(); |
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udelay(300); |
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/* enable DDR controller */ |
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setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); |
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/* now check the real size */ |
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disable_addr_trans(); |
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msize = get_ram_size(CONFIG_SYS_DDR_BASE, msize); |
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enable_addr_trans(); |
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#endif |
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return msize; |
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} |
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static int setup_sdram(void) |
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{ |
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u32 msize = CONFIG_SYS_DDR_SIZE << 20; |
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long int size_01, size_02; |
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size_01 = fixed_sdram(CONFIG_SYS_DDR_CONFIG); |
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size_02 = fixed_sdram(CONFIG_SYS_DDR_CONFIG_256); |
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if (size_01 > size_02) |
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msize = fixed_sdram(CONFIG_SYS_DDR_CONFIG); |
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else |
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msize = size_02; |
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return msize; |
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} |
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phys_size_t initdram(int board_type) |
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{ |
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immap_t *im = (immap_t *)CONFIG_SYS_IMMR; |
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fsl_lbc_t *lbc = &im->im_lbc; |
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u32 msize = 0; |
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if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im) |
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return -1; |
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msize = setup_sdram(); |
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out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR); |
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out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR); |
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sync(); |
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return msize; |
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} |
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#if defined(CONFIG_OF_BOARD_SETUP) |
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void ft_board_setup(void *blob, bd_t *bd) |
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{ |
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ft_cpu_setup(blob, bd); |
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} |
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#endif |
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/* gpio mask for spi_cs */ |
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#define IDSCPLD_SPI_CS_MASK 0x00000001 |
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/* spi_cs multiplexed through cpld */ |
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#define IDSCPLD_SPI_CS_BASE (CONFIG_SYS_CPLD_BASE + 0xf) |
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#if defined(CONFIG_MISC_INIT_R) |
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/* srp umcr mask for rts */ |
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#define IDSUMCR_RTS_MASK 0x04 |
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int misc_init_r(void) |
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{ |
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/*srp*/ |
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duart83xx_t *uart1 = &((immap_t *)CONFIG_SYS_IMMR)->duart[0]; |
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duart83xx_t *uart2 = &((immap_t *)CONFIG_SYS_IMMR)->duart[1]; |
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gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0]; |
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u8 *spi_base = (u8 *)IDSCPLD_SPI_CS_BASE; |
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/* deactivate spi_cs channels */ |
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out_8(spi_base, 0); |
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/* deactivate the spi_cs */ |
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setbits_be32(&iopd->dir, IDSCPLD_SPI_CS_MASK); |
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/*srp - deactivate rts*/ |
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out_8(&uart1->umcr, IDSUMCR_RTS_MASK); |
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out_8(&uart2->umcr, IDSUMCR_RTS_MASK); |
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gd->fdt_blob = (void *)CONFIG_SYS_FLASH_BASE; |
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return 0; |
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} |
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#endif |
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#ifdef CONFIG_MPC8XXX_SPI |
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/*
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* The following are used to control the SPI chip selects |
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*/ |
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int spi_cs_is_valid(unsigned int bus, unsigned int cs) |
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{ |
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return bus == 0 && ((cs >= 0) && (cs <= 2)); |
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} |
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void spi_cs_activate(struct spi_slave *slave) |
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{ |
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gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0]; |
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u8 *spi_base = (u8 *)IDSCPLD_SPI_CS_BASE; |
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/* select the spi_cs channel */ |
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out_8(spi_base, 1 << slave->cs); |
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/* activate the spi_cs */ |
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clrbits_be32(&iopd->dat, IDSCPLD_SPI_CS_MASK); |
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} |
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void spi_cs_deactivate(struct spi_slave *slave) |
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{ |
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gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0]; |
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u8 *spi_base = (u8 *)IDSCPLD_SPI_CS_BASE; |
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/* select the spi_cs channel */ |
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out_8(spi_base, 1 << slave->cs); |
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/* deactivate the spi_cs */ |
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setbits_be32(&iopd->dat, IDSCPLD_SPI_CS_MASK); |
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} |
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#endif /* CONFIG_HARD_SPI */ |
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@ -0,0 +1,587 @@ |
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/*
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* (C) Copyright 2013 |
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* Heiko Schocher, DENX Software Engineering, hs@denx.de. |
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* |
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* Based on: |
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* Copyright (c) 2011 IDS GmbH, Germany |
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* Sergej Stepanov <ste@ids.de> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef __CONFIG_H |
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#define __CONFIG_H |
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/*
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* High Level Configuration Options |
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*/ |
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#define CONFIG_MPC831x |
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#define CONFIG_MPC8313 |
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#define CONFIG_IDS8313 |
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#define CONFIG_FSL_ELBC |
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#define CONFIG_MISC_INIT_R |
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#define CONFIG_AUTOBOOT_KEYED |
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#define CONFIG_AUTOBOOT_PROMPT \ |
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"\nEnter password - autoboot in %d seconds...\n", CONFIG_BOOTDELAY |
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#define CONFIG_AUTOBOOT_DELAY_STR "ids" |
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#define CONFIG_BOOT_RETRY_TIME 900 |
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#define CONFIG_BOOT_RETRY_MIN 30 |
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#define CONFIG_BOOTDELAY 1 |
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#define CONFIG_RESET_TO_RETRY |
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#define CONFIG_83XX_CLKIN 66000000 /* in Hz */ |
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#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN |
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#define CONFIG_SYS_IMMR 0xF0000000 |
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#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ |
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#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ |
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/*
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* Hardware Reset Configuration Word |
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* if CLKIN is 66.000MHz, then |
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* CSB = 132MHz, CORE = 264MHz, DDRC = 264MHz, LBC = 132MHz |
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*/ |
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#define CONFIG_SYS_HRCW_LOW (0x20000000 /* reserved, must be set */ |\ |
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HRCWL_DDR_TO_SCB_CLK_2X1 |\
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HRCWL_CSB_TO_CLKIN_2X1 |\
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HRCWL_CORE_TO_CSB_2X1) |
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#define CONFIG_SYS_HRCW_HIGH (HRCWH_PCI_HOST |\ |
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HRCWH_CORE_ENABLE |\
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HRCWH_FROM_0XFFF00100 |\
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HRCWH_BOOTSEQ_DISABLE |\
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HRCWH_SW_WATCHDOG_DISABLE |\
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HRCWH_ROM_LOC_LOCAL_8BIT |\
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HRCWH_RL_EXT_LEGACY |\
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HRCWH_TSEC1M_IN_MII |\
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HRCWH_TSEC2M_IN_MII |\
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HRCWH_BIG_ENDIAN) |
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#define CONFIG_SYS_SICRH 0x00000000 |
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#define CONFIG_SYS_SICRL (SICRL_LBC | SICRL_SPI_D) |
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#define CONFIG_HWCONFIG |
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#define CONFIG_SYS_HID0_INIT 0x000000000 |
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#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK |\ |
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HID0_ENABLE_INSTRUCTION_CACHE |\
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HID0_DISABLE_DYNAMIC_POWER_MANAGMENT) |
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#define CONFIG_SYS_HID2 (HID2_HBE | 0x00020000) |
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/*
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* Definitions for initial stack pointer and data area (in DCACHE ) |
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*/ |
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#define CONFIG_SYS_INIT_RAM_LOCK |
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#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 |
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#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in DPRAM */ |
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#define CONFIG_SYS_GBL_DATA_SIZE 0x100 |
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ |
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- CONFIG_SYS_GBL_DATA_SIZE) |
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
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/*
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* Local Bus LCRR and LBCR regs |
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*/ |
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#define CONFIG_SYS_LCRR_EADC LCRR_EADC_1 |
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#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 |
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#define CONFIG_SYS_LBC_LBCR (0x00040000 |\ |
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(0xFF << LBCR_BMT_SHIFT) |\
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0xF) |
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#define CONFIG_SYS_LBC_MRTPR 0x20000000 |
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/*
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* Internal Definitions |
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*/ |
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/*
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* DDR Setup |
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*/ |
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#define CONFIG_SYS_DDR_BASE 0x00000000 |
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE |
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#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE |
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/*
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* Manually set up DDR parameters, |
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* as this board has not the SPD connected to I2C. |
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*/ |
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#define CONFIG_SYS_DDR_SIZE 256 /* MB */ |
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#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN |\ |
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0x00010000 |\
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CSCONFIG_ROW_BIT_13 |\
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CSCONFIG_COL_BIT_10) |
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#define CONFIG_SYS_DDR_CONFIG_256 (CONFIG_SYS_DDR_CONFIG | \ |
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CSCONFIG_BANK_BIT_3) |
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#define CONFIG_SYS_DDR_TIMING_3 (1 << 16) /* ext refrec */ |
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#define CONFIG_SYS_DDR_TIMING_0 ((3 << TIMING_CFG0_RWT_SHIFT) |\ |
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(3 << TIMING_CFG0_WRT_SHIFT) |\
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(3 << TIMING_CFG0_RRT_SHIFT) |\
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(3 << TIMING_CFG0_WWT_SHIFT) |\
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(6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) |\
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(2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) |\
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(8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
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(2 << TIMING_CFG0_MRS_CYC_SHIFT)) |
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#define CONFIG_SYS_DDR_TIMING_1 ((4 << TIMING_CFG1_PRETOACT_SHIFT) |\ |
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(12 << TIMING_CFG1_ACTTOPRE_SHIFT) |\
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(4 << TIMING_CFG1_ACTTORW_SHIFT) |\
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(7 << TIMING_CFG1_CASLAT_SHIFT) |\
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(4 << TIMING_CFG1_REFREC_SHIFT) |\
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(4 << TIMING_CFG1_WRREC_SHIFT) |\
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(2 << TIMING_CFG1_ACTTOACT_SHIFT) |\
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(2 << TIMING_CFG1_WRTORD_SHIFT)) |
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#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) |\ |
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(5 << TIMING_CFG2_CPO_SHIFT) |\
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(4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) |\
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(2 << TIMING_CFG2_RD_TO_PRE_SHIFT) |\
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(0 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) |\
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(1 << TIMING_CFG2_CKE_PLS_SHIFT) |\
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(6 << TIMING_CFG2_FOUR_ACT_SHIFT)) |
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#define CONFIG_SYS_DDR_INTERVAL ((0x800 << SDRAM_INTERVAL_REFINT_SHIFT) |\ |
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(0x800 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) |
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#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN |\ |
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SDRAM_CFG_2T_EN | SDRAM_CFG_HSE |\
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SDRAM_CFG_DBW_32 |\
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SDRAM_CFG_SDRAM_TYPE_DDR2) |
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#define CONFIG_SYS_SDRAM_CFG2 0x00401000 |
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#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) |\ |
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(0x0242 << SDRAM_MODE_SD_SHIFT)) |
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#define CONFIG_SYS_DDR_MODE_2 0x00000000 |
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#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075 |
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#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN |\ |
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DDRCDR_PZ_NOMZ |\
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DDRCDR_NZ_NOMZ |\
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DDRCDR_ODT |\
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DDRCDR_M_ODR |\
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DDRCDR_Q_DRN) |
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/*
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* on-board devices |
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*/ |
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#define CONFIG_TSEC1 |
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#define CONFIG_TSEC2 |
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#define CONFIG_TSEC_ENET |
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#define CONFIG_NET_MULTI |
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#define CONFIG_HARD_SPI |
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#define CONFIG_HARD_I2C |
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/*
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* NOR FLASH setup |
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*/ |
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#define CONFIG_SYS_FLASH_CFI |
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#define CONFIG_FLASH_CFI_DRIVER |
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#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT |
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#define CONFIG_FLASH_SHOW_PROGRESS 50 |
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
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#define CONFIG_SYS_FLASH_BASE 0xFF800000 |
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#define CONFIG_SYS_FLASH_SIZE 8 |
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#define CONFIG_SYS_FLASH_PROTECTION |
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#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE |
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#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 |
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#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE |\ |
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BR_PS_8 |\
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BR_MS_GPCM |\
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BR_V) |
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#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ |
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OR_GPCM_SCY_10 |\
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OR_GPCM_EHTR |\
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OR_GPCM_TRLX |\
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OR_GPCM_CSNT |\
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OR_GPCM_EAD) |
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 |
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#define CONFIG_SYS_MAX_FLASH_SECT 128 |
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#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 |
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 |
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/*
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* NAND FLASH setup |
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*/ |
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#define CONFIG_SYS_NAND_BASE 0xE1000000 |
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#define CONFIG_SYS_MAX_NAND_DEVICE 1 |
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#define CONFIG_SYS_NAND_MAX_CHIPS 1 |
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#define CONFIG_MTD_NAND_VERIFY_WRITE |
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#define CONFIG_NAND_FSL_ELBC |
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#define CONFIG_SYS_NAND_PAGE_SIZE (2048) |
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#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) |
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#define NAND_CACHE_PAGES 64 |
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#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE |
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#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E |
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#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM |
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#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM |
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|
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#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_NAND_BASE) |\ |
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(2<<BR_DECC_SHIFT) |\
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BR_PS_8 |\
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BR_MS_FCM |\
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BR_V) |
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|
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#define CONFIG_SYS_OR1_PRELIM (0xFFFF8000 |\ |
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OR_FCM_PGS |\
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OR_FCM_CSCT |\
|
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OR_FCM_CST |\
|
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OR_FCM_CHT |\
|
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OR_FCM_SCY_4 |\
|
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OR_FCM_TRLX |\
|
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OR_FCM_EHTR |\
|
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OR_FCM_RST) |
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|
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/*
|
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* MRAM setup |
||||
*/ |
||||
#define CONFIG_SYS_MRAM_BASE 0xE2000000 |
||||
#define CONFIG_SYS_MRAM_SIZE 0x20000 /* 128 Kb */ |
||||
#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_MRAM_BASE |
||||
#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000010 /* 128 Kb */ |
||||
|
||||
#define CONFIG_SYS_OR_TIMING_MRAM |
||||
|
||||
#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_MRAM_BASE |\ |
||||
BR_PS_8 |\
|
||||
BR_MS_GPCM |\
|
||||
BR_V) |
||||
|
||||
#define CONFIG_SYS_OR2_PRELIM 0xFFFE0C74 |
||||
|
||||
/*
|
||||
* CPLD setup |
||||
*/ |
||||
#define CONFIG_SYS_CPLD_BASE 0xE3000000 |
||||
#define CONFIG_SYS_CPLD_SIZE 0x8000 |
||||
#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_CPLD_BASE |
||||
#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000E |
||||
|
||||
#define CONFIG_SYS_OR_TIMING_MRAM |
||||
|
||||
#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CPLD_BASE |\ |
||||
BR_PS_8 |\
|
||||
BR_MS_GPCM |\
|
||||
BR_V) |
||||
|
||||
#define CONFIG_SYS_OR3_PRELIM 0xFFFF8814 |
||||
|
||||
/*
|
||||
* HW-Watchdog |
||||
*/ |
||||
#define CONFIG_WATCHDOG 1 |
||||
#define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF |
||||
|
||||
/*
|
||||
* I2C setup |
||||
*/ |
||||
#define CONFIG_CMD_I2C |
||||
#define CONFIG_SYS_I2C |
||||
#define CONFIG_SYS_I2C_FSL |
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000 |
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F |
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3100 |
||||
#define CONFIG_RTC_PCF8563 |
||||
#define CONFIG_SYS_I2C_RTC_ADDR 0x51 |
||||
|
||||
/*
|
||||
* SPI setup |
||||
*/ |
||||
#ifdef CONFIG_HARD_SPI |
||||
#define CONFIG_MPC8XXX_SPI |
||||
#define CONFIG_CMD_SPI |
||||
#define CONFIG_SYS_GPIO1_PRELIM |
||||
#define CONFIG_SYS_GPIO1_DIR 0x00000001 |
||||
#define CONFIG_SYS_GPIO1_DAT 0x00000001 |
||||
#endif |
||||
|
||||
/*
|
||||
* Ethernet setup |
||||
*/ |
||||
#ifdef CONFIG_TSEC1 |
||||
#define CONFIG_HAS_ETH0 |
||||
#define CONFIG_TSEC1_NAME "TSEC0" |
||||
#define CONFIG_SYS_TSEC1_OFFSET 0x24000 |
||||
#define TSEC1_PHY_ADDR 0x1 |
||||
#define TSEC1_FLAGS TSEC_GIGABIT |
||||
#define TSEC1_PHYIDX 0 |
||||
#endif |
||||
|
||||
#ifdef CONFIG_TSEC2 |
||||
#define CONFIG_HAS_ETH1 |
||||
#define CONFIG_TSEC2_NAME "TSEC1" |
||||
#define CONFIG_SYS_TSEC2_OFFSET 0x25000 |
||||
#define TSEC2_PHY_ADDR 0x3 |
||||
#define TSEC2_FLAGS TSEC_GIGABIT |
||||
#define TSEC2_PHYIDX 0 |
||||
#endif |
||||
#define CONFIG_ETHPRIME "TSEC1" |
||||
|
||||
/*
|
||||
* Serial Port |
||||
*/ |
||||
#define CONFIG_CONS_INDEX 1 |
||||
#define CONFIG_SYS_NS16550 |
||||
#define CONFIG_SYS_NS16550_SERIAL |
||||
#define CONFIG_SYS_NS16550_REG_SIZE 1 |
||||
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE \ |
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} |
||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) |
||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) |
||||
#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2) |
||||
|
||||
#define CONFIG_HAS_FSL_DR_USB |
||||
#define CONFIG_SYS_SCCR_USBDRCM 3 |
||||
|
||||
/*
|
||||
* BAT's |
||||
*/ |
||||
#define CONFIG_HIGH_BATS |
||||
|
||||
/* DDR @ 0x00000000 */ |
||||
#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE |\ |
||||
BATL_PP_10) |
||||
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE |\ |
||||
BATU_BL_256M |\
|
||||
BATU_VS |\
|
||||
BATU_VP) |
||||
#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L |
||||
#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U |
||||
|
||||
/* Initial RAM @ 0xFD000000 */ |
||||
#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR |\ |
||||
BATL_PP_10 |\
|
||||
BATL_GUARDEDSTORAGE) |
||||
#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR |\ |
||||
BATU_BL_256K |\
|
||||
BATU_VS |\
|
||||
BATU_VP) |
||||
#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L |
||||
#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U |
||||
|
||||
/* FLASH @ 0xFF800000 */ |
||||
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE |\ |
||||
BATL_PP_10 |\
|
||||
BATL_GUARDEDSTORAGE) |
||||
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE |\ |
||||
BATU_BL_8M |\
|
||||
BATU_VS |\
|
||||
BATU_VP) |
||||
#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE |\ |
||||
BATL_PP_10 |\
|
||||
BATL_CACHEINHIBIT |\
|
||||
BATL_GUARDEDSTORAGE) |
||||
#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U |
||||
|
||||
#define CONFIG_SYS_IBAT3L (0) |
||||
#define CONFIG_SYS_IBAT3U (0) |
||||
#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L |
||||
#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U |
||||
|
||||
#define CONFIG_SYS_IBAT4L (0) |
||||
#define CONFIG_SYS_IBAT4U (0) |
||||
#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L |
||||
#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U |
||||
|
||||
/* IMMRBAR @ 0xF0000000 */ |
||||
#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR |\ |
||||
BATL_PP_10 |\
|
||||
BATL_CACHEINHIBIT |\
|
||||
BATL_GUARDEDSTORAGE) |
||||
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR |\ |
||||
BATU_BL_128M |\
|
||||
BATU_VS |\
|
||||
BATU_VP) |
||||
#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L |
||||
#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U |
||||
|
||||
/* NAND-Flash @ 0xE1000000, MRAM @ 0xE2000000, CPLD @ 0xE3000000 */ |
||||
#define CONFIG_SYS_IBAT6L (0xE0000000 |\ |
||||
BATL_PP_10 |\
|
||||
BATL_GUARDEDSTORAGE) |
||||
#define CONFIG_SYS_IBAT6U (0xE0000000 |\ |
||||
BATU_BL_256M |\
|
||||
BATU_VS |\
|
||||
BATU_VP) |
||||
#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L |
||||
#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U |
||||
|
||||
#define CONFIG_SYS_IBAT7L (0) |
||||
#define CONFIG_SYS_IBAT7U (0) |
||||
#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L |
||||
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U |
||||
|
||||
/*
|
||||
* U-Boot environment setup |
||||
*/ |
||||
#include <config_cmd_default.h> |
||||
|
||||
#define CONFIG_CMD_DHCP |
||||
#define CONFIG_CMD_PING |
||||
#define CONFIG_CMD_NFS |
||||
#define CONFIG_CMD_NAND |
||||
#define CONFIG_CMD_FLASH |
||||
#define CONFIG_CMD_SNTP |
||||
#define CONFIG_CMD_MII |
||||
#define CONFIG_CMD_DATE |
||||
#define CONFIG_CMDLINE_EDITING |
||||
#define CONFIG_CMD_EDITENV |
||||
#define CONFIG_CMD_JFFS2 |
||||
#define CONFIG_BOOTP_SUBNETMASK |
||||
#define CONFIG_BOOTP_GATEWAY |
||||
#define CONFIG_BOOTP_HOSTNAME |
||||
#define CONFIG_BOOTP_BOOTPATH |
||||
#define CONFIG_BOOTP_BOOTFILESIZE |
||||
/* pass open firmware flat tree */ |
||||
#define CONFIG_OF_LIBFDT |
||||
#define CONFIG_OF_BOARD_SETUP |
||||
#define CONFIG_OF_STDOUT_VIA_ALIAS |
||||
|
||||
/*
|
||||
* The reserved memory |
||||
*/ |
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
||||
#define CONFIG_SYS_MONITOR_LEN (768 * 1024) |
||||
#define CONFIG_SYS_MALLOC_LEN (8 * 1024 * 1024) |
||||
|
||||
/*
|
||||
* Environment Configuration |
||||
*/ |
||||
#define CONFIG_ENV_IS_IN_FLASH |
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \ |
||||
+ CONFIG_SYS_MONITOR_LEN) |
||||
#define CONFIG_ENV_SIZE 0x20000 |
||||
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE) |
||||
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) |
||||
|
||||
|
||||
#define CONFIG_NETDEV eth1 |
||||
#define CONFIG_HOSTNAME ids8313 |
||||
#define CONFIG_ROOTPATH "/opt/eldk-4.2/ppc_6xx" |
||||
#define CONFIG_BOOTFILE "ids8313/uImage" |
||||
#define CONFIG_UBOOTPATH "ids8313/u-boot.bin" |
||||
#define CONFIG_FDTFILE "ids8313/ids8313.dtb" |
||||
#define CONFIG_LOADADDR 0x400000 |
||||
#define CONFIG_CMD_ENV_FLAGS |
||||
#define CONFIG_ENV_FLAGS_LIST_STATIC "ethaddr:mo,eth1addr:mo" |
||||
|
||||
#define CONFIG_BAUDRATE 115200 |
||||
#define CONFIG_SYS_HZ 1000 |
||||
|
||||
/* Initial Memory map for Linux*/ |
||||
#define CONFIG_SYS_BOOTMAPSZ (256 << 20) |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CONFIG_SYS_LONGHELP |
||||
#define CONFIG_SYS_PROMPT "=> " |
||||
#define CONFIG_SYS_CBSIZE 1024 |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ |
||||
+ sizeof(CONFIG_SYS_PROMPT)+16) |
||||
#define CONFIG_SYS_MAXARGS 16 |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
||||
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ |
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " |
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x00001000 |
||||
#define CONFIG_SYS_MEMTEST_END 0x00C00000 |
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x100000 |
||||
#define CONFIG_MII |
||||
#define CONFIG_LOADS_ECHO |
||||
#define CONFIG_TIMESTAMP |
||||
#define CONFIG_PREBOOT "echo;" \ |
||||
"echo Type \\\"run nfsboot\\\" " \
|
||||
"to mount root filesystem over NFS;echo" |
||||
#undef CONFIG_BOOTARGS |
||||
#define CONFIG_BOOTCOMMAND "run boot_cramfs" |
||||
#undef CONFIG_SYS_LOADS_BAUD_CHANGE |
||||
|
||||
#define CONFIG_JFFS2_NAND |
||||
#define CONFIG_JFFS2_DEV "0" |
||||
|
||||
/* mtdparts command line support */ |
||||
#define CONFIG_CMD_MTDPARTS |
||||
#define CONFIG_FLASH_CFI_MTD |
||||
#define CONFIG_MTD_DEVICE |
||||
#define MTDIDS_DEFAULT "nor0=ff800000.flash,nand0=e1000000.flash" |
||||
#define MTDPARTS_DEFAULT "mtdparts=ff800000.flash:7m(dum)," \ |
||||
"768k(BOOT-BIN)," \
|
||||
"128k(BOOT-ENV),128k(BOOT-REDENV);" \
|
||||
"e1000000.flash:-(ubi)" |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"netdev=" __stringify(CONFIG_NETDEV) "\0" \
|
||||
"ethprime=TSEC1\0" \
|
||||
"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
|
||||
"tftpflash=tftpboot ${loadaddr} ${uboot}; " \
|
||||
"protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
|
||||
" +${filesize}; " \
|
||||
"erase " __stringify(CONFIG_SYS_TEXT_BASE) \
|
||||
" +${filesize}; " \
|
||||
"cp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE) \
|
||||
" ${filesize}; " \
|
||||
"protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
|
||||
" +${filesize}; " \
|
||||
"cmp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE) \
|
||||
" ${filesize}\0" \
|
||||
"console=ttyS0\0" \
|
||||
"fdtaddr=0x780000\0" \
|
||||
"kernel_addr=ff800000\0" \
|
||||
"fdtfile=" __stringify(CONFIG_FDTFILE) "\0" \
|
||||
"setbootargs=setenv bootargs " \
|
||||
"root=${rootdev} rw console=${console}," \
|
||||
"${baudrate} ${othbootargs}\0" \
|
||||
"setipargs=setenv bootargs root=${rootdev} rw " \
|
||||
"nfsroot=${serverip}:${rootpath} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:" \
|
||||
"${netmask}:${hostname}:${netdev}:off " \
|
||||
"console=${console},${baudrate} ${othbootargs}\0" \
|
||||
"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
|
||||
"mtdids=" MTDIDS_DEFAULT "\0" \
|
||||
"mtdparts=" MTDPARTS_DEFAULT "\0" \
|
||||
"\0" |
||||
|
||||
#define CONFIG_NFSBOOTCOMMAND \ |
||||
"setenv rootdev /dev/nfs;" \
|
||||
"run setipargs;run addmtd;" \
|
||||
"tftp ${loadaddr} ${bootfile};" \
|
||||
"tftp ${fdtaddr} ${fdtfile};" \
|
||||
"fdt addr ${fdtaddr};" \
|
||||
"bootm ${loadaddr} - ${fdtaddr}" |
||||
|
||||
/* UBI Support */ |
||||
#define CONFIG_CMD_NAND_TRIMFFS |
||||
#define CONFIG_CMD_UBI |
||||
#define CONFIG_CMD_UBIFS |
||||
#define CONFIG_RBTREE |
||||
#define CONFIG_LZO |
||||
#define CONFIG_MTD_PARTITIONS |
||||
|
||||
/* bootcount support */ |
||||
#define CONFIG_BOOTCOUNT_LIMIT |
||||
#define CONFIG_BOOTCOUNT_I2C |
||||
#define CONFIG_BOOTCOUNT_ALEN 1 |
||||
#define CONFIG_SYS_BOOTCOUNT_ADDR 0x9 |
||||
|
||||
#define CONFIG_VERSION_VARIABLE |
||||
|
||||
#define CONFIG_FIT |
||||
#define CONFIG_FIT_SIGNATURE |
||||
#define CONFIG_CMD_FDT |
||||
#define CONFIG_CMD_HASH |
||||
#define CONFIG_RSA |
||||
#define CONFIG_SHA1 |
||||
#define CONFIG_SHA256 |
||||
#define CONFIG_OF_CONTROL |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
Loading…
Reference in new issue