Adjust minnowmax to use driver model for PCI. This requires adding a device tree node to specify the ranges, removing the board-specific PCI code and ensuring that the host bridge is configured. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Simon Glass <sjg@chromium.org>master
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/*
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* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <pci.h> |
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#include <asm/pci.h> |
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#include <asm/fsp/fsp_support.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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void board_pci_setup_hose(struct pci_controller *hose) |
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{ |
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hose->first_busno = 0; |
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hose->last_busno = 0; |
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/* PCI memory space */ |
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pci_set_region(hose->regions + 0, |
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CONFIG_PCI_MEM_BUS, |
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CONFIG_PCI_MEM_PHYS, |
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CONFIG_PCI_MEM_SIZE, |
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PCI_REGION_MEM); |
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/* PCI IO space */ |
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pci_set_region(hose->regions + 1, |
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CONFIG_PCI_IO_BUS, |
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CONFIG_PCI_IO_PHYS, |
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CONFIG_PCI_IO_SIZE, |
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PCI_REGION_IO); |
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pci_set_region(hose->regions + 2, |
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CONFIG_PCI_PREF_BUS, |
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CONFIG_PCI_PREF_PHYS, |
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CONFIG_PCI_PREF_SIZE, |
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PCI_REGION_PREFETCH); |
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pci_set_region(hose->regions + 3, |
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0, |
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0, |
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gd->ram_size < 0x80000000 ? gd->ram_size : 0x80000000, |
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PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); |
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hose->region_count = 4; |
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} |
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