Support of the MINI2440 board from FriendlyARM from an old version of u-boot : http://repo.or.cz/r/u-boot-openmoko/mini2440.git Currently, supporting only boot from NOR. Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>master
Gabriel Huau
13 years ago
committed by
Albert ARIBAUD
parent
5d889ae79e
commit
b77026225a
@ -0,0 +1,44 @@ |
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#
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# (C) Copyright 2012
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(BOARD).o
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COBJS := mini2440.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS) |
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$(call cmd_link_o_target, $(OBJS) $(SOBJS))
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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@ -0,0 +1,134 @@ |
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/*
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* (C) Copyright 2002 |
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
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* Marius Groeger <mgroeger@sysgo.de> |
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* |
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* (C) Copyright 2002 |
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* David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> |
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* |
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* (C) Copyright 2009 |
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* Michel Pollet <buserror@gmail.com> |
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* |
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* (C) Copyright 2012 |
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* Gabriel Huau <contact@huau-gabriel.fr> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <asm/arch/s3c2440.h> |
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#include <asm/arch/iomux.h> |
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#include <asm/arch/gpio.h> |
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#include <asm/io.h> |
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#include <asm/gpio.h> |
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#include <netdev.h> |
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#include "mini2440.h" |
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DECLARE_GLOBAL_DATA_PTR; |
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static inline void pll_delay(unsigned long loops) |
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{ |
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__asm__ volatile ("1:\n" |
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"subs %0, %1, #1\n" |
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"bne 1b" : "=r" (loops) : "0" (loops)); |
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} |
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int board_early_init_f(void) |
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{ |
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struct s3c24x0_clock_power * const clk_power = |
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s3c24x0_get_base_clock_power(); |
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/* to reduce PLL lock time, adjust the LOCKTIME register */ |
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clk_power->locktime = 0xFFFFFF; /* Max PLL Lock time count */ |
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clk_power->clkdivn = CLKDIVN_VAL; |
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/* configure UPLL */ |
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clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV); |
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/* some delay between MPLL and UPLL */ |
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pll_delay(100); |
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/* configure MPLL */ |
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clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV); |
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/* some delay between MPLL and UPLL */ |
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pll_delay(10000); |
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return 0; |
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} |
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/*
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* Miscellaneous platform dependent initialisations |
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*/ |
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int board_init(void) |
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{ |
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struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); |
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/* IOMUX Port H : UART Configuration */ |
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gpio->gphcon = IOMUXH_nCTS0 | IOMUXH_nRTS0 | IOMUXH_TXD0 | IOMUXH_RXD0 | |
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IOMUXH_TXD1 | IOMUXH_RXD1 | IOMUXH_TXD2 | IOMUXH_RXD2; |
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gpio_direction_output(GPH8, 0); |
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gpio_direction_output(GPH9, 0); |
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gpio_direction_output(GPH10, 0); |
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/* adress of boot parameters */ |
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gd->bd->bi_boot_params = CONFIG_BOOT_PARAM_ADDR; |
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return 0; |
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} |
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int dram_init(void) |
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{ |
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struct s3c24x0_memctl *memctl = s3c24x0_get_base_memctl(); |
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/*
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* Configuring bus width and timing |
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* Initialize clocks for each bank 0..5 |
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* Bank 3 and 4 are used for DM9000 |
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*/ |
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writel(BANK_CONF, &memctl->bwscon); |
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writel(B0_CONF, &memctl->bankcon[0]); |
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writel(B1_CONF, &memctl->bankcon[1]); |
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writel(B2_CONF, &memctl->bankcon[2]); |
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writel(B3_CONF, &memctl->bankcon[3]); |
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writel(B4_CONF, &memctl->bankcon[4]); |
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writel(B5_CONF, &memctl->bankcon[5]); |
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/* Bank 6 and 7 are used for DRAM */ |
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writel(SDRAM_64MB, &memctl->bankcon[6]); |
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writel(SDRAM_64MB, &memctl->bankcon[7]); |
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writel(MEM_TIMING, &memctl->refresh); |
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writel(BANKSIZE_CONF, &memctl->banksize); |
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writel(B6_MRSR, &memctl->mrsrb6); |
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writel(B7_MRSR, &memctl->mrsrb7); |
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gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE, |
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PHYS_SDRAM_SIZE); |
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return 0; |
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} |
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int board_eth_init(bd_t *bis) |
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{ |
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#ifdef CONFIG_DRIVER_DM9000 |
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return dm9000_initialize(bis); |
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#else |
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return 0; |
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#endif |
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} |
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@ -0,0 +1,144 @@ |
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#ifndef __MINI2440_BOARD_CONF_H__ |
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#define __MINI2440_BOARD_CONF_H__ |
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/* PLL Parameters */ |
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#define CLKDIVN_VAL 7 |
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#define M_MDIV 0x7f |
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#define M_PDIV 0x2 |
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#define M_SDIV 0x1 |
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#define U_M_MDIV 0x38 |
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#define U_M_PDIV 0x2 |
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#define U_M_SDIV 0x2 |
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/* BWSCON */ |
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#define DW8 0x0 |
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#define DW16 0x1 |
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#define DW32 0x2 |
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#define WAIT (0x1<<2) |
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#define UBLB (0x1<<3) |
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#define B1_BWSCON (DW32) |
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#define B2_BWSCON (DW16) |
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#define B3_BWSCON (DW16 + WAIT + UBLB) |
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#define B4_BWSCON (DW16 + WAIT + UBLB) |
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#define B5_BWSCON (DW16) |
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#define B6_BWSCON (DW32) |
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#define B7_BWSCON (DW32) |
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/*
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* Bank Configuration |
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*/ |
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#define B0_Tacs 0x0 /* 0clk */ |
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#define B0_Tcos 0x0 /* 0clk */ |
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#define B0_Tacc 0x7 /* 14clk */ |
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#define B0_Tcoh 0x0 /* 0clk */ |
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#define B0_Tah 0x0 /* 0clk */ |
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#define B0_Tacp 0x0 /* 0clk */ |
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#define B0_PMC 0x0 /* normal */ |
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#define B1_Tacs 0x0 |
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#define B1_Tcos 0x0 |
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#define B1_Tacc 0x7 |
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#define B1_Tcoh 0x0 |
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#define B1_Tah 0x0 |
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#define B1_Tacp 0x0 |
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#define B1_PMC 0x0 |
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#define B2_Tacs 0x0 |
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#define B2_Tcos 0x0 |
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#define B2_Tacc 0x7 |
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#define B2_Tcoh 0x0 |
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#define B2_Tah 0x0 |
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#define B2_Tacp 0x0 |
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#define B2_PMC 0x0 |
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#define B3_Tacs 0x0 |
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#define B3_Tcos 0x3 /* 4clk */ |
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#define B3_Tacc 0x7 |
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#define B3_Tcoh 0x1 /* 1clk */ |
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#define B3_Tah 0x3 /* 4clk */ |
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#define B3_Tacp 0x0 |
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#define B3_PMC 0x0 |
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#define B4_Tacs 0x0 |
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#define B4_Tcos 0x3 |
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#define B4_Tacc 0x7 |
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#define B4_Tcoh 0x1 |
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#define B4_Tah 0x3 |
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#define B4_Tacp 0x0 |
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#define B4_PMC 0x0 |
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#define B5_Tacs 0x0 |
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#define B5_Tcos 0x0 |
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#define B5_Tacc 0x7 |
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#define B5_Tcoh 0x0 |
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#define B5_Tah 0x0 |
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#define B5_Tacp 0x0 |
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#define B5_PMC 0x0 |
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/*
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* SDRAM Configuration |
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*/ |
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#define SDRAM_MT 0x3 /* SDRAM */ |
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#define SDRAM_Trcd 0x0 /* 2clk */ |
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#define SDRAM_SCAN_9 0x1 /* 9bit */ |
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#define SDRAM_SCAN_10 0x2 /* 10bit */ |
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#define SDRAM_64MB ((SDRAM_MT<<15) + (SDRAM_Trcd<<2) + (SDRAM_SCAN_9)) |
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/*
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* Refresh Parameter |
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*/ |
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#define REFEN 0x1 /* Refresh enable */ |
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#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */ |
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#define Trp 0x1 /* 3clk */ |
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#define Trc 0x3 /* 7clk */ |
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#define Tchr 0x0 /* unused */ |
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#define REFCNT 1012 /* period=10.37us, HCLK=100Mhz, (2048 + 1-10.37*100) */ |
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/*
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* MRSR Parameter |
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*/ |
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#define BL 0x0 |
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#define BT 0x0 |
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#define CL 0x3 /* 3 clocks */ |
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#define TM 0x0 |
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#define WBL 0x0 |
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/*
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* BankSize Parameter |
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*/ |
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#define BK76MAP 0x2 /* 128MB/128MB */ |
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#define SCLK_EN 0x1 /* SCLK active */ |
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#define SCKE_EN 0x1 /* SDRAM power down mode enable */ |
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#define BURST_EN 0x1 /* Burst enable */ |
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/*
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* Register values |
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*/ |
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#define BANK_CONF ((0 + (B1_BWSCON<<4) + (B2_BWSCON<<8) + (B3_BWSCON<<12) + \ |
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(B4_BWSCON<<16) + (B5_BWSCON<<20) + (B6_BWSCON<<24) + \
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(B7_BWSCON<<28))) |
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#define B0_CONF ((B0_Tacs<<13) + (B0_Tcos<<11) + (B0_Tacc<<8) + \ |
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(B0_Tcoh<<6) + (B0_Tah<<4) + (B0_Tacp<<2) + (B0_PMC)) |
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#define B1_CONF ((B1_Tacs<<13) + (B1_Tcos<<11) + (B1_Tacc<<8) + \ |
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(B1_Tcoh<<6) + (B1_Tah<<4) + (B1_Tacp<<2) + (B1_PMC)) |
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#define B2_CONF ((B2_Tacs<<13) + (B2_Tcos<<11) + (B2_Tacc<<8) + \ |
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(B2_Tcoh<<6) + (B2_Tah<<4) + (B2_Tacp<<2) + (B2_PMC)) |
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#define B3_CONF ((B3_Tacs<<13) + (B3_Tcos<<11) + (B3_Tacc<<8) + \ |
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(B3_Tcoh<<6) + (B3_Tah<<4) + (B3_Tacp<<2) + (B3_PMC)) |
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#define B4_CONF ((B4_Tacs<<13) + (B4_Tcos<<11) + (B4_Tacc<<8) + \ |
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(B4_Tcoh<<6) + (B4_Tah<<4) + (B4_Tacp<<2) + (B4_PMC)) |
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#define B5_CONF ((B5_Tacs<<13) + (B5_Tcos<<11) + (B5_Tacc<<8) + \ |
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(B5_Tcoh<<6) + (B5_Tah<<4) + (B5_Tacp<<2) + (B5_PMC)) |
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#define MEM_TIMING (REFEN<<23) + (TREFMD<<22) + (Trp<<20) + \ |
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(Trc<<18) + (Tchr<<16) + REFCNT |
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#define BANKSIZE_CONF (BK76MAP) + (SCLK_EN<<4) + (SCKE_EN<<5) + (BURST_EN<<7) |
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#define B6_MRSR (CL<<4) |
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#define B7_MRSR (CL<<4) |
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#endif |
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@ -0,0 +1,28 @@ |
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U-Boot for FriendlyARM Mini2440 (s3c2440) |
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This file contains information for the port of U-Boot to FriendlyARM |
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mini2440 |
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All information about the board can be found on : |
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http://www.friendlyarm.net/products/mini2440 |
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To build u-boot : ./MAKEALL mini2440 |
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Overview : |
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-------- |
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FriendlyARM Mini 2440 SBC (Single-Board Computer) with 400 MHz Samsung S3C2440 |
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ARM9 processor. The board measures 100 x 100 mm, ideal for learning about ARM9 |
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systems. It's a low cost board. |
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Boot Methods : |
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------------ |
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Mini2440 can boot from NOR or NAND. |
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Build : |
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----- |
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./MAKEALL mini2440 |
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or |
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make mini2440_config |
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make |
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@ -0,0 +1,186 @@ |
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/*
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* (C) Copyright 2002 |
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
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* Marius Groeger <mgroeger@sysgo.de> |
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* Gary Jennejohn <gj@denx.de> |
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* David Mueller <d.mueller@elsoft.ch> |
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* |
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* (C) Copyright 2009-2010 |
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* Michel Pollet <buserror@gmail.com> |
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* |
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* (C) Copyright 2012 |
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* Gabriel Huau <contact@huau-gabriel.fr> |
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* |
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* Configuation settings for the MINI2440 board. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#ifndef __CONFIG_H |
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#define __CONFIG_H |
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#define CONFIG_SYS_TEXT_BASE 0x0 |
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#define CONFIG_S3C2440_GPIO |
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/*
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* High Level Configuration Options |
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*/ |
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#define CONFIG_ARM920T /* This is an ARM920T Core */ |
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#define CONFIG_S3C24X0 /* in a SAMSUNG S3C24X0 SoC */ |
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#define CONFIG_S3C2440 /* in a SAMSUNG S3C2440 SoC */ |
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#define CONFIG_MINI2440 /* on a MIN2440 Board */ |
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#define MACH_TYPE_MINI2440 1999 |
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#define CONFIG_MACH_TYPE MACH_TYPE_MINI2440 |
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/*
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* We don't use lowlevel_init |
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*/ |
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#define CONFIG_SKIP_LOWLEVEL_INIT |
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#define CONFIG_BOARD_EARLY_INIT_F |
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/*
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* input clock of PLL |
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*/ |
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/* MINI2440 has 12.0000MHz input clock */ |
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#define CONFIG_SYS_CLK_FREQ 12000000 |
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/*
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* Size of malloc() pool |
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*/ |
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048*1024) |
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/*
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* Hardware drivers |
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*/ |
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#define CONFIG_DRIVER_DM9000 |
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#define CONFIG_DRIVER_DM9000_NO_EEPROM |
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#define CONFIG_DM9000_BASE 0x20000300 |
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#define DM9000_IO CONFIG_DM9000_BASE |
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#define DM9000_DATA (CONFIG_DM9000_BASE+4) |
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/*
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* select serial console configuration |
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*/ |
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#define CONFIG_S3C24X0_SERIAL |
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#define CONFIG_SERIAL1 |
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/*
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* allow to overwrite serial and ethaddr |
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*/ |
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#define CONFIG_ENV_OVERWRITE |
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/*
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* Command definition |
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*/ |
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#include <config_cmd_default.h> |
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#define CONFIG_CMD_DHCP |
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#define CONFIG_CMD_PORTIO |
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#define CONFIG_CMD_REGINFO |
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#define CONFIG_CMD_SAVES |
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/*
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* Miscellaneous configurable options |
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*/ |
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#define CONFIG_LONGHELP |
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#define CONFIG_SYS_PROMPT "MINI2440 => " |
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#define CONFIG_SYS_CBSIZE 256 |
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) |
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#define CONFIG_SYS_MAXARGS 32 |
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
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#define CONFIG_SYS_MEMTEST_START 0x30000000 |
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#define CONFIG_SYS_MEMTEST_END 0x34000000 /* 64MB in DRAM */ |
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|
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/* default load address */ |
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#define CONFIG_SYS_LOAD_ADDR 0x32000000 |
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|
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/* boot parameters address */ |
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#define CONFIG_BOOT_PARAM_ADDR 0x30000100 |
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|
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/*
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* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need |
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* it to wrap 100 times (total 1562500) to get 1 sec. |
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*/ |
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#define CONFIG_SYS_HZ 1562500 |
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/*
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* valid baudrates |
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*/ |
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
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#define CONFIG_BAUDRATE 115200 |
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|
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/*
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* Stack sizes |
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* The stack sizes are set up in start.S using the settings below |
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*/ |
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#define CONFIG_STACKSIZE (128*1024) /* regular stack */ |
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#ifdef CONFIG_USE_IRQ |
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#define CONFIG_STACKSIZE_IRQ (8*1024) /* IRQ stack */ |
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#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ |
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#endif |
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|
||||
/*
|
||||
* Physical Memory Map |
||||
*/ |
||||
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ |
||||
#define PHYS_SDRAM_SIZE (64*1024*1024) /* 64MB of DRAM */ |
||||
#define CONFIG_SYS_SDRAM_BASE 0x30000000 |
||||
#define CONFIG_SYS_FLASH_BASE 0x0 |
||||
|
||||
/*
|
||||
* Stack should be on the SRAM because |
||||
* DRAM is not init |
||||
*/ |
||||
#define CONFIG_SYS_INIT_SP_ADDR (0x40001000 - GENERATED_GBL_DATA_SIZE) |
||||
|
||||
/*
|
||||
* NOR FLASH organization |
||||
* Now uses the standard CFI interface |
||||
* FLASH and environment organization |
||||
*/ |
||||
#define CONFIG_SYS_FLASH_CFI |
||||
#define CONFIG_FLASH_CFI_DRIVER |
||||
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT |
||||
#define CONFIG_SYS_MONITOR_BASE 0x0 |
||||
/* max number of memory banks */ |
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 |
||||
/* 512 * 4096 sectors, or 32 * 64k blocks */ |
||||
#define CONFIG_SYS_MAX_FLASH_SECT 512 |
||||
#define CONFIG_FLASH_SHOW_PROGRESS 1 |
||||
|
||||
/*
|
||||
* Config for NOR flash |
||||
*/ |
||||
#define CONFIG_ENV_IS_IN_FLASH |
||||
#define CONFIG_MY_ENV_OFFSET 0x40000 |
||||
/* addr of environment */ |
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_MY_ENV_OFFSET) |
||||
/* 16k Total Size of Environment Sector */ |
||||
#define CONFIG_ENV_SIZE 0x4000 |
||||
|
||||
/* ATAG configuration */ |
||||
#define CONFIG_INITRD_TAG |
||||
#define CONFIG_SETUP_MEMORY_TAGS |
||||
#define CONFIG_CMDLINE_TAG |
||||
#define CONFIG_CMDLINE_EDITING |
||||
#define CONFIG_AUTO_COMPLETE |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
Loading…
Reference in new issue