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powerpc: remove genietv board support

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Enough time has passed since this board was moved to Orphan. Remove.

 - Remove board/genietv/*
 - Remove include/configs/GENIETV.h
 - Clean-up if defined(CONFIG_GENIETV)
 - Move the entry from boards.cfg to doc/README.scrapyard

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
master
Masahiro Yamada 11 years ago committed by Tom Rini
parent d6b11fd1f0
commit b8a49bdaaa
11 changed files with 1 additions and 1429 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
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  1. 8
      board/genietv/Makefile
  2. 449
      board/genietv/flash.c
  3. 360
      board/genietv/genietv.c
  4. 101
      board/genietv/u-boot.lds
  5. 127
      board/genietv/u-boot.lds.debug
  6. 1
      boards.cfg
  7. 1
      doc/README.console
  8. 1
      doc/README.scrapyard
  9. 2
      doc/README.video
  10. 26
      include/commproc.h
  11. 354
      include/configs/GENIETV.h

8
board/genietv/Makefile
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#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y = genietv.o flash.o

449
board/genietv/flash.c
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/*
* (C) Copyright 2000-2011
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <mpc8xx.h>
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
/*-----------------------------------------------------------------------
* Functions
*/
static ulong flash_get_size(vu_long *addr, flash_info_t *info);
static int write_word(flash_info_t *info, ulong dest, ulong data);
static void flash_get_offsets(ulong base, flash_info_t *info);
/*-----------------------------------------------------------------------
*/
unsigned long flash_init(void)
{
unsigned long size_b0;
int i;
/* Init: no FLASHes known */
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i)
flash_info[i].flash_id = FLASH_UNKNOWN;
/* Detect size */
size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE,
&flash_info[0]);
/* Setup offsets */
flash_get_offsets(CONFIG_SYS_FLASH_BASE, &flash_info[0]);
#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
/* Monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
CONFIG_SYS_MONITOR_BASE,
CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
&flash_info[0]);
#endif
flash_info[0].size = size_b0;
return size_b0;
}
/*-----------------------------------------------------------------------
* Fix this to support variable sector sizes
*/
static void flash_get_offsets(ulong base, flash_info_t *info)
{
int i;
/* set up sector start address table */
if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
/* set sector offsets for bottom boot block type */
for (i = 0; i < info->sector_count; i++)
info->start[i] = base + (i * 0x00010000);
}
}
/*-----------------------------------------------------------------------
*/
void flash_print_info(flash_info_t *info)
{
int i;
if (info->flash_id == FLASH_UNKNOWN) {
puts("missing or unknown FLASH type\n");
return;
}
switch (info->flash_id & FLASH_VENDMASK) {
case FLASH_MAN_AMD:
printf("AMD ");
break;
case FLASH_MAN_FUJ:
printf("FUJITSU ");
break;
case FLASH_MAN_BM:
printf("BRIGHT MICRO ");
break;
default:
printf("Unknown Vendor ");
break;
}
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_AM040:
printf("29F040 or 29LV040 (4 Mbit, uniform sectors)\n");
break;
case FLASH_AM400B:
printf("AM29LV400B (4 Mbit, bottom boot sect)\n");
break;
case FLASH_AM400T:
printf("AM29LV400T (4 Mbit, top boot sector)\n");
break;
case FLASH_AM800B:
printf("AM29LV800B (8 Mbit, bottom boot sect)\n");
break;
case FLASH_AM800T:
printf("AM29LV800T (8 Mbit, top boot sector)\n");
break;
case FLASH_AM160B:
printf("AM29LV160B (16 Mbit, bottom boot sect)\n");
break;
case FLASH_AM160T:
printf("AM29LV160T (16 Mbit, top boot sector)\n");
break;
case FLASH_AM320B:
printf("AM29LV320B (32 Mbit, bottom boot sect)\n");
break;
case FLASH_AM320T:
printf("AM29LV320T (32 Mbit, top boot sector)\n");
break;
default:
printf("Unknown Chip Type\n");
break;
}
if (info->size >> 20) {
printf(" Size: %ld MB in %d Sectors\n",
info->size >> 20,
info->sector_count);
} else {
printf(" Size: %ld KB in %d Sectors\n",
info->size >> 10,
info->sector_count);
}
puts(" Sector Start Addresses:");
for (i = 0; i < info->sector_count; ++i) {
if ((i % 5) == 0)
puts("\n ");
printf(" %08lX%s",
info->start[i],
info->protect[i] ? " (RO)" : " ");
}
putc('\n');
return;
}
/*-----------------------------------------------------------------------
*/
/*
* The following code cannot be run from FLASH!
*/
static ulong flash_get_size(vu_long *addr, flash_info_t *info)
{
short i;
volatile unsigned char *caddr;
char value;
caddr = (volatile unsigned char *)addr ;
/* Write auto select command: read Manufacturer ID */
debug("Base address is: %8p\n", caddr);
caddr[0x0555] = 0xAA;
caddr[0x02AA] = 0x55;
caddr[0x0555] = 0x90;
value = caddr[0];
debug("Manufact ID: %02x\n", value);
switch (value) {
case 0x1: /* AMD_MANUFACT */
info->flash_id = FLASH_MAN_AMD;
break;
case 0x4: /* FUJ_MANUFACT */
info->flash_id = FLASH_MAN_FUJ;
break;
default:
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
break;
}
value = caddr[1]; /* device ID */
debug("Device ID: %02x\n", value);
switch (value) {
case AMD_ID_LV040B:
info->flash_id += FLASH_AM040;
info->sector_count = 8;
info->size = 0x00080000;
break; /* => 512Kb */
default:
info->flash_id = FLASH_UNKNOWN;
return 0; /* => no or unknown flash */
}
flash_get_offsets((ulong)addr, &flash_info[0]);
/* check for protected sectors */
for (i = 0; i < info->sector_count; i++) {
/*
* read sector protection at sector address,
* (A7 .. A0) = 0x02
* D0 = 1 if protected
*/
caddr = (volatile unsigned char *)(info->start[i]);
info->protect[i] = caddr[2] & 1;
}
/*
* Prevent writes to uninitialized FLASH.
*/
if (info->flash_id != FLASH_UNKNOWN) {
caddr = (volatile unsigned char *)info->start[0];
*caddr = 0xF0; /* reset bank */
}
return info->size;
}
int flash_erase(flash_info_t *info, int s_first, int s_last)
{
volatile unsigned char *addr =
(volatile unsigned char *)(info->start[0]);
int flag, prot, sect, l_sect;
ulong start, now, last;
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN)
printf("- missing\n");
else
printf("- no sectors to erase\n");
return 1;
}
if ((info->flash_id == FLASH_UNKNOWN) ||
(info->flash_id > FLASH_AMD_COMP)) {
printf("Can't erase unknown flash type - aborted\n");
return 1;
}
prot = 0;
for (sect = s_first; sect <= s_last; ++sect) {
if (info->protect[sect])
prot++;
}
if (prot) {
printf("- Warning: %d protected sectors will not be erased!\n",
prot);
} else {
printf("\n");
}
l_sect = -1;
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
addr[0x0555] = 0xAA;
addr[0x02AA] = 0x55;
addr[0x0555] = 0x80;
addr[0x0555] = 0xAA;
addr[0x02AA] = 0x55;
/* Start erase on unprotected sectors */
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
addr = (volatile unsigned char *)(info->start[sect]);
addr[0] = 0x30;
l_sect = sect;
}
}
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* wait at least 80us - let's wait 1 ms */
udelay(1000);
/*
* We wait for the last triggered sector
*/
if (l_sect < 0)
goto DONE;
start = get_timer(0);
last = start;
addr = (volatile unsigned char *)(info->start[l_sect]);
while ((addr[0] & 0xFF) != 0xFF) {
now = get_timer(start);
if (now > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf("Timeout\n");
return 1;
}
/* show that we're waiting */
if ((now - last) > 1000) { /* every second */
putc('.');
last = now;
}
}
DONE:
/* reset to read mode */
addr = (volatile unsigned char *)info->start[0];
addr[0] = 0xF0; /* reset bank */
printf(" done\n");
return 0;
}
/*-----------------------------------------------------------------------
* Copy memory to flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
{
ulong cp, wp, data;
int i, l, rc;
wp = (addr & ~3); /* get lower word aligned address */
/*
* handle unaligned start bytes
*/
l = addr - wp;
if (l != 0) {
data = 0;
for (i = 0, cp = wp; i < l; ++i, ++cp)
data = (data << 8) | (*(uchar *)cp);
for (; i < 4 && cnt > 0; ++i) {
data = (data << 8) | *src++;
--cnt;
++cp;
}
for (; cnt == 0 && i < 4; ++i, ++cp)
data = (data << 8) | (*(uchar *)cp);
rc = write_word(info, wp, data);
if (rc != 0)
return rc;
wp += 4;
}
/*
* handle word aligned part
*/
while (cnt >= 4) {
data = 0;
for (i = 0; i < 4; ++i)
data = (data << 8) | *src++;
rc = write_word(info, wp, data);
if (rc != 0)
return rc;
wp += 4;
cnt -= 4;
}
if (cnt == 0)
return 0;
/*
* handle unaligned tail bytes
*/
data = 0;
for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
data = (data << 8) | *src++;
--cnt;
}
for (; i < 4; ++i, ++cp)
data = (data << 8) | (*(uchar *)cp);
return write_word(info, wp, data);
}
/*-----------------------------------------------------------------------
* Write a word to Flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
static int write_word(flash_info_t *info, ulong dest, ulong data)
{
volatile unsigned char *cdest, *cdata;
volatile unsigned char *addr =
(volatile unsigned char *)(info->start[0]);
ulong start;
int flag, count = 4 ;
cdest = (volatile unsigned char *)dest ;
cdata = (volatile unsigned char *)&data ;
/* Check if Flash is (sufficiently) erased */
if ((*((vu_long *)dest) & data) != data)
return 2;
while (count--) {
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
addr[0x0555] = 0xAA;
addr[0x02AA] = 0x55;
addr[0x0555] = 0xA0;
*cdest = *cdata;
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* data polling for D7 */
start = get_timer(0);
while ((*cdest ^ *cdata) & 0x80) {
if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT)
return 1;
}
cdata++ ;
cdest++ ;
}
return 0;
}

360
board/genietv/genietv.c
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/*
* genietv/genietv.c
*
* The GENIETV is using the following physical memorymap (copied from
* the FADS configuration):
*
* ff020000 -> ff02ffff : pcmcia
* ff010000 -> ff01ffff : BCSR connected to CS1, setup by 8xxROM
* ff000000 -> ff00ffff : IMAP internal in the cpu
* 02800000 -> 0287ffff : flash connected to CS0
* 00000000 -> nnnnnnnn : sdram setup by U-Boot
*
* CS pins are connected as follows:
*
* CS0 -512Kb boot flash
* CS1 - SDRAM #1
* CS2 - SDRAM #2
* CS3 - Flash #1
* CS4 - Flash #2
* CS5 - LON (if present)
* CS6 - PCMCIA #1
* CS7 - PCMCIA #2
*
* Ports are configured as follows:
*
* PA7 - SDRAM banks enable
*/
#include <common.h>
#include <mpc8xx.h>
#define CONFIG_SYS_PA7 0x0100
/* ------------------------------------------------------------------------- */
static long int dram_size (long int, long int *, long int);
/* ------------------------------------------------------------------------- */
#define _NOT_USED_ 0xFFFFFFFF
const uint sdram_table[] = {
/*
* Single Read. (Offset 0 in UPMB RAM)
*/
0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBEEC00,
0x1FFDDC47, /* last */
/*
* SDRAM Initialization (offset 5 in UPMB RAM)
*
* This is no UPM entry point. The following definition uses
* the remaining space to establish an initialization
* sequence, which is executed by a RUN command.
*
*/
0x1FFDDC34, 0xEFEEAC34, 0x1FBD5C35, /* last */
/*
* Burst Read. (Offset 8 in UPMB RAM)
*/
0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00,
0xF0AFFC00, 0xF1AFFC00, 0xEFBEEC00, 0x1FFDDC47, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Single Write. (Offset 18 in UPMB RAM)
*/
0x1F2DFC04, 0xEEAFAC00, 0x01BE4C04, 0x1FFDDC47, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Burst Write. (Offset 20 in UPMB RAM)
*/
0x1F0DFC04, 0xEEAFAC00, 0x10AF5C00, 0xF0AFFC00,
0xF0AFFC00, 0xE1BEEC04, 0x1FFDDC47, /* last */
_NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Refresh (Offset 30 in UPMB RAM)
*/
0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
0xFFFFFC84, 0xFFFFFC07, /* last */
_NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Exception. (Offset 3c in UPMB RAM)
*/
0x7FFFFC07, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_,
};
/* ------------------------------------------------------------------------- */
/*
* Check Board Identity
*/
int checkboard (void)
{
puts ("Board: GenieTV\n");
return 0;
}
#if 0
static void PrintState (void)
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &im->im_memctl;
printf ("\n0 - FLASH: B=%08x O=%08x", memctl->memc_br0,
memctl->memc_or0);
printf ("\n1 - SDRAM: B=%08x O=%08x", memctl->memc_br1,
memctl->memc_or1);
printf ("\n2 - SDRAM: B=%08x O=%08x", memctl->memc_br2,
memctl->memc_or2);
}
#endif
/* ------------------------------------------------------------------------- */
phys_size_t initdram (int board_type)
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &im->im_memctl;
long int size_b0, size_b1, size8;
/* Enable SDRAM */
/* Configuring PA7 for general purpouse output pin */
im->im_ioport.iop_papar &= ~CONFIG_SYS_PA7; /* 0 = general purpouse */
im->im_ioport.iop_padir |= CONFIG_SYS_PA7; /* 1 = output */
/* Enable SDRAM - PA7 = 1 */
im->im_ioport.iop_padat |= CONFIG_SYS_PA7; /* value of PA7 */
/*
* Preliminary prescaler for refresh (depends on number of
* banks): This value is selected for four cycles every 62.4 us
* with two SDRAM banks or four cycles every 31.2 us with one
* bank. It will be adjusted after memory sizing.
*/
memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL;
upmconfig (UPMB, (uint *) sdram_table,
sizeof (sdram_table) / sizeof (uint));
/*
* Map controller banks 1 and 2 to the SDRAM banks 1 and 2 at
* preliminary addresses - these have to be modified after the
* SDRAM size has been determined.
*/
memctl->memc_or1 = 0xF0000000 | CONFIG_SYS_OR_TIMING_SDRAM;
memctl->memc_br1 =
((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V);
memctl->memc_or2 = 0xF0000000 | CONFIG_SYS_OR_TIMING_SDRAM;
memctl->memc_br2 =
((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V);
/* perform SDRAM initialization sequence */
memctl->memc_mar = 0x00000088;
memctl->memc_mcr = 0x80802105; /* SDRAM bank 0 */
memctl->memc_mcr = 0x80804105; /* SDRAM bank 1 */
/* Execute refresh 8 times */
memctl->memc_mbmr = (CONFIG_SYS_MBMR_8COL & ~MBMR_TLFB_MSK) | MBMR_TLFB_8X;
memctl->memc_mcr = 0x80802130; /* SDRAM bank 0 - execute twice */
memctl->memc_mcr = 0x80804130; /* SDRAM bank 1 - execute twice */
/* Execute refresh 4 times */
memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL;
/*
* Check Bank 0 Memory Size for re-configuration
*
* try 8 column mode
*/
#if 0
PrintState ();
#endif
/* printf ("\nChecking bank1..."); */
size8 = dram_size (CONFIG_SYS_MBMR_8COL, (long *) SDRAM_BASE1_PRELIM,
SDRAM_MAX_SIZE);
size_b0 = size8;
/* printf ("\nChecking bank2..."); */
size_b1 =
dram_size (memctl->memc_mbmr, (long *) SDRAM_BASE2_PRELIM,
SDRAM_MAX_SIZE);
/*
* Final mapping: map bigger bank first
*/
memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V;
if (size_b1 > 0) {
/*
* Position Bank 1 immediately above Bank 0
*/
memctl->memc_or2 =
((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
memctl->memc_br2 =
((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V) +
(size_b0 & BR_BA_MSK);
} else {
/*
* No bank 1
*
* invalidate bank
*/
memctl->memc_br2 = 0;
/* adjust refresh rate depending on SDRAM type, one bank */
memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_4K;
}
/* If no memory detected, disable SDRAM */
if ((size_b0 + size_b1) == 0) {
printf ("disabling SDRAM!\n");
/* Disable SDRAM - PA7 = 1 */
im->im_ioport.iop_padat &= ~CONFIG_SYS_PA7; /* value of PA7 */
}
/* else */
/* printf("done! (%08lx)\n", size_b0 + size_b1); */
#if 0
PrintState ();
#endif
return (size_b0 + size_b1);
}
/* ------------------------------------------------------------------------- */
/*
* Check memory range for valid RAM. A simple memory test determines
* the actually available RAM size between addresses `base' and
* `base + maxsize'. Some (not all) hardware errors are detected:
* - short between address lines
* - short between data lines
*/
static long int dram_size (long int mbmr_value, long int *base,
long int maxsize)
{
long size;
/*memctl->memc_mbmr = mbmr_value; */
size = get_ram_size (base, maxsize);
if (size) {
/* printf("(%08lx)", size); */
} else {
printf ("(0)");
}
return (size);
}
#if defined(CONFIG_CMD_PCMCIA)
#ifdef CONFIG_SYS_PCMCIA_MEM_ADDR
volatile unsigned char *pcmcia_mem = (unsigned char *) CONFIG_SYS_PCMCIA_MEM_ADDR;
#endif
int pcmcia_init (void)
{
volatile pcmconf8xx_t *pcmp;
uint v, slota, slotb;
/*
** Enable the PCMCIA for a Flash card.
*/
pcmp = (pcmconf8xx_t *) (&(((immap_t *) CONFIG_SYS_IMMR)->im_pcmcia));
#if 0
pcmp->pcmc_pbr0 = CONFIG_SYS_PCMCIA_MEM_ADDR;
pcmp->pcmc_por0 = 0xc00ff05d;
#endif
/* Set all slots to zero by default. */
pcmp->pcmc_pgcra = 0;
pcmp->pcmc_pgcrb = 0;
#ifdef PCMCIA_SLOT_A
pcmp->pcmc_pgcra = 0x40;
#endif
#ifdef PCMCIA_SLOT_B
pcmp->pcmc_pgcrb = 0x40;
#endif
/* Check if any PCMCIA card is luged in. */
slota = (pcmp->pcmc_pipr & 0x18000000) == 0;
slotb = (pcmp->pcmc_pipr & 0x00001800) == 0;
if (!(slota || slotb)) {
printf ("No card present\n");
#ifdef PCMCIA_SLOT_A
pcmp->pcmc_pgcra = 0;
#endif
#ifdef PCMCIA_SLOT_B
pcmp->pcmc_pgcrb = 0;
#endif
return -1;
} else
printf ("Unknown card (");
v = 0;
switch ((pcmp->pcmc_pipr >> 14) & 3) {
case 0x00:
printf ("5V");
v = 5;
break;
case 0x01:
printf ("5V and 3V");
v = 3;
break;
case 0x03:
printf ("5V, 3V and x.xV");
v = 3;
break;
}
switch (v) {
case 3:
printf ("; using 3V");
/* Enable 3 volt Vcc. */
break;
default:
printf ("; unknown voltage");
return -1;
}
printf (")\n");
/* disable pcmcia reset after a while */
udelay (20);
pcmp->pcmc_pgcrb = 0;
/* If you using a real hd you should give a short
* spin-up time. */
#ifdef CONFIG_DISK_SPINUP_TIME
udelay (CONFIG_DISK_SPINUP_TIME);
#endif
return 0;
}
#endif

101
board/genietv/u-boot.lds
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/*
* (C) Copyright 2000-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
OUTPUT_ARCH(powerpc)
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
arch/powerpc/cpu/mpc8xx/start.o (.text*)
arch/powerpc/cpu/mpc8xx/traps.o (.text*)
lib/built-in.o (.text*)
net/built-in.o (.text*)
arch/powerpc/cpu/mpc8xx/built-in.o (.text*)
board/genietv/built-in.o (.text*)
arch/powerpc/lib/built-in.o (.text*)
*(.text.do_load_serial*)
*(.text.do_mem_*)
*(.text.do_bootm*)
. = env_offset;
common/env_embedded.o (.text*)
*(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
_GOT2_TABLE_ = .;
KEEP(*(.got2))
KEEP(*(.got))
PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
_FIXUP_TABLE_ = .;
KEEP(*(.fixup))
}
__got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data*)
*(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
. = .;
. = ALIGN(4);
.u_boot_list : {
KEEP(*(SORT(.u_boot_list*)));
}
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(4096);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(4096);
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
{
*(.bss*)
*(.sbss*)
*(COMMON)
}
. = ALIGN(256 * 1024);
.ppcenv :
{
common/env_embedded.o (.ppcenv)
}
. = ALIGN(4);
__bss_end = . ;
PROVIDE (end = .);
}

127
board/genietv/u-boot.lds.debug
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@ -1,127 +0,0 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
OUTPUT_ARCH(powerpc)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
arch/powerpc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
arch/powerpc/lib/ppcstring.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
lib/zlib.o (.text)
. = env_offset;
common/env_embedded.o(.text)
*(.text)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = ALIGN(4);
.u_boot_list : {
KEEP(*(SORT(.u_boot_list*)));
}
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(4096);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(4096);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
. = ALIGN(256 * 1024);
.ppcenv :
{
common/env_embedded.o (.ppcenv)
}
__bss_end = . ;
PROVIDE (end = .);
}

1
boards.cfg
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@ -1252,4 +1252,3 @@ Orphan powerpc mpc8xx - - fads
Orphan powerpc mpc8xx - - fads FADS823 - -
Orphan powerpc mpc8xx - - fads FADS850SAR - -
Orphan powerpc mpc8xx - - fads FADS860T - -
Orphan powerpc mpc8xx - - genietv GENIETV - -

1
doc/README.console
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@ -99,4 +99,3 @@ The driver has been tested with the following configurations (see
CREDITS for other contact informations):
- MPC823FADS with AD7176 on a PAL TV (YCbYCr) - arsenio@tin.it
- GENIETV with AD7177 on a PAL TV (YCbYCr) - arsenio@tin.it

1
doc/README.scrapyard
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@ -11,6 +11,7 @@ easily if here is something they might want to dig for...
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
genietv powerpc mpc8xx - 2014-04-04
mbx8xx powerpc mpc8xx - 2014-04-04
nx823 powerpc mpc8xx - 2014-04-04
idmr m68k mcf52x2 ba650e9b 2014-01-28

2
doc/README.video
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@ -11,8 +11,6 @@ U-Boot MPC8xx video controller driver
The driver has been tested with the following configurations:
- MPC823FADS with AD7176 on a PAL TV (YCbYCr) - arsenio@tin.it
- GENIETV with AD7177 on a PAL TV (YCbYCr) - arsenio@tin.it
"video-mode" environment variable
===============================

26
include/commproc.h
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@ -704,32 +704,6 @@ typedef struct scc_enet {
#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3-15 */
#endif /* CONFIG_GEN860T */
/*** GENIETV ********************************************************/
#if defined(CONFIG_GENIETV)
/* Ethernet is only on SCC2 */
#define CONFIG_SCC2_ENET
#define PROFF_ENET PROFF_SCC2
#define CPM_CR_ENET CPM_CR_CH_SCC2
#define SCC_ENET 1
#define CPMVEC_ENET CPMVEC_SCC2
#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
#define SICR_ENET_MASK ((uint)0x0000ff00)
#define SICR_ENET_CLKRT ((uint)0x00002e00)
#endif /* CONFIG_GENIETV */
/*** HERMES-PRO ******************************************************/
/* The HERMES-PRO uses the FEC on a MPC860T for Ethernet */

354
include/configs/GENIETV.h
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@ -1,354 +0,0 @@
/*
* A collection of structures, addresses, and values associated with
* the Motorola 860T FADS board. Copied from the MBX stuff.
* Magnus Damm added defines for 8xxrom and extended bd_info.
* Helmut Buchsbaum added bitvalues for BCSRx
*
* Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
*/
/*
* The GENIETV is using the following physical memorymap (copied from
* the FADS configuration):
*
* ff020000 -> ff02ffff : pcmcia
* ff010000 -> ff01ffff : BCSR connected to CS1, setup by 8xxROM
* ff000000 -> ff00ffff : IMAP internal in the cpu
* 30000000 -> 300fffff : flash connected to CS0
* 00000000 -> nnnnnnnn : sdram setup by U-Boot
*
* CS pins are connected as follows:
*
* CS0 -512Kb boot flash
* CS1 - SDRAM #1
* CS2 - SDRAM #2
* CS3 - Flash #1
* CS4 - Flash #2
* CS5 - Lon (if present)
* CS6 - PCMCIA #1
* CS7 - PCMCIA #2
*/
/* ------------------------------------------------------------------------- */
/*
* board/config.h - configuration options, board specific
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_SYS_TEXT_BASE 0x00000000
#define CONFIG_ETHADDR 08:00:22:50:70:63 /* Ethernet address */
#define CONFIG_ENV_OVERWRITE 1 /* Overwrite the environment */
#define CONFIG_SYS_ALLOC_DPRAM /* Use dynamic DPRAM allocation */
#define CONFIG_SYS_AUTOLOAD "n" /* No autoload */
/*#define CONFIG_VIDEO 1 / To enable the video initialization */
/*#define CONFIG_VIDEO_ADDR 0x00200000 */
/*#define CONFIG_HARD_I2C 1 / I2C with hardware support */
/*#define CONFIG_PCMCIA 1 / To enable the PCMCIA initialization */
/*#define CONFIG_SYS_PCMCIA_IO_ADDR 0xff020000 */
/*#define CONFIG_SYS_PCMCIA_IO_SIZE 0x10000 */
/*#define CONFIG_SYS_PCMCIA_MEM_ADDR 0xe0000000 */
/*#define CONFIG_SYS_PCMCIA_MEM_SIZE 0x10000 */
/* Video related */
/*#define CONFIG_VIDEO_LOGO 1 / Show the logo */
/*#define CONFIG_VIDEO_ENCODER_AD7177 1 / Enable this encoder */
/*#define CONFIG_VIDEO_ENCODER_AD7177_ADDR 0xF4 / ALSB to ground */
/* Wireless 56Khz 4PPM keyboard on SMCx */
/*#define CONFIG_KEYBOARD 0 */
/*#define CONFIG_WL_4PPM_KEYBOARD_SMC 0 / SMC to use (0 indexed) */
/*
* High Level Configuration Options
* (easy to change)
*/
#include <mpc8xx_irq.h>
#define CONFIG_GENIETV 1
#define CONFIG_MPC823 1
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
#undef CONFIG_8xx_CONS_SMC2
#undef CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE 9600
#define MPC8XX_FACT 12 /* Multiply by 12 */
#define MPC8XX_XIN 5000000 /* 4 MHz clock */
#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT))
#define CONFIG_SYS_PLPRCR_MF ((MPC8XX_FACT-1) << 20)
#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ /* Force it - dont measure it */
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
#if 1
#define CONFIG_BOOTDELAY 1 /* autoboot after 2 seconds */
#define CONFIG_LOADS_ECHO 0 /* Dont echoes received characters */
#define CONFIG_BOOTARGS ""
#define CONFIG_BOOTCOMMAND \
"bootp; tftp; " \
"setenv bootargs console=tty0 console=ttyS0 " \
"root=/dev/nfs nfsroot=${serverip}:${rootpath} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${subnetmask}:${hostname}:eth0:off ;" \
"bootm "
#else
#define CONFIG_BOOTDELAY 0 /* autoboot disabled */
#endif
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_PROMPT ":>" /* Monitor Command Prompt */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 8 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x00800000 /* 0 ... 8 MB in DRAM */
#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
#define CONFIG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, 115200 }
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
*/
/*-----------------------------------------------------------------------
* Internal Memory Mapped Register
*/
#define CONFIG_SYS_IMMR 0xFF000000
#define CONFIG_SYS_IMMR_SIZE ((uint)(64 * 1024))
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
* Also NOTE that it doesn't mean SDRAM - it means MEMORY.
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_FLASH_BASE 0x02800000
#define CONFIG_SYS_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */
#if 0
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 128 kB for Monitor */
#else
#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
#endif
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 128 kB for malloc() */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */
#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector (64k)*/
/* values according to the manual */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
/*-----------------------------------------------------------------------
* SYPCR - System Protection Control 11-9
* SYPCR can only be written once after reset!
*-----------------------------------------------------------------------
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
*/
#if defined(CONFIG_WATCHDOG)
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
#else
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
#endif
/*-----------------------------------------------------------------------
* SIUMCR - SIU Module Configuration 11-6
*-----------------------------------------------------------------------
* PCMCIA config., multi-function pin tri-state
*
#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
*/
#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC10)
/*-----------------------------------------------------------------------
* TBSCR - Time Base Status and Control 11-26
*-----------------------------------------------------------------------
* Clear Reference Interrupt Status, Timebase freezing enabled
*/
#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
/*-----------------------------------------------------------------------
* PISCR - Periodic Interrupt Status and Control 11-31
*-----------------------------------------------------------------------
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
*/
#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
/*-----------------------------------------------------------------------
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
*-----------------------------------------------------------------------
* Reset PLL lock status sticky bit, timer expired status bit and timer *
* interrupt status bit - leave PLL multiplication factor unchanged !
*
* #define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
*/
#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | CONFIG_SYS_PLPRCR_MF)
/*-----------------------------------------------------------------------
* SCCR - System Clock and reset Control Register 15-27
*-----------------------------------------------------------------------
* Set clock output, timebase and RTC source and divider,
* power management and some other internal clocks
*/
#define SCCR_MASK SCCR_EBDF11
#define CONFIG_SYS_SCCR (SCCR_TBS | \
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
SCCR_DFALCD00)
/*-----------------------------------------------------------------------
*
*-----------------------------------------------------------------------
*
*/
#define CONFIG_SYS_DER 0
/* Because of the way the 860 starts up and assigns CS0 the
* entire address space, we have to set the memory controller
* differently. Normally, you write the option register
* first, and then enable the chip select by writing the
* base register. For CS0, you must write the base register
* first, followed by the option register.
*/
/*
* Init Memory Controller:
*
* BR0 and OR0(FLASH)
*/
#define FLASH_BASE0_PRELIM 0x02800000 /* FLASH bank #0 */
#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
#define CONFIG_SYS_PRELIM_OR_AM 0xFF800000 /* OR addr mask (512Kb) */
/* FLASH timing */
#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \
OR_SCY_15_CLK | OR_TRLX )
/*#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) */
#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) /* 0xfff80ff4 */
#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_8) /* 0x02800401 */
/*
* BR1/2 and OR1/2 (SDRAM)
*/
#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
#define SDRAM_MAX_SIZE 0x04000000 /* 64Mb bank */
#define SDRAM_BASE1_PRELIM 0x00000000 /* First bank */
#define SDRAM_BASE2_PRELIM 0x10000000 /* Second bank */
/*
* Memory Periodic Timer Prescaler
*/
/* periodic timer for refresh */
#define CONFIG_SYS_MBMR_PTB 0x5d /* start with divider for 100 MHz */
/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32
/*
* MBMR settings for SDRAM
*/
/* 8 column SDRAM */
#define CONFIG_SYS_MBMR_8COL ((CONFIG_SYS_MBMR_PTB << MAMR_PTA_SHIFT) | MAMR_PTAE | \
MAMR_G0CLA_A11 | MAMR_RLFA_1X | MAMR_WLFA_1X \
| MAMR_TLFA_4X) /* 0x5d802114 */
/* values according to the manual */
#define CONFIG_DRAM_50MHZ 1
#define CONFIG_SDRAM_50MHZ
/* We don't use the 8259.
*/
#define NR_8259_INTS 0
/*
* MPC8xx CPM Options
*/
#define CONFIG_SCC_ENET 1
#define CONFIG_DISK_SPINUP_TIME 1000000
/* PCMCIA configuration */
#define PCMCIA_MAX_SLOTS 1
#define PCMCIA_SLOT_B 1
#endif /* __CONFIG_H */
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