The code provides framework for heterogeneous multicore chips based on StarCore
and Power Architecture which are chasis-2 compliant, like B4860 and B4420
It will make u-boot recognize all non-ppc cores and peripherals like
SC3900/DSP CPUs, MAPLE, CPRI and print their configuration in u-boot logs.
Example boot logs of B4860QDS:
U-Boot 2015.01-00232-geef6e36-dirty (Jan 19 2015 - 11:58:45)
CPU0: B4860E, Version: 2.2, (0x86880022)
Core: e6500, Version: 2.0, (0x80400120)
Clock Configuration:
CPU0:1600 MHz, CPU1:1600 MHz, CPU2:1600 MHz, CPU3:1600 MHz,
DSP CPU0:1200 MHz, DSP CPU1:1200 MHz, DSP CPU2:1200 MHz, DSP CPU3:1200 MHz,
DSP CPU4:1200 MHz, DSP CPU5:1200 MHz,
CCB:666.667 MHz,
DDR:933.333 MHz (1866.667 MT/s data rate) (Asynchronous), IFC:166.667 MHz
CPRI:600 MHz
MAPLE:600 MHz, MAPLE-ULB:800 MHz, MAPLE-eTVPE:1000 MHz
FMAN1: 666.667 MHz
QMAN: 333.333 MHz
Top level changes include:
(1) Top level CONFIG to identify HETEROGENUOUS clusters
(2) CONFIGS for SC3900/DSP components
(3) Global structures like "cpu_type" and "MPC85xx_SYS_INFO"
updated for dsp cores and other components
(3) APIs to get DSP num cores and their Mask like:
cpu_dsp_mask, cpu_num_dspcores etc same as that of PowerPC
(5) Code to fetch and print SC cores and other heterogenous
device's frequencies
(6) README added for the same
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
master
Shaveta Leekha
10 years ago
committed by
York Sun
parent
8176a87423
commit
b8bf0adc12
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DSP side awareness for Freescale heterogeneous multicore chips based on |
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StarCore and Power Architecture |
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=============================================================== |
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powerpc/mpc85xx code ve APIs and function to get the number, |
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configuration and frequencies of all PowerPC cores and devices |
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connected to them, but it didnt have the similar code ofr HEterogeneous |
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SC3900/DSP cores and such devices like CPRI, MAPLE, MAPLE-ULB etc. |
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|
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Code for DSP side awareness provides such functionality for Freescale |
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Heterogeneous SoCs which are chasis-2 compliant like B4860 and B4420 |
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|
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As part of this feature, following changes have been made: |
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========================================================== |
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1. Changed files: |
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================= |
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- arch/powerpc/cpu/mpc85xx/cpu.c |
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Code added in this file to print the DSP cores and other device's(CPRI, |
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MAPLE etc) frequencies |
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|
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- arch/powerpc/cpu/mpc85xx/speed.c |
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|
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Added Defines and code to extract the frequncy information for all |
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required cores and devices from RCW and System frequency |
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|
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- arch/powerpc/cpu/mpc8xxx/cpu.c |
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Added API to get the number of SC cores in running system and Their BIT |
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MASK, similar to the code written for PowerPC |
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|
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- arch/powerpc/include/asm/config_mpc85xx.h |
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Added top level CONFIG to identify presence of HETEROGENUOUS clusters |
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in the system and CONFIGS for SC3900/DSP components |
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- arch/powerpc/include/asm/processor.h |
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- include/common.h |
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Added newly added Functions Declaration |
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- include/e500.h |
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Global structure updated for dsp cores and other components |
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2. CONFIGs ADDED |
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================ |
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CONFIG_HETROGENOUS_CLUSTERS - Define for checking the presence of |
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DSP/SC3900 core clusters |
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CONFIG_SYS_FSL_NUM_CC_PLLS - Define for number of PLLs |
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Though there are only 4 PLLs in B4, but in sequence of PLLs from PLL1 - |
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PLL5, PLL3 is Reserved(as mentioned in RM), so this define contains the |
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value as 5 not 4, to iterate over all PLLs while coding |
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|
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CONFIG_SYS_MAPLE - Define for MAPLE Baseband Accelerator |
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CONFIG_SYS_CPRI - Define for CPRI Interface |
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CONFIG_PPC_CLUSTER_START - Start index of ppc clusters |
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CONFIG_DSP_CLUSTER_START - Start index of dsp clusters |
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Following are the defines for PLL's index that provide the Clocking to |
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CPRI, ULB and ETVE components |
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CONFIG_SYS_CPRI_CLK - Define PLL index for CPRI clock |
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CONFIG_SYS_ULB_CLK - Define PLL index for ULB clock |
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CONFIG_SYS_ETVPE_CLK - Define PLL index for ETVPE clock |
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3. Changes in MPC85xx_SYS_INFO Global structure |
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=============================================== |
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DSP cores and other device's components have been added in this structure. |
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freq_processor_dsp[CONFIG_MAX_DSP_CPUS] - Array to contain the DSP core's frequencies |
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freq_cpri - To store CPRI frequency |
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freq_maple - To store MAPLE frequency |
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freq_maple_ulb - To store MAPLE-ULB frequency |
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freq_maple_etvpe - To store MAPLE-eTVPE frequency |
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4. U-BOOT LOGS |
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============== |
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4.1 B4860QDS board |
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Boot from NOR flash |
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U-Boot 2014.07-00222-g70587a8-dirty (Aug 07 2014 - 13:15:47) |
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CPU0: B4860E, Version: 2.0, (0x86880020) |
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Core: e6500, Version: 2.0, (0x80400020) Clock Configuration: |
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CPU0:1600 MHz, CPU1:1600 MHz, CPU2:1600 MHz, CPU3:1600 MHz, |
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DSP CPU0:1200 MHz, DSP CPU1:1200 MHz, DSP CPU2:1200 MHz, DSP CPU3:1200 MHz, |
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DSP CPU4:1200 MHz, DSP CPU5:1200 MHz, |
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CCB:666.667 MHz, |
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DDR:933.333 MHz (1866.667 MT/s data rate) (Asynchronous), IFC:166.667 MHz |
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CPRI:600 MHz |
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MAPLE:600 MHz, MAPLE-ULB:800 MHz, MAPLE-eTVPE:1000 MHz |
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FMAN1: 666.667 MHz |
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QMAN: 333.333 MHz |
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CPUn - PowerPC core |
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DSP CPUn - SC3900 core |
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Shaveta Leekha(shaveta@freescale.com) |
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Created August 7, 2014 |
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=========================================== |
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