This board has not been converted to generic board by the deadline. Remove it. Signed-off-by: Simon Glass <sjg@chromium.org>master
Simon Glass
10 years ago
committed by
Tom Rini
parent
ad4f54ea86
commit
b9599dd857
@ -1,15 +0,0 @@ |
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if TARGET_TX25 |
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config SYS_BOARD |
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default "tx25" |
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config SYS_VENDOR |
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default "karo" |
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config SYS_SOC |
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default "mx25" |
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config SYS_CONFIG_NAME |
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default "tx25" |
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endif |
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@ -1,6 +0,0 @@ |
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TX25 BOARD |
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M: John Rigby <jcrigby@gmail.com> |
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S: Maintained |
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F: board/karo/tx25/ |
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F: include/configs/tx25.h |
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F: configs/tx25_defconfig |
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@ -1,11 +0,0 @@ |
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#
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# (C) Copyright 2009 DENX Software Engineering
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# Author: John Rigby <jcrigby@gmail.com>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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ifdef CONFIG_SPL_BUILD |
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obj-y += lowlevel_init.o
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endif |
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obj-y += tx25.o
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@ -1,98 +0,0 @@ |
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/* |
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* (C) Copyright 2009 DENX Software Engineering |
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* Author: John Rigby <jrigby@gmail.com>
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* |
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* Based on U-Boot and RedBoot sources for several different i.mx |
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* platforms. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <asm/macro.h> |
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#include <asm/arch/macro.h> |
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.macro init_clocks
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/* |
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* clocks |
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* |
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* first enable CLKO debug output |
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* 0x40000000 enables the debug CLKO signal |
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* 0x05000000 sets CLKO divider to 6 |
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* 0x00600000 makes CLKO parent clk the USB clk |
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*/ |
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write32 0x53f80064, 0x45600000 |
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/* CCTL: ARM = 399 MHz, AHB = 133 MHz */ |
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write32 0x53f80008, 0x20034000 |
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/* |
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* PCDR2: NFC = 33.25 MHz |
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* This is required for the NAND Flash of this board, which is a Samsung |
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* K9F1G08U0B with 25-ns R/W cycle times, in order to make it work with |
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* the NFC driver in symmetric (i.e. one-cycle) mode. |
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*/ |
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write32 0x53f80020, 0x01010103 |
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/* |
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* enable all implemented clocks in all three |
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* clock control registers |
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*/ |
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write32 0x53f8000c, 0x1fffffff |
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write32 0x53f80010, 0xffffffff |
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write32 0x53f80014, 0xfdfff |
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.endm |
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.macro init_ddrtype
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/* |
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* ddr_type is 3.3v SDRAM |
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*/ |
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write32 0x43fac454, 0x800 |
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.endm |
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/* |
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* sdram controller init |
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*/ |
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.macro init_sdram_bank bankaddr, ctl, cfg |
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ldr r0, =0xb8001000 |
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ldr r2, =\bankaddr |
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/* |
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* reset SDRAM controller |
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* then wait for initialization to complete |
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*/ |
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ldr r1, =(1 << 1) |
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str r1, [r0, #0x10] |
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1: ldr r3, [r0, #0x10] |
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tst r3, #(1 << 31) |
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beq 1b |
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ldr r1, =0x95728 |
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str r1, [r0, #\cfg] /* config */ |
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ldr r1, =0x92116480 /* control | precharge */ |
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str r1, [r0, #\ctl] /* write command to controller */ |
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str r1, [r2, #0x400] /* command encoded in address */ |
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ldr r1, =0xa2116480 /* auto refresh */ |
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str r1, [r0, #\ctl] |
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ldrb r3, [r2] /* read dram twice to auto refresh */ |
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ldrb r3, [r2] |
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ldr r1, =0xb2116480 /* control | load mode */ |
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str r1, [r0, #\ctl] /* write command to controller */ |
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strb r1, [r2, #0x33] /* command encoded in address */ |
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ldr r1, =0x82116480 /* control | normal (0)*/ |
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str r1, [r0, #\ctl] /* write command to controller */ |
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.endm |
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.globl lowlevel_init
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lowlevel_init: |
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init_aips |
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init_max |
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init_m3if |
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init_clocks |
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init_sdram_bank 0x80000000, 0x0, 0x4 |
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init_sdram_bank 0x90000000, 0x8, 0xc |
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mov pc, lr |
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@ -1,210 +0,0 @@ |
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/*
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* (C) Copyright 2009 DENX Software Engineering |
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* Author: John Rigby <jrigby@gmail.com> |
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* |
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* Based on imx27lite.c: |
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* Copyright (C) 2008,2009 Eric Jarrige <jorasse@users.sourceforge.net> |
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* Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com> |
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* And: |
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* RedBoot tx25_misc.c Copyright (C) 2009 Red Hat |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/io.h> |
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#include <asm/arch/imx-regs.h> |
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#include <asm/arch/iomux-mx25.h> |
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#include <asm/gpio.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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#ifdef CONFIG_SPL_BUILD |
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void board_init_f(ulong bootflag) |
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{ |
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/*
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* copy ourselves from where we are running to where we were |
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* linked at. Use ulong pointers as all addresses involved |
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* are 4-byte-aligned. |
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*/ |
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ulong *start_ptr, *end_ptr, *link_ptr, *run_ptr, *dst; |
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asm volatile ("ldr %0, =_start" : "=r"(start_ptr)); |
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asm volatile ("ldr %0, =_end" : "=r"(end_ptr)); |
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asm volatile ("ldr %0, =board_init_f" : "=r"(link_ptr)); |
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asm volatile ("adr %0, board_init_f" : "=r"(run_ptr)); |
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for (dst = start_ptr; dst < end_ptr; dst++) |
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*dst = *(dst+(run_ptr-link_ptr)); |
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/*
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* branch to nand_boot's link-time address. |
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*/ |
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asm volatile("ldr pc, =nand_boot"); |
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} |
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#endif |
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#ifdef CONFIG_FEC_MXC |
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/*
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* FIXME: need to revisit this |
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* The original code enabled PUE and 100-k pull-down without PKE, so the right |
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* value here is likely: |
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* 0 for no pull |
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* or: |
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* PAD_CTL_PUS_100K_DOWN for 100-k pull-down |
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*/ |
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#define FEC_OUT_PAD_CTRL 0 |
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#define GPIO_FEC_RESET_B IMX_GPIO_NR(4, 7) |
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#define GPIO_FEC_ENABLE_B IMX_GPIO_NR(4, 9) |
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void tx25_fec_init(void) |
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{ |
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static const iomux_v3_cfg_t fec_pads[] = { |
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MX25_PAD_FEC_TX_CLK__FEC_TX_CLK, |
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MX25_PAD_FEC_RX_DV__FEC_RX_DV, |
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MX25_PAD_FEC_RDATA0__FEC_RDATA0, |
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NEW_PAD_CTRL(MX25_PAD_FEC_TDATA0__FEC_TDATA0, FEC_OUT_PAD_CTRL), |
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NEW_PAD_CTRL(MX25_PAD_FEC_TX_EN__FEC_TX_EN, FEC_OUT_PAD_CTRL), |
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NEW_PAD_CTRL(MX25_PAD_FEC_MDC__FEC_MDC, FEC_OUT_PAD_CTRL), |
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MX25_PAD_FEC_MDIO__FEC_MDIO, |
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MX25_PAD_FEC_RDATA1__FEC_RDATA1, |
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NEW_PAD_CTRL(MX25_PAD_FEC_TDATA1__FEC_TDATA1, FEC_OUT_PAD_CTRL), |
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NEW_PAD_CTRL(MX25_PAD_D13__GPIO_4_7, 0), /* FEC_RESET_B */ |
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NEW_PAD_CTRL(MX25_PAD_D11__GPIO_4_9, 0), /* FEC_ENABLE_B */ |
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}; |
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static const iomux_v3_cfg_t fec_cfg_pads[] = { |
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MX25_PAD_FEC_RDATA0__GPIO_3_10, |
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MX25_PAD_FEC_RDATA1__GPIO_3_11, |
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MX25_PAD_FEC_RX_DV__GPIO_3_12, |
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}; |
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debug("tx25_fec_init\n"); |
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imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); |
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/* drop PHY power and assert reset (low) */ |
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gpio_direction_output(GPIO_FEC_RESET_B, 0); |
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gpio_direction_output(GPIO_FEC_ENABLE_B, 0); |
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mdelay(5); |
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debug("resetting phy\n"); |
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/* turn on PHY power leaving reset asserted */ |
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gpio_set_value(GPIO_FEC_ENABLE_B, 1); |
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mdelay(10); |
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/*
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* Setup some strapping pins that are latched by the PHY |
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* as reset goes high. |
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* |
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* Set PHY mode to 111 |
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* mode0 comes from FEC_RDATA0 which is GPIO 3_10 in mux mode 5 |
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* mode1 comes from FEC_RDATA1 which is GPIO 3_11 in mux mode 5 |
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* mode2 is tied high so nothing to do |
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* |
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* Turn on RMII mode |
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* RMII mode is selected by FEC_RX_DV which is GPIO 3_12 in mux mode |
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*/ |
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/*
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* set each mux mode to gpio mode |
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*/ |
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imx_iomux_v3_setup_multiple_pads(fec_cfg_pads, |
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ARRAY_SIZE(fec_cfg_pads)); |
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/*
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* set each to 1 and make each an output |
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*/ |
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gpio_direction_output(IMX_GPIO_NR(3, 10), 1); |
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gpio_direction_output(IMX_GPIO_NR(3, 11), 1); |
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gpio_direction_output(IMX_GPIO_NR(3, 12), 1); |
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mdelay(22); /* this value came from RedBoot */ |
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/*
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* deassert PHY reset |
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*/ |
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gpio_set_value(GPIO_FEC_RESET_B, 1); |
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mdelay(5); |
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/*
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* set FEC pins back |
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*/ |
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imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); |
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} |
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#else |
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#define tx25_fec_init() |
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#endif |
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#ifdef CONFIG_MXC_UART |
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/*
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* Set up input pins with hysteresis and 100-k pull-ups |
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*/ |
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#define UART1_IN_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP) |
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/*
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* FIXME: need to revisit this |
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* The original code enabled PUE and 100-k pull-down without PKE, so the right |
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* value here is likely: |
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* 0 for no pull |
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* or: |
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* PAD_CTL_PUS_100K_DOWN for 100-k pull-down |
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*/ |
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#define UART1_OUT_PAD_CTRL 0 |
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static void tx25_uart1_init(void) |
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{ |
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static const iomux_v3_cfg_t uart1_pads[] = { |
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NEW_PAD_CTRL(MX25_PAD_UART1_RXD__UART1_RXD, UART1_IN_PAD_CTRL), |
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NEW_PAD_CTRL(MX25_PAD_UART1_TXD__UART1_TXD, UART1_OUT_PAD_CTRL), |
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NEW_PAD_CTRL(MX25_PAD_UART1_RTS__UART1_RTS, UART1_OUT_PAD_CTRL), |
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NEW_PAD_CTRL(MX25_PAD_UART1_CTS__UART1_CTS, UART1_IN_PAD_CTRL), |
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}; |
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imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); |
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} |
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#else |
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#define tx25_uart1_init() |
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#endif |
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int board_init() |
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{ |
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tx25_uart1_init(); |
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/* board id for linux */ |
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gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; |
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return 0; |
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} |
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int board_late_init(void) |
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{ |
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tx25_fec_init(); |
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return 0; |
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} |
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int dram_init(void) |
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{ |
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/* dram_init must store complete ramsize in gd->ram_size */ |
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gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1, |
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PHYS_SDRAM_1_SIZE); |
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return 0; |
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} |
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void dram_init_banksize(void) |
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{ |
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1; |
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gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1, |
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PHYS_SDRAM_1_SIZE); |
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#if CONFIG_NR_DRAM_BANKS > 1 |
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gd->bd->bi_dram[1].start = PHYS_SDRAM_2; |
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gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2, |
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PHYS_SDRAM_2_SIZE); |
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#else |
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#endif |
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} |
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int checkboard(void) |
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{ |
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printf("KARO TX25\n"); |
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return 0; |
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} |
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@ -1,6 +0,0 @@ |
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CONFIG_ARM=y |
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CONFIG_TARGET_TX25=y |
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CONFIG_SPL=y |
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# CONFIG_CMD_IMLS is not set |
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# CONFIG_CMD_FLASH is not set |
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# CONFIG_CMD_SETEXPR is not set |
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@ -1,172 +0,0 @@ |
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/*
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* (C) Copyright 2009 DENX Software Engineering |
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* Author: John Rigby <jrigby@gmail.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef __CONFIG_H |
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#define __CONFIG_H |
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#include <asm/arch/imx-regs.h> |
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/*
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* KARO TX25 board - SoC Configuration |
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*/ |
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#define CONFIG_MX25 |
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#define CONFIG_MX25_CLK32 32000 /* OSC32K frequency */ |
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#define CONFIG_SYS_TIMER_RATE CONFIG_MX25_CLK32 |
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#define CONFIG_SYS_TIMER_COUNTER \ |
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(&((struct gpt_regs *)IMX_GPT1_BASE)->counter) |
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#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* 256 kB for U-Boot */ |
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#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" |
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#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" |
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#define CONFIG_SPL_MAX_SIZE 2048 |
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#define CONFIG_SPL_NAND_SUPPORT |
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#define CONFIG_SPL_LIBGENERIC_SUPPORT |
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#define CONFIG_SPL_SERIAL_SUPPORT |
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#define CONFIG_SPL_TEXT_BASE 0x810c0000 |
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#define CONFIG_SYS_TEXT_BASE 0x81200000 |
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#ifndef MACH_TYPE_TX25 |
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#define MACH_TYPE_TX25 2177 |
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#endif |
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#define CONFIG_MACH_TYPE MACH_TYPE_TX25 |
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#ifdef CONFIG_SPL_BUILD |
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/* Start copying real U-boot from the second page */ |
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#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO |
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#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x30000 |
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#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE |
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST |
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#define CONFIG_SYS_NAND_PAGE_SIZE 2048 |
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#define CONFIG_SYS_NAND_OOBSIZE 64 |
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#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) |
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#define CONFIG_SYS_NAND_PAGE_COUNT 64 |
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#define CONFIG_SYS_NAND_SIZE (128 * 1024 * 1024) |
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#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 |
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#else |
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#define CONFIG_SKIP_LOWLEVEL_INIT |
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#endif |
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#define CONFIG_DISPLAY_CPUINFO |
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#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ |
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#define CONFIG_SETUP_MEMORY_TAGS |
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#define CONFIG_INITRD_TAG |
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/*
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* Memory Info |
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*/ |
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/* malloc() len */ |
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#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */ |
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/*
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* Board has 2 32MB banks of DRAM but there is a bug when using |
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* both so only the first is configured |
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*/ |
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#define CONFIG_NR_DRAM_BANKS 1 |
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#define PHYS_SDRAM_1 0x80000000 |
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#define PHYS_SDRAM_1_SIZE 0x02000000 |
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#if (CONFIG_NR_DRAM_BANKS == 2) |
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#define PHYS_SDRAM_2 0x90000000 |
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#define PHYS_SDRAM_2_SIZE 0x02000000 |
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#endif |
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/* 8MB DRAM test */ |
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#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 |
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#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1+0x0800000) |
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/*
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* Serial Info |
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*/ |
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#define CONFIG_MXC_UART |
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#define CONFIG_MXC_UART_BASE UART1_BASE |
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#define CONFIG_CONS_INDEX 1 /* use UART0 for console */ |
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#define CONFIG_BAUDRATE 115200 /* Default baud rate */ |
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#define CONFIG_MXC_GPIO |
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/*
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* Flash & Environment |
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*/ |
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/* No NOR flash present */ |
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#define CONFIG_SYS_NO_FLASH |
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#define CONFIG_ENV_IS_IN_NAND |
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#define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN |
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#define CONFIG_ENV_SIZE (128 * 1024) /* 128 kB NAND block size */ |
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#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) |
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/* NAND */ |
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#define CONFIG_NAND_MXC |
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#define CONFIG_MXC_NAND_REGS_BASE (0xBB000000) |
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#define CONFIG_SYS_MAX_NAND_DEVICE 1 |
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#define CONFIG_SYS_NAND_BASE (0xBB000000) |
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#define CONFIG_JFFS2_NAND |
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#define CONFIG_MXC_NAND_HWECC |
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#define CONFIG_SYS_NAND_LARGEPAGE |
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/* U-Boot general configuration */ |
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
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/* Print buffer sz */ |
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ |
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sizeof(CONFIG_SYS_PROMPT) + 16) |
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#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ |
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/* Boot Argument Buffer Size */ |
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
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#define CONFIG_CMDLINE_EDITING |
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#define CONFIG_SYS_LONGHELP |
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/* U-Boot commands */ |
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#define CONFIG_CMD_NAND |
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#define CONFIG_CMD_CACHE |
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/*
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* Ethernet |
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*/ |
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#define CONFIG_FEC_MXC |
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#define CONFIG_FEC_MXC_PHYADDR 0x1f |
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#define CONFIG_MII |
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#define CONFIG_BOARD_LATE_INIT |
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#define CONFIG_ENV_OVERWRITE |
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#define CONFIG_BOOTDELAY 5 |
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#define CONFIG_LOADADDR 0x81000000 /* loadaddr env var */ |
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#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR |
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#define CONFIG_EXTRA_ENV_SETTINGS \ |
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"netdev=eth0\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=${serverip}:${rootpath}\0" \
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"ramargs=setenv bootargs root=/dev/ram rw\0" \
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"addip=setenv bootargs ${bootargs} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
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":${hostname}:${netdev}:off panic=1\0" \
|
||||
"addtty=setenv bootargs ${bootargs}" \
|
||||
" console=ttymxc0,${baudrate}\0" \
|
||||
"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
|
||||
"addmisc=setenv bootargs ${bootargs}\0" \
|
||||
"u-boot=tx25/u-boot.bin\0" \
|
||||
"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
|
||||
"hostname=tx25\0" \
|
||||
"bootfile=tx25/uImage\0" \
|
||||
"rootpath=/opt/eldk/arm\0" \
|
||||
"net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
|
||||
"run nfsargs addip addtty addmtd addmisc;" \
|
||||
"bootm\0" \
|
||||
"bootcmd=run net_nfs\0" \
|
||||
"load=tftp ${loadaddr} ${u-boot}\0" \
|
||||
"update=nand erase 0 40000;nand write ${loadaddr} 0 40000\0" \
|
||||
"upd=run load update\0" \
|
||||
|
||||
/* additions for new relocation code, must be added to all boards */ |
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
||||
#define CONFIG_SYS_INIT_SP_ADDR (IMX_RAM_BASE + IMX_RAM_SIZE) |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
Loading…
Reference in new issue