The patch adds basic support for the Freescale's i.MX35 (arm1136 based) processor. The patch adds also a prototype for the initialization of the FEC(ethernet controller) to netdev.h to avoid warnings. Signed-off-by: Stefano Babic <sbabic@denx.de>master
Stefano Babic
14 years ago
committed by
Albert Aribaud
parent
d59140170a
commit
b9bb053159
@ -0,0 +1,63 @@ |
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(SOC).o
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COBJS += generic.o
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COBJS += timer.o
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COBJS += iomux.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
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all: $(obj).depend $(LIB) |
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$(LIB): $(OBJS) |
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$(call cmd_link_o_target, $(OBJS))
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$(OBJS) : $(TOPDIR)/include/asm/arch/asm-offsets.h |
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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$(TOPDIR)/include/asm/arch/asm-offsets.h: $(TOPDIR)/include/autoconf.mk.dep \
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./asm-offsets.s
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@echo Generating $@
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$(TOPDIR)/tools/scripts/make-asm-offsets ./asm-offsets.s $@
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asm-offsets.s: $(TOPDIR)/include/autoconf.mk.dep \
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./asm-offsets.c
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$(CC) -DDO_DEPS_ONLY \
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$(CFLAGS) $(CFLAGS_$(BCURDIR)/$(@F)) $(CFLAGS_$(BCURDIR)) \
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-o $@ ./asm-offsets.c -c -S
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@ -0,0 +1,43 @@ |
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/*
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* Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c |
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* |
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* This program is used to generate definitions needed by |
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* assembly language modules. |
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* |
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* We use the technique used in the OSF Mach kernel code: |
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* generate asm statements containing #defines, |
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* compile this file to assembler, and then extract the |
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* #defines from the assembly-language output. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License |
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* as published by the Free Software Foundation; either version |
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* 2 of the License, or (at your option) any later version. |
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*/ |
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#include <common.h> |
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#include <asm/arch/imx-regs.h> |
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#include <linux/kbuild.h> |
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int main(void) |
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{ |
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/* Round up to make sure size gives nice stack alignment */ |
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DEFINE(CLKCTL_CCMR, offsetof(struct ccm_regs, ccmr)); |
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DEFINE(CLKCTL_PDR0, offsetof(struct ccm_regs, pdr0)); |
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DEFINE(CLKCTL_PDR1, offsetof(struct ccm_regs, pdr1)); |
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DEFINE(CLKCTL_PDR2, offsetof(struct ccm_regs, pdr2)); |
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DEFINE(CLKCTL_PDR3, offsetof(struct ccm_regs, pdr3)); |
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DEFINE(CLKCTL_PDR4, offsetof(struct ccm_regs, pdr4)); |
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DEFINE(CLKCTL_RCSR, offsetof(struct ccm_regs, rcsr)); |
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DEFINE(CLKCTL_MPCTL, offsetof(struct ccm_regs, mpctl)); |
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DEFINE(CLKCTL_PPCTL, offsetof(struct ccm_regs, ppctl)); |
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DEFINE(CLKCTL_ACMR, offsetof(struct ccm_regs, acmr)); |
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DEFINE(CLKCTL_COSR, offsetof(struct ccm_regs, cosr)); |
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DEFINE(CLKCTL_CGR0, offsetof(struct ccm_regs, cgr0)); |
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DEFINE(CLKCTL_CGR1, offsetof(struct ccm_regs, cgr1)); |
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DEFINE(CLKCTL_CGR2, offsetof(struct ccm_regs, cgr2)); |
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return 0; |
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} |
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@ -0,0 +1,463 @@ |
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/*
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* (C) Copyright 2007 |
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* Sascha Hauer, Pengutronix |
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* |
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* (C) Copyright 2008-2010 Freescale Semiconductor, Inc. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <asm/io.h> |
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#include <asm/errno.h> |
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#include <asm/arch/imx-regs.h> |
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#include <asm/arch/crm_regs.h> |
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#include <asm/arch/clock.h> |
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#include <asm/arch/sys_proto.h> |
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#include <netdev.h> |
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#define CLK_CODE(arm, ahb, sel) (((arm) << 16) + ((ahb) << 8) + (sel)) |
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#define CLK_CODE_ARM(c) (((c) >> 16) & 0xFF) |
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#define CLK_CODE_AHB(c) (((c) >> 8) & 0xFF) |
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#define CLK_CODE_PATH(c) ((c) & 0xFF) |
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#define CCM_GET_DIVIDER(x, m, o) (((x) & (m)) >> (o)) |
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#ifdef CONFIG_FSL_ESDHC |
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DECLARE_GLOBAL_DATA_PTR; |
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#endif |
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static int g_clk_mux_auto[8] = { |
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CLK_CODE(1, 3, 0), CLK_CODE(1, 2, 1), CLK_CODE(2, 1, 1), -1, |
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CLK_CODE(1, 6, 0), CLK_CODE(1, 4, 1), CLK_CODE(2, 2, 1), -1, |
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}; |
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static int g_clk_mux_consumer[16] = { |
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CLK_CODE(1, 4, 0), CLK_CODE(1, 3, 1), CLK_CODE(1, 3, 1), -1, |
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-1, -1, CLK_CODE(4, 1, 0), CLK_CODE(1, 5, 0), |
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CLK_CODE(1, 8, 1), CLK_CODE(1, 6, 1), CLK_CODE(2, 4, 0), -1, |
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-1, -1, CLK_CODE(4, 2, 0), -1, |
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}; |
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static int hsp_div_table[3][16] = { |
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{4, 3, 2, -1, -1, -1, 1, 5, 4, 3, 2, -1, -1, -1, 1, -1}, |
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{-1, -1, -1, -1, -1, -1, -1, -1, 8, 6, 4, -1, -1, -1, 2, -1}, |
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{3, -1, -1, -1, -1, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1}, |
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}; |
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u32 get_cpu_rev(void) |
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{ |
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int reg; |
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struct iim_regs *iim = |
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(struct iim_regs *)IIM_BASE_ADDR; |
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reg = readl(&iim->iim_srev); |
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if (!reg) { |
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reg = readw(ROMPATCH_REV); |
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reg <<= 4; |
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} else { |
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reg += CHIP_REV_1_0; |
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} |
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return 0x35000 + (reg & 0xFF); |
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} |
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static u32 get_arm_div(u32 pdr0, u32 *fi, u32 *fd) |
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{ |
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int *pclk_mux; |
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if (pdr0 & MXC_CCM_PDR0_AUTO_CON) { |
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pclk_mux = g_clk_mux_consumer + |
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((pdr0 & MXC_CCM_PDR0_CON_MUX_DIV_MASK) >> |
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MXC_CCM_PDR0_CON_MUX_DIV_OFFSET); |
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} else { |
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pclk_mux = g_clk_mux_auto + |
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((pdr0 & MXC_CCM_PDR0_AUTO_MUX_DIV_MASK) >> |
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MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET); |
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} |
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if ((*pclk_mux) == -1) |
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return -1; |
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if (fi && fd) { |
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if (!CLK_CODE_PATH(*pclk_mux)) { |
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*fi = *fd = 1; |
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return CLK_CODE_ARM(*pclk_mux); |
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} |
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if (pdr0 & MXC_CCM_PDR0_AUTO_CON) { |
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*fi = 3; |
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*fd = 4; |
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} else { |
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*fi = 2; |
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*fd = 3; |
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} |
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} |
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return CLK_CODE_ARM(*pclk_mux); |
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} |
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static int get_ahb_div(u32 pdr0) |
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{ |
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int *pclk_mux; |
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pclk_mux = g_clk_mux_consumer + |
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((pdr0 & MXC_CCM_PDR0_CON_MUX_DIV_MASK) >> |
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MXC_CCM_PDR0_CON_MUX_DIV_OFFSET); |
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if ((*pclk_mux) == -1) |
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return -1; |
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return CLK_CODE_AHB(*pclk_mux); |
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} |
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static u32 decode_pll(u32 reg, u32 infreq) |
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{ |
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u32 mfi = (reg >> 10) & 0xf; |
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u32 mfn = reg & 0x3f; |
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u32 mfd = (reg >> 16) & 0x3f; |
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u32 pd = (reg >> 26) & 0xf; |
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mfi = mfi <= 5 ? 5 : mfi; |
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mfd += 1; |
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pd += 1; |
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return ((2 * (infreq / 1000) * (mfi * mfd + mfn)) / (mfd * pd)) * 1000; |
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} |
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static u32 get_mcu_main_clk(void) |
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{ |
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u32 arm_div = 0, fi = 0, fd = 0; |
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struct ccm_regs *ccm = |
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(struct ccm_regs *)IMX_CCM_BASE; |
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arm_div = get_arm_div(readl(&ccm->pdr0), &fi, &fd); |
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fi *= |
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decode_pll(readl(&ccm->mpctl), |
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CONFIG_MX35_HCLK_FREQ); |
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return fi / (arm_div * fd); |
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} |
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static u32 get_ipg_clk(void) |
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{ |
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u32 freq = get_mcu_main_clk(); |
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struct ccm_regs *ccm = |
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(struct ccm_regs *)IMX_CCM_BASE; |
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u32 pdr0 = readl(&ccm->pdr0); |
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return freq / (get_ahb_div(pdr0) * 2); |
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} |
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static u32 get_ipg_per_clk(void) |
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{ |
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u32 freq = get_mcu_main_clk(); |
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struct ccm_regs *ccm = |
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(struct ccm_regs *)IMX_CCM_BASE; |
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u32 pdr0 = readl(&ccm->pdr0); |
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u32 pdr4 = readl(&ccm->pdr4); |
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u32 div; |
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if (pdr0 & MXC_CCM_PDR0_PER_SEL) { |
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div = (CCM_GET_DIVIDER(pdr4, |
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MXC_CCM_PDR4_PER0_PRDF_MASK, |
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MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1) * |
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(CCM_GET_DIVIDER(pdr4, |
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MXC_CCM_PDR4_PER0_PODF_MASK, |
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MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1); |
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} else { |
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div = CCM_GET_DIVIDER(pdr0, |
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MXC_CCM_PDR0_PER_PODF_MASK, |
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MXC_CCM_PDR0_PER_PODF_OFFSET) + 1; |
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freq /= get_ahb_div(pdr0); |
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} |
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return freq / div; |
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} |
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u32 imx_get_uartclk(void) |
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{ |
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u32 freq; |
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struct ccm_regs *ccm = |
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(struct ccm_regs *)IMX_CCM_BASE; |
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u32 pdr4 = readl(&ccm->pdr4); |
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if (readl(&ccm->pdr3) & MXC_CCM_PDR3_UART_M_U) { |
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freq = get_mcu_main_clk(); |
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} else { |
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freq = decode_pll(readl(&ccm->ppctl), |
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CONFIG_MX35_HCLK_FREQ); |
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} |
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freq /= ((CCM_GET_DIVIDER(pdr4, |
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MXC_CCM_PDR4_UART_PRDF_MASK, |
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MXC_CCM_PDR4_UART_PRDF_OFFSET) + 1) * |
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(CCM_GET_DIVIDER(pdr4, |
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MXC_CCM_PDR4_UART_PODF_MASK, |
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MXC_CCM_PDR4_UART_PODF_OFFSET) + 1)); |
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return freq; |
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} |
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unsigned int mxc_get_main_clock(enum mxc_main_clocks clk) |
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{ |
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u32 nfc_pdf, hsp_podf; |
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u32 pll, ret_val = 0, usb_prdf, usb_podf; |
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struct ccm_regs *ccm = |
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(struct ccm_regs *)IMX_CCM_BASE; |
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u32 reg = readl(&ccm->pdr0); |
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u32 reg4 = readl(&ccm->pdr4); |
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reg |= 0x1; |
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switch (clk) { |
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case CPU_CLK: |
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ret_val = get_mcu_main_clk(); |
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break; |
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case AHB_CLK: |
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ret_val = get_mcu_main_clk(); |
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break; |
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case HSP_CLK: |
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if (reg & CLKMODE_CONSUMER) { |
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hsp_podf = (reg >> 20) & 0x3; |
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pll = get_mcu_main_clk(); |
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hsp_podf = hsp_div_table[hsp_podf][(reg>>16)&0xF]; |
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if (hsp_podf > 0) { |
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ret_val = pll / hsp_podf; |
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} else { |
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puts("mismatch HSP with ARM clock setting\n"); |
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ret_val = 0; |
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} |
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} else { |
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ret_val = get_mcu_main_clk(); |
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} |
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break; |
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case IPG_CLK: |
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ret_val = get_ipg_clk();; |
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break; |
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case IPG_PER_CLK: |
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ret_val = get_ipg_per_clk(); |
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break; |
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case NFC_CLK: |
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nfc_pdf = (reg4 >> 28) & 0xF; |
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pll = get_mcu_main_clk(); |
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/* AHB/nfc_pdf */ |
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ret_val = pll / (nfc_pdf + 1); |
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break; |
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case USB_CLK: |
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usb_prdf = (reg4 >> 25) & 0x7; |
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usb_podf = (reg4 >> 22) & 0x7; |
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if (reg4 & 0x200) { |
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pll = get_mcu_main_clk(); |
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} else { |
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pll = decode_pll(readl(&ccm->ppctl), |
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CONFIG_MX35_HCLK_FREQ); |
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} |
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ret_val = pll / ((usb_prdf + 1) * (usb_podf + 1)); |
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break; |
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default: |
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printf("Unknown clock: %d\n", clk); |
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break; |
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} |
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return ret_val; |
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} |
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unsigned int mxc_get_peri_clock(enum mxc_peri_clocks clk) |
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{ |
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u32 ret_val = 0, pdf, pre_pdf, clk_sel; |
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struct ccm_regs *ccm = |
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(struct ccm_regs *)IMX_CCM_BASE; |
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u32 mpdr2 = readl(&ccm->pdr2); |
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u32 mpdr3 = readl(&ccm->pdr3); |
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u32 mpdr4 = readl(&ccm->pdr4); |
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switch (clk) { |
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case UART1_BAUD: |
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case UART2_BAUD: |
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case UART3_BAUD: |
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clk_sel = mpdr3 & (1 << 14); |
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pre_pdf = (mpdr4 >> 13) & 0x7; |
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pdf = (mpdr4 >> 10) & 0x7; |
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ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : |
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decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / |
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((pre_pdf + 1) * (pdf + 1)); |
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break; |
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case SSI1_BAUD: |
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pre_pdf = (mpdr2 >> 24) & 0x7; |
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pdf = mpdr2 & 0x3F; |
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clk_sel = mpdr2 & (1 << 6); |
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ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : |
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decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / |
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((pre_pdf + 1) * (pdf + 1)); |
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break; |
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case SSI2_BAUD: |
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pre_pdf = (mpdr2 >> 27) & 0x7; |
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pdf = (mpdr2 >> 8) & 0x3F; |
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clk_sel = mpdr2 & (1 << 6); |
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ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : |
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decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / |
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((pre_pdf + 1) * (pdf + 1)); |
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break; |
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case CSI_BAUD: |
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clk_sel = mpdr2 & (1 << 7); |
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pre_pdf = (mpdr2 >> 16) & 0x7; |
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pdf = (mpdr2 >> 19) & 0x7; |
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ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : |
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decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / |
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((pre_pdf + 1) * (pdf + 1)); |
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break; |
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case MSHC_CLK: |
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pre_pdf = readl(&ccm->pdr1); |
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clk_sel = (pre_pdf & 0x80); |
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pdf = (pre_pdf >> 22) & 0x3F; |
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pre_pdf = (pre_pdf >> 28) & 0x7; |
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ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : |
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decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / |
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((pre_pdf + 1) * (pdf + 1)); |
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break; |
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case ESDHC1_CLK: |
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clk_sel = mpdr3 & 0x40; |
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pre_pdf = mpdr3 & 0x7; |
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pdf = (mpdr3>>3) & 0x7; |
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ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : |
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decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / |
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((pre_pdf + 1) * (pdf + 1)); |
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break; |
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case ESDHC2_CLK: |
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clk_sel = mpdr3 & 0x40; |
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pre_pdf = (mpdr3 >> 8) & 0x7; |
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pdf = (mpdr3 >> 11) & 0x7; |
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ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : |
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decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / |
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((pre_pdf + 1) * (pdf + 1)); |
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break; |
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case ESDHC3_CLK: |
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clk_sel = mpdr3 & 0x40; |
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pre_pdf = (mpdr3 >> 16) & 0x7; |
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pdf = (mpdr3 >> 19) & 0x7; |
||||
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : |
||||
decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / |
||||
((pre_pdf + 1) * (pdf + 1)); |
||||
break; |
||||
case SPDIF_CLK: |
||||
clk_sel = mpdr3 & 0x400000; |
||||
pre_pdf = (mpdr3 >> 29) & 0x7; |
||||
pdf = (mpdr3 >> 23) & 0x3F; |
||||
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : |
||||
decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / |
||||
((pre_pdf + 1) * (pdf + 1)); |
||||
break; |
||||
default: |
||||
printf("%s(): This clock: %d not supported yet\n", |
||||
__func__, clk); |
||||
break; |
||||
} |
||||
|
||||
return ret_val; |
||||
} |
||||
|
||||
unsigned int mxc_get_clock(enum mxc_clock clk) |
||||
{ |
||||
switch (clk) { |
||||
case MXC_ARM_CLK: |
||||
return get_mcu_main_clk(); |
||||
case MXC_AHB_CLK: |
||||
break; |
||||
case MXC_IPG_CLK: |
||||
return get_ipg_clk(); |
||||
case MXC_IPG_PERCLK: |
||||
return get_ipg_per_clk(); |
||||
case MXC_UART_CLK: |
||||
return imx_get_uartclk(); |
||||
case MXC_ESDHC_CLK: |
||||
return mxc_get_peri_clock(ESDHC1_CLK); |
||||
case MXC_USB_CLK: |
||||
return mxc_get_main_clock(USB_CLK); |
||||
case MXC_FEC_CLK: |
||||
return get_ipg_clk(); |
||||
case MXC_CSPI_CLK: |
||||
return get_ipg_clk(); |
||||
} |
||||
return -1; |
||||
} |
||||
|
||||
#ifdef CONFIG_FEC_MXC |
||||
/*
|
||||
* The MX35 has no fuse for MAC, return a NULL MAC |
||||
*/ |
||||
void imx_get_mac_from_fuse(unsigned char *mac) |
||||
{ |
||||
memset(mac, 0, 6); |
||||
} |
||||
|
||||
u32 imx_get_fecclk(void) |
||||
{ |
||||
return mxc_get_clock(MXC_IPG_CLK); |
||||
} |
||||
#endif |
||||
|
||||
int do_mx35_showclocks(cmd_tbl_t *cmdtp, |
||||
int flag, int argc, char * const argv[]) |
||||
{ |
||||
u32 cpufreq = get_mcu_main_clk(); |
||||
printf("mx35 cpu clock: %dMHz\n", cpufreq / 1000000); |
||||
printf("ipg clock : %dHz\n", get_ipg_clk()); |
||||
printf("ipg per clock : %dHz\n", get_ipg_per_clk()); |
||||
printf("uart clock : %dHz\n", mxc_get_clock(MXC_UART_CLK)); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
U_BOOT_CMD( |
||||
clockinfo, CONFIG_SYS_MAXARGS, 1, do_mx35_showclocks, |
||||
"display clocks\n", |
||||
"" |
||||
); |
||||
|
||||
#if defined(CONFIG_DISPLAY_CPUINFO) |
||||
int print_cpuinfo(void) |
||||
{ |
||||
printf("CPU: Freescale i.MX35 at %d MHz\n", |
||||
get_mcu_main_clk() / 1000000); |
||||
/* mxc_dump_clocks(); */ |
||||
return 0; |
||||
} |
||||
#endif |
||||
|
||||
/*
|
||||
* Initializes on-chip ethernet controllers. |
||||
* to override, implement board_eth_init() |
||||
*/ |
||||
|
||||
int cpu_eth_init(bd_t *bis) |
||||
{ |
||||
int rc = -ENODEV; |
||||
|
||||
#if defined(CONFIG_FEC_MXC) |
||||
rc = fecmxc_initialize(bis); |
||||
#endif |
||||
|
||||
return rc; |
||||
} |
||||
|
||||
int get_clocks(void) |
||||
{ |
||||
#ifdef CONFIG_FSL_ESDHC |
||||
gd->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); |
||||
#endif |
||||
return 0; |
||||
} |
||||
|
||||
void reset_cpu(ulong addr) |
||||
{ |
||||
struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR; |
||||
writew(4, &wdog->wcr); |
||||
} |
||||
@ -0,0 +1,116 @@ |
||||
/*
|
||||
* Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/io.h> |
||||
#include <asm/arch/imx-regs.h> |
||||
#include <asm/arch/mx35_pins.h> |
||||
#include <asm/arch/iomux.h> |
||||
|
||||
/*
|
||||
* IOMUX register (base) addresses |
||||
*/ |
||||
enum iomux_reg_addr { |
||||
IOMUXGPR = IOMUXC_BASE_ADDR, /* General purpose */ |
||||
IOMUXSW_MUX_CTL = IOMUXC_BASE_ADDR + 4, /* MUX control */ |
||||
IOMUXSW_MUX_END = IOMUXC_BASE_ADDR + 0x324, /* last MUX control */ |
||||
IOMUXSW_PAD_CTL = IOMUXC_BASE_ADDR + 0x328, /* Pad control */ |
||||
IOMUXSW_PAD_END = IOMUXC_BASE_ADDR + 0x794, /* last Pad control */ |
||||
IOMUXSW_INPUT_CTL = IOMUXC_BASE_ADDR + 0x7AC, /* input select */ |
||||
IOMUXSW_INPUT_END = IOMUXC_BASE_ADDR + 0x9F4, /* last input select */ |
||||
}; |
||||
|
||||
#define MUX_PIN_NUM_MAX \ |
||||
(((IOMUXSW_PAD_END - IOMUXSW_PAD_CTL) >> 2) + 1) |
||||
#define MUX_INPUT_NUM_MUX \ |
||||
(((IOMUXSW_INPUT_END - IOMUXSW_INPUT_CTL) >> 2) + 1) |
||||
|
||||
#define PIN_TO_IOMUX_INDEX(pin) ((PIN_TO_IOMUX_PAD(pin) - 0x328) >> 2) |
||||
|
||||
/*
|
||||
* Request ownership for an IO pin. This function has to be the first one |
||||
* being called before that pin is used. |
||||
*/ |
||||
void mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg) |
||||
{ |
||||
u32 mux_reg = PIN_TO_IOMUX_MUX(pin); |
||||
|
||||
if (mux_reg != NON_MUX_I) { |
||||
mux_reg += IOMUXGPR; |
||||
writel(cfg, mux_reg); |
||||
} |
||||
} |
||||
|
||||
/*
|
||||
* Release ownership for an IO pin |
||||
*/ |
||||
void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg) |
||||
{ |
||||
} |
||||
|
||||
/*
|
||||
* This function configures the pad value for a IOMUX pin. |
||||
* |
||||
* @param pin a pin number as defined in iomux_pin_name_t |
||||
* @param config the ORed value of elements defined in iomux_pad_config_t |
||||
*/ |
||||
void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config) |
||||
{ |
||||
u32 pad_reg = IOMUXGPR + PIN_TO_IOMUX_PAD(pin); |
||||
|
||||
writel(config, pad_reg); |
||||
} |
||||
|
||||
/*
|
||||
* This function enables/disables the general purpose function for a particular |
||||
* signal. |
||||
* |
||||
* @param gp one signal as defined in iomux_gp_func_t |
||||
* @param en enable/disable |
||||
*/ |
||||
void mxc_iomux_set_gpr(iomux_gp_func_t gp, int en) |
||||
{ |
||||
u32 l; |
||||
|
||||
l = readl(IOMUXGPR); |
||||
if (en) |
||||
l |= gp; |
||||
else |
||||
l &= ~gp; |
||||
|
||||
writel(l, IOMUXGPR); |
||||
} |
||||
|
||||
/*
|
||||
* This function configures input path. |
||||
* |
||||
* @param input index of input select register as defined in |
||||
* iomux_input_select_t |
||||
* @param config the binary value of elements defined in |
||||
* iomux_input_config_t |
||||
*/ |
||||
void mxc_iomux_set_input(iomux_input_select_t input, u32 config) |
||||
{ |
||||
u32 reg = IOMUXSW_INPUT_CTL + (input << 2); |
||||
|
||||
writel(config, reg); |
||||
} |
||||
@ -0,0 +1,120 @@ |
||||
/*
|
||||
* (C) Copyright 2007 |
||||
* Sascha Hauer, Pengutronix |
||||
* |
||||
* (C) Copyright 2008-2009 Freescale Semiconductor, Inc. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/io.h> |
||||
#include <asm/arch/imx-regs.h> |
||||
|
||||
/* General purpose timers bitfields */ |
||||
#define GPTCR_SWR (1<<15) /* Software reset */ |
||||
#define GPTCR_FRR (1<<9) /* Freerun / restart */ |
||||
#define GPTCR_CLKSOURCE_32 (0x100<<6) /* Clock source */ |
||||
#define GPTCR_CLKSOURCE_IPG (0x001<<6) /* Clock source */ |
||||
#define GPTCR_TEN (1) /* Timer enable */ |
||||
#define GPTPR_VAL (66) |
||||
|
||||
int timer_init(void) |
||||
{ |
||||
int i; |
||||
struct gpt_regs *gpt = (struct gpt_regs *)GPT1_BASE_ADDR; |
||||
|
||||
/* setup GP Timer 1 */ |
||||
writel(GPTCR_SWR, &gpt->ctrl); |
||||
for (i = 0; i < 100; i++) |
||||
writel(0, &gpt->ctrl); /* We have no udelay by now */ |
||||
|
||||
writel(GPTPR_VAL, &gpt->pre); |
||||
/* Freerun Mode, PERCLK1 input */ |
||||
writel(readl(&gpt->ctrl) | |
||||
GPTCR_CLKSOURCE_IPG | GPTCR_TEN, |
||||
&gpt->ctrl); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
void reset_timer_masked(void) |
||||
{ |
||||
struct gpt_regs *gpt = (struct gpt_regs *)GPT1_BASE_ADDR; |
||||
|
||||
writel(0, &gpt->ctrl); |
||||
/* Freerun Mode, PERCLK1 input */ |
||||
writel(GPTCR_CLKSOURCE_IPG | GPTCR_TEN, |
||||
&gpt->ctrl); |
||||
} |
||||
|
||||
inline ulong get_timer_masked(void) |
||||
{ |
||||
|
||||
struct gpt_regs *gpt = (struct gpt_regs *)GPT1_BASE_ADDR; |
||||
ulong val = readl(&gpt->counter); |
||||
|
||||
return val; |
||||
} |
||||
|
||||
void reset_timer(void) |
||||
{ |
||||
reset_timer_masked(); |
||||
} |
||||
|
||||
ulong get_timer(ulong base) |
||||
{ |
||||
ulong tmp; |
||||
|
||||
tmp = get_timer_masked(); |
||||
|
||||
if (tmp <= (base * 1000)) { |
||||
/* Overflow */ |
||||
tmp += (0xffffffff - base); |
||||
} |
||||
|
||||
return (tmp / 1000) - base; |
||||
} |
||||
|
||||
void set_timer(ulong t) |
||||
{ |
||||
} |
||||
|
||||
/*
|
||||
* delay x useconds AND preserve advance timstamp value |
||||
* GPTCNT is now supposed to tick 1 by 1 us. |
||||
*/ |
||||
void __udelay(unsigned long usec) |
||||
{ |
||||
ulong tmp; |
||||
|
||||
tmp = get_timer_masked(); /* get current timestamp */ |
||||
|
||||
/* if setting this forward will roll time stamp */ |
||||
if ((usec + tmp + 1) < tmp) { |
||||
/* reset "advancing" timestamp to 0, set lastinc value */ |
||||
reset_timer_masked(); |
||||
} else { |
||||
/* else, set advancing stamp wake up time */ |
||||
tmp += usec; |
||||
} |
||||
|
||||
while (get_timer_masked() < tmp) /* loop till event */ |
||||
/*NOP*/; |
||||
} |
||||
@ -0,0 +1,45 @@ |
||||
/*
|
||||
* (C) Copyright 2011 |
||||
* Stefano Babic, DENX Software Engineering, sbabic@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __ASM_ARCH_CLOCK_H |
||||
#define __ASM_ARCH_CLOCK_H |
||||
|
||||
enum mxc_clock { |
||||
MXC_ARM_CLK = 0, |
||||
MXC_AHB_CLK, |
||||
MXC_IPG_CLK, |
||||
MXC_IPG_PERCLK, |
||||
MXC_UART_CLK, |
||||
MXC_ESDHC_CLK, |
||||
MXC_USB_CLK, |
||||
MXC_CSPI_CLK, |
||||
MXC_FEC_CLK, |
||||
}; |
||||
|
||||
unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref); |
||||
|
||||
u32 imx_get_uartclk(void); |
||||
u32 imx_get_fecclk(void); |
||||
unsigned int mxc_get_clock(enum mxc_clock clk); |
||||
|
||||
#endif /* __ASM_ARCH_CLOCK_H */ |
||||
@ -0,0 +1,270 @@ |
||||
/*
|
||||
* Copyright 2004-2009 Freescale Semiconductor, Inc. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __CPU_ARM1136_MX35_CRM_REGS_H__ |
||||
#define __CPU_ARM1136_MX35_CRM_REGS_H__ |
||||
|
||||
/* Register bit definitions */ |
||||
#define MXC_CCM_CCMR_WFI (1 << 30) |
||||
#define MXC_CCM_CCMR_STBY_EXIT_SRC (1 << 29) |
||||
#define MXC_CCM_CCMR_VSTBY (1 << 28) |
||||
#define MXC_CCM_CCMR_WBEN (1 << 27) |
||||
#define MXC_CCM_CCMR_VOL_RDY_CNT_OFFSET 20 |
||||
#define MXC_CCM_CCMR_VOL_RDY_CNT_MASK (0xF << 20) |
||||
#define MXC_CCM_CCMR_ROMW_OFFSET 18 |
||||
#define MXC_CCM_CCMR_ROMW_MASK (0x3 << 18) |
||||
#define MXC_CCM_CCMR_RAMW_OFFSET 21 |
||||
#define MXC_CCM_CCMR_RAMW_MASK (0x3 << 21) |
||||
#define MXC_CCM_CCMR_LPM_OFFSET 14 |
||||
#define MXC_CCM_CCMR_LPM_MASK (0x3 << 14) |
||||
#define MXC_CCM_CCMR_UPE (1 << 9) |
||||
#define MXC_CCM_CCMR_MPE (1 << 3) |
||||
|
||||
#define MXC_CCM_PDR0_PER_SEL (1 << 26) |
||||
#define MXC_CCM_PDR0_IPU_HND_BYP (1 << 23) |
||||
#define MXC_CCM_PDR0_HSP_PODF_OFFSET 20 |
||||
#define MXC_CCM_PDR0_HSP_PODF_MASK (0x3 << 20) |
||||
#define MXC_CCM_PDR0_CON_MUX_DIV_OFFSET 16 |
||||
#define MXC_CCM_PDR0_CON_MUX_DIV_MASK (0xF << 16) |
||||
#define MXC_CCM_PDR0_CKIL_SEL (1 << 15) |
||||
#define MXC_CCM_PDR0_PER_PODF_OFFSET 12 |
||||
#define MXC_CCM_PDR0_PER_PODF_MASK (0xF << 12) |
||||
#define MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET 9 |
||||
#define MXC_CCM_PDR0_AUTO_MUX_DIV_MASK (0x7 << 9) |
||||
#define MXC_CCM_PDR0_AUTO_CON 0x1 |
||||
|
||||
#define MXC_CCM_PDR1_MSHC_PRDF_OFFSET 28 |
||||
#define MXC_CCM_PDR1_MSHC_PRDF_MASK (0x7 << 28) |
||||
#define MXC_CCM_PDR1_MSHC_PODF_OFFSET 22 |
||||
#define MXC_CCM_PDR1_MSHC_PODF_MASK (0x3F << 22) |
||||
#define MXC_CCM_PDR1_MSHC_M_U (1 << 7) |
||||
|
||||
#define MXC_CCM_PDR2_SSI2_PRDF_OFFSET 27 |
||||
#define MXC_CCM_PDR2_SSI2_PRDF_MASK (0x7 << 27) |
||||
#define MXC_CCM_PDR2_SSI1_PRDF_OFFSET 24 |
||||
#define MXC_CCM_PDR2_SSI1_PRDF_MASK (0x7 << 24) |
||||
#define MXC_CCM_PDR2_CSI_PRDF_OFFSET 19 |
||||
#define MXC_CCM_PDR2_CSI_PRDF_MASK (0x7 << 19) |
||||
#define MXC_CCM_PDR2_CSI_PODF_OFFSET 16 |
||||
#define MXC_CCM_PDR2_CSI_PODF_MASK (0x7 << 16) |
||||
#define MXC_CCM_PDR2_SSI2_PODF_OFFSET 8 |
||||
#define MXC_CCM_PDR2_SSI2_PODF_MASK (0x3F << 8) |
||||
#define MXC_CCM_PDR2_CSI_M_U (1 << 7) |
||||
#define MXC_CCM_PDR2_SSI_M_U (1 << 6) |
||||
#define MXC_CCM_PDR2_SSI1_PODF_OFFSET 0 |
||||
#define MXC_CCM_PDR2_SSI1_PODF_MASK (0x3F) |
||||
|
||||
#define MXC_CCM_PDR3_SPDIF_PRDF_OFFSET 29 |
||||
#define MXC_CCM_PDR3_SPDIF_PRDF_MASK (0x7 << 29) |
||||
#define MXC_CCM_PDR3_SPDIF_PODF_OFFSET 23 |
||||
#define MXC_CCM_PDR3_SPDIF_PODF_MASK (0x3F << 23) |
||||
#define MXC_CCM_PDR3_SPDIF_M_U (1 << 22) |
||||
#define MXC_CCM_PDR3_ESDHC3_PRDF_OFFSET 19 |
||||
#define MXC_CCM_PDR3_ESDHC3_PRDF_MASK (0x7 << 19) |
||||
#define MXC_CCM_PDR3_ESDHC3_PODF_OFFSET 16 |
||||
#define MXC_CCM_PDR3_ESDHC3_PODF_MASK (0x7 << 16) |
||||
#define MXC_CCM_PDR3_UART_M_U (1 << 15) |
||||
#define MXC_CCM_PDR3_ESDHC2_PRDF_OFFSET 11 |
||||
#define MXC_CCM_PDR3_ESDHC2_PRDF_MASK (0x7 << 11) |
||||
#define MXC_CCM_PDR3_ESDHC2_PODF_OFFSET 8 |
||||
#define MXC_CCM_PDR3_ESDHC2_PODF_MASK (0x7 << 8) |
||||
#define MXC_CCM_PDR3_ESDHC_M_U (1 << 6) |
||||
#define MXC_CCM_PDR3_ESDHC1_PRDF_OFFSET 3 |
||||
#define MXC_CCM_PDR3_ESDHC1_PRDF_MASK (0x7 << 3) |
||||
#define MXC_CCM_PDR3_ESDHC1_PODF_OFFSET 0 |
||||
#define MXC_CCM_PDR3_ESDHC1_PODF_MASK (0x7) |
||||
|
||||
#define MXC_CCM_PDR4_NFC_PODF_OFFSET 28 |
||||
#define MXC_CCM_PDR4_NFC_PODF_MASK (0xF << 28) |
||||
#define MXC_CCM_PDR4_USB_PRDF_OFFSET 25 |
||||
#define MXC_CCM_PDR4_USB_PRDF_MASK (0x7 << 25) |
||||
#define MXC_CCM_PDR4_USB_PODF_OFFSET 22 |
||||
#define MXC_CCM_PDR4_USB_PODF_MASK (0x7 << 22) |
||||
#define MXC_CCM_PDR4_PER0_PRDF_OFFSET 19 |
||||
#define MXC_CCM_PDR4_PER0_PRDF_MASK (0x7 << 19) |
||||
#define MXC_CCM_PDR4_PER0_PODF_OFFSET 16 |
||||
#define MXC_CCM_PDR4_PER0_PODF_MASK (0x7 << 16) |
||||
#define MXC_CCM_PDR4_UART_PRDF_OFFSET 13 |
||||
#define MXC_CCM_PDR4_UART_PRDF_MASK (0x7 << 13) |
||||
#define MXC_CCM_PDR4_UART_PODF_OFFSET 10 |
||||
#define MXC_CCM_PDR4_UART_PODF_MASK (0x7 << 10) |
||||
#define MXC_CCM_PDR4_USB_M_U (1 << 9) |
||||
|
||||
/* Bit definitions for RCSR */ |
||||
#define MXC_CCM_RCSR_BUS_WIDTH (1 << 29) |
||||
#define MXC_CCM_RCSR_BUS_16BIT (1 << 29) |
||||
#define MXC_CCM_RCSR_PAGE_SIZE (3 << 27) |
||||
#define MXC_CCM_RCSR_PAGE_512 (0 << 27) |
||||
#define MXC_CCM_RCSR_PAGE_2K (1 << 27) |
||||
#define MXC_CCM_RCSR_PAGE_4K1 (2 << 27) |
||||
#define MXC_CCM_RCSR_PAGE_4K2 (3 << 27) |
||||
#define MXC_CCM_RCSR_SOFT_RESET (1 << 15) |
||||
#define MXC_CCM_RCSR_NF16B (1 << 14) |
||||
#define MXC_CCM_RCSR_NFC_4K (1 << 9) |
||||
#define MXC_CCM_RCSR_NFC_FMS (1 << 8) |
||||
|
||||
/* Bit definitions for both MCU, PERIPHERAL PLL control registers */ |
||||
#define MXC_CCM_PCTL_BRM 0x80000000 |
||||
#define MXC_CCM_PCTL_PD_OFFSET 26 |
||||
#define MXC_CCM_PCTL_PD_MASK (0xF << 26) |
||||
#define MXC_CCM_PCTL_MFD_OFFSET 16 |
||||
#define MXC_CCM_PCTL_MFD_MASK (0x3FF << 16) |
||||
#define MXC_CCM_PCTL_MFI_OFFSET 10 |
||||
#define MXC_CCM_PCTL_MFI_MASK (0xF << 10) |
||||
#define MXC_CCM_PCTL_MFN_OFFSET 0 |
||||
#define MXC_CCM_PCTL_MFN_MASK 0x3FF |
||||
|
||||
/* Bit definitions for Audio clock mux register*/ |
||||
#define MXC_CCM_ACMR_ESAI_CLK_SEL_OFFSET 12 |
||||
#define MXC_CCM_ACMR_ESAI_CLK_SEL_MASK (0xF << 12) |
||||
#define MXC_CCM_ACMR_SPDIF_CLK_SEL_OFFSET 8 |
||||
#define MXC_CCM_ACMR_SPDIF_CLK_SEL_MASK (0xF << 8) |
||||
#define MXC_CCM_ACMR_SSI1_CLK_SEL_OFFSET 4 |
||||
#define MXC_CCM_ACMR_SSI1_CLK_SEL_MASK (0xF << 4) |
||||
#define MXC_CCM_ACMR_SSI2_CLK_SEL_OFFSET 0 |
||||
#define MXC_CCM_ACMR_SSI2_CLK_SEL_MASK (0xF << 0) |
||||
|
||||
/* Bit definitions for Clock gating Register*/ |
||||
#define MXC_CCM_CGR0_ASRC_OFFSET 0 |
||||
#define MXC_CCM_CGR0_ASRC_MASK (0x3 << 0) |
||||
#define MXC_CCM_CGR0_ATA_OFFSET 2 |
||||
#define MXC_CCM_CGR0_ATA_MASK (0x3 << 2) |
||||
#define MXC_CCM_CGR0_CAN1_OFFSET 6 |
||||
#define MXC_CCM_CGR0_CAN1_MASK (0x3 << 6) |
||||
#define MXC_CCM_CGR0_CAN2_OFFSET 8 |
||||
#define MXC_CCM_CGR0_CAN2_MASK (0x3 << 8) |
||||
#define MXC_CCM_CGR0_CSPI1_OFFSET 10 |
||||
#define MXC_CCM_CGR0_CSPI1_MASK (0x3 << 10) |
||||
#define MXC_CCM_CGR0_CSPI2_OFFSET 12 |
||||
#define MXC_CCM_CGR0_CSPI2_MASK (0x3 << 12) |
||||
#define MXC_CCM_CGR0_ECT_OFFSET 14 |
||||
#define MXC_CCM_CGR0_ECT_MASK (0x3 << 14) |
||||
#define MXC_CCM_CGR0_EDI0_OFFSET 16 |
||||
#define MXC_CCM_CGR0_EDI0_MASK (0x3 << 16) |
||||
#define MXC_CCM_CGR0_EMI_OFFSET 18 |
||||
#define MXC_CCM_CGR0_EMI_MASK (0x3 << 18) |
||||
#define MXC_CCM_CGR0_EPIT1_OFFSET 20 |
||||
#define MXC_CCM_CGR0_EPIT1_MASK (0x3 << 20) |
||||
#define MXC_CCM_CGR0_EPIT2_OFFSET 22 |
||||
#define MXC_CCM_CGR0_EPIT2_MASK (0x3 << 22) |
||||
#define MXC_CCM_CGR0_ESAI_OFFSET 24 |
||||
#define MXC_CCM_CGR0_ESAI_MASK (0x3 << 24) |
||||
#define MXC_CCM_CGR0_ESDHC1_OFFSET 26 |
||||
#define MXC_CCM_CGR0_ESDHC1_MASK (0x3 << 26) |
||||
#define MXC_CCM_CGR0_ESDHC2_OFFSET 28 |
||||
#define MXC_CCM_CGR0_ESDHC2_MASK (0x3 << 28) |
||||
#define MXC_CCM_CGR0_ESDHC3_OFFSET 30 |
||||
#define MXC_CCM_CGR0_ESDHC3_MASK (0x3 << 30) |
||||
|
||||
#define MXC_CCM_CGR1_FEC_OFFSET 0 |
||||
#define MXC_CCM_CGR1_FEC_MASK (0x3 << 0) |
||||
#define MXC_CCM_CGR1_GPIO1_OFFSET 2 |
||||
#define MXC_CCM_CGR1_GPIO1_MASK (0x3 << 2) |
||||
#define MXC_CCM_CGR1_GPIO2_OFFSET 4 |
||||
#define MXC_CCM_CGR1_GPIO2_MASK (0x3 << 4) |
||||
#define MXC_CCM_CGR1_GPIO3_OFFSET 6 |
||||
#define MXC_CCM_CGR1_GPIO3_MASK (0x3 << 6) |
||||
#define MXC_CCM_CGR1_GPT_OFFSET 8 |
||||
#define MXC_CCM_CGR1_GPT_MASK (0x3 << 8) |
||||
#define MXC_CCM_CGR1_I2C1_OFFSET 10 |
||||
#define MXC_CCM_CGR1_I2C1_MASK (0x3 << 10) |
||||
#define MXC_CCM_CGR1_I2C2_OFFSET 12 |
||||
#define MXC_CCM_CGR1_I2C2_MASK (0x3 << 12) |
||||
#define MXC_CCM_CGR1_I2C3_OFFSET 14 |
||||
#define MXC_CCM_CGR1_I2C3_MASK (0x3 << 14) |
||||
#define MXC_CCM_CGR1_IOMUXC_OFFSET 16 |
||||
#define MXC_CCM_CGR1_IOMUXC_MASK (0x3 << 16) |
||||
#define MXC_CCM_CGR1_IPU_OFFSET 18 |
||||
#define MXC_CCM_CGR1_IPU_MASK (0x3 << 18) |
||||
#define MXC_CCM_CGR1_KPP_OFFSET 20 |
||||
#define MXC_CCM_CGR1_KPP_MASK (0x3 << 20) |
||||
#define MXC_CCM_CGR1_MLB_OFFSET 22 |
||||
#define MXC_CCM_CGR1_MLB_MASK (0x3 << 22) |
||||
#define MXC_CCM_CGR1_MSHC_OFFSET 24 |
||||
#define MXC_CCM_CGR1_MSHC_MASK (0x3 << 24) |
||||
#define MXC_CCM_CGR1_OWIRE_OFFSET 26 |
||||
#define MXC_CCM_CGR1_OWIRE_MASK (0x3 << 26) |
||||
#define MXC_CCM_CGR1_PWM_OFFSET 28 |
||||
#define MXC_CCM_CGR1_PWM_MASK (0x3 << 28) |
||||
#define MXC_CCM_CGR1_RNGC_OFFSET 30 |
||||
#define MXC_CCM_CGR1_RNGC_MASK (0x3 << 30) |
||||
|
||||
#define MXC_CCM_CGR2_RTC_OFFSET 0 |
||||
#define MXC_CCM_CGR2_RTC_MASK (0x3 << 0) |
||||
#define MXC_CCM_CGR2_RTIC_OFFSET 2 |
||||
#define MXC_CCM_CGR2_RTIC_MASK (0x3 << 2) |
||||
#define MXC_CCM_CGR2_SCC_OFFSET 4 |
||||
#define MXC_CCM_CGR2_SCC_MASK (0x3 << 4) |
||||
#define MXC_CCM_CGR2_SDMA_OFFSET 6 |
||||
#define MXC_CCM_CGR2_SDMA_MASK (0x3 << 6) |
||||
#define MXC_CCM_CGR2_SPBA_OFFSET 8 |
||||
#define MXC_CCM_CGR2_SPBA_MASK (0x3 << 8) |
||||
#define MXC_CCM_CGR2_SPDIF_OFFSET 10 |
||||
#define MXC_CCM_CGR2_SPDIF_MASK (0x3 << 10) |
||||
#define MXC_CCM_CGR2_SSI1_OFFSET 12 |
||||
#define MXC_CCM_CGR2_SSI1_MASK (0x3 << 12) |
||||
#define MXC_CCM_CGR2_SSI2_OFFSET 14 |
||||
#define MXC_CCM_CGR2_SSI2_MASK (0x3 << 14) |
||||
#define MXC_CCM_CGR2_UART1_OFFSET 16 |
||||
#define MXC_CCM_CGR2_UART1_MASK (0x3 << 16) |
||||
#define MXC_CCM_CGR2_UART2_OFFSET 18 |
||||
#define MXC_CCM_CGR2_UART2_MASK (0x3 << 18) |
||||
#define MXC_CCM_CGR2_UART3_OFFSET 20 |
||||
#define MXC_CCM_CGR2_UART3_MASK (0x3 << 20) |
||||
#define MXC_CCM_CGR2_USBOTG_OFFSET 22 |
||||
#define MXC_CCM_CGR2_USBOTG_MASK (0x3 << 22) |
||||
#define MXC_CCM_CGR2_WDOG_OFFSET 24 |
||||
#define MXC_CCM_CGR2_WDOG_MASK (0x3 << 24) |
||||
#define MXC_CCM_CGR2_MAX_OFFSET 26 |
||||
#define MXC_CCM_CGR2_MAX_MASK (0x3 << 26) |
||||
#define MXC_CCM_CGR2_MAX_ENABLE (0x2 << 26) |
||||
#define MXC_CCM_CGR2_AUDMUX_OFFSET 30 |
||||
#define MXC_CCM_CGR2_AUDMUX_MASK (0x3 << 30) |
||||
|
||||
#define MXC_CCM_CGR3_CSI_OFFSET 0 |
||||
#define MXC_CCM_CGR3_CSI_MASK (0x3 << 0) |
||||
#define MXC_CCM_CGR3_IIM_OFFSET 2 |
||||
#define MXC_CCM_CGR3_IIM_MASK (0x3 << 2) |
||||
#define MXC_CCM_CGR3_GPU2D_OFFSET 4 |
||||
#define MXC_CCM_CGR3_GPU2D_MASK (0x3 << 4) |
||||
|
||||
#define MXC_CCM_COSR_CLKOSEL_MASK 0x1F |
||||
#define MXC_CCM_COSR_CLKOSEL_OFFSET 0 |
||||
#define MXC_CCM_COSR_CLKOEN (1 << 5) |
||||
#define MXC_CCM_COSR_CLKOUTDIV_1 (1 << 6) |
||||
#define MXC_CCM_COSR_CLKOUT_PREDIV_MASK (0x7 << 10) |
||||
#define MXC_CCM_COSR_CLKOUT_PREDIV_OFFSET 10 |
||||
#define MXC_CCM_COSR_CLKOUT_PRODIV_MASK (0x7 << 13) |
||||
#define MXC_CCM_COSR_CLKOUT_PRODIV_OFFSET 13 |
||||
#define MXC_CCM_COSR_SSI1_RX_SRC_SEL_MASK (0x3 << 16) |
||||
#define MXC_CCM_COSR_SSI1_RX_SRC_SEL_OFFSET 16 |
||||
#define MXC_CCM_COSR_SSI1_TX_SRC_SEL_MASK (0x3 << 18) |
||||
#define MXC_CCM_COSR_SSI1_TX_SRC_SEL_OFFSET 18 |
||||
#define MXC_CCM_COSR_SSI2_RX_SRC_SEL_MASK (0x3 << 20) |
||||
#define MXC_CCM_COSR_SSI2_RX_SRC_SEL_OFFSET 20 |
||||
#define MXC_CCM_COSR_SSI2_TX_SRC_SEL_MASK (0x3 << 22) |
||||
#define MXC_CCM_COSR_SSI2_TX_SRC_SEL_OFFSET 22 |
||||
#define MXC_CCM_COSR_ASRC_AUDIO_EN (1 << 24) |
||||
#define MXC_CCM_COSR_ASRC_AUDIO_PODF_MASK (0x3F << 26) |
||||
#define MXC_CCM_COSR_ASRC_AUDIO_PODF_OFFSET 26 |
||||
|
||||
#endif |
||||
@ -0,0 +1,291 @@ |
||||
/*
|
||||
* (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> |
||||
* |
||||
* (C) Copyright 2008-2009 Freescale Semiconductor, Inc. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __ASM_ARCH_MX35_H |
||||
#define __ASM_ARCH_MX35_H |
||||
|
||||
/*
|
||||
* IRAM |
||||
*/ |
||||
#define IRAM_BASE_ADDR 0x10000000 /* internal ram */ |
||||
#define IRAM_SIZE 0x00020000 /* 128 KB */ |
||||
|
||||
/*
|
||||
* AIPS 1 |
||||
*/ |
||||
#define AIPS1_BASE_ADDR 0x43F00000 |
||||
#define AIPS1_CTRL_BASE_ADDR AIPS1_BASE_ADDR |
||||
#define MAX_BASE_ADDR 0x43F04000 |
||||
#define EVTMON_BASE_ADDR 0x43F08000 |
||||
#define CLKCTL_BASE_ADDR 0x43F0C000 |
||||
#define I2C_BASE_ADDR 0x43F80000 |
||||
#define I2C3_BASE_ADDR 0x43F84000 |
||||
#define ATA_BASE_ADDR 0x43F8C000 |
||||
#define UART1_BASE_ADDR 0x43F90000 |
||||
#define UART2_BASE_ADDR 0x43F94000 |
||||
#define I2C2_BASE_ADDR 0x43F98000 |
||||
#define CSPI1_BASE_ADDR 0x43FA4000 |
||||
#define IOMUXC_BASE_ADDR 0x43FAC000 |
||||
|
||||
/*
|
||||
* SPBA |
||||
*/ |
||||
#define SPBA_BASE_ADDR 0x50000000 |
||||
#define UART3_BASE_ADDR 0x5000C000 |
||||
#define CSPI2_BASE_ADDR 0x50010000 |
||||
#define ATA_DMA_BASE_ADDR 0x50020000 |
||||
#define FEC_BASE_ADDR 0x50038000 |
||||
#define SPBA_CTRL_BASE_ADDR 0x5003C000 |
||||
|
||||
/*
|
||||
* AIPS 2 |
||||
*/ |
||||
#define AIPS2_BASE_ADDR 0x53F00000 |
||||
#define AIPS2_CTRL_BASE_ADDR AIPS2_BASE_ADDR |
||||
#define CCM_BASE_ADDR 0x53F80000 |
||||
#define GPT1_BASE_ADDR 0x53F90000 |
||||
#define EPIT1_BASE_ADDR 0x53F94000 |
||||
#define EPIT2_BASE_ADDR 0x53F98000 |
||||
#define GPIO3_BASE_ADDR 0x53FA4000 |
||||
#define MMC_SDHC1_BASE_ADDR 0x53FB4000 |
||||
#define MMC_SDHC2_BASE_ADDR 0x53FB8000 |
||||
#define MMC_SDHC3_BASE_ADDR 0x53FBC000 |
||||
#define IPU_CTRL_BASE_ADDR 0x53FC0000 |
||||
#define GPIO3_BASE_ADDR 0x53FA4000 |
||||
#define GPIO1_BASE_ADDR 0x53FCC000 |
||||
#define GPIO2_BASE_ADDR 0x53FD0000 |
||||
#define SDMA_BASE_ADDR 0x53FD4000 |
||||
#define RTC_BASE_ADDR 0x53FD8000 |
||||
#define WDOG_BASE_ADDR 0x53FDC000 |
||||
#define PWM_BASE_ADDR 0x53FE0000 |
||||
#define RTIC_BASE_ADDR 0x53FEC000 |
||||
#define IIM_BASE_ADDR 0x53FF0000 |
||||
|
||||
#define IMX_CCM_BASE CCM_BASE_ADDR |
||||
|
||||
/*
|
||||
* ROMPATCH and AVIC |
||||
*/ |
||||
#define ROMPATCH_BASE_ADDR 0x60000000 |
||||
#define AVIC_BASE_ADDR 0x68000000 |
||||
|
||||
/*
|
||||
* NAND, SDRAM, WEIM, M3IF, EMI controllers |
||||
*/ |
||||
#define EXT_MEM_CTRL_BASE 0xB8000000 |
||||
#define ESDCTL_BASE_ADDR 0xB8001000 |
||||
#define WEIM_BASE_ADDR 0xB8002000 |
||||
#define WEIM_CTRL_CS0 WEIM_BASE_ADDR |
||||
#define WEIM_CTRL_CS1 (WEIM_BASE_ADDR + 0x10) |
||||
#define WEIM_CTRL_CS2 (WEIM_BASE_ADDR + 0x20) |
||||
#define WEIM_CTRL_CS3 (WEIM_BASE_ADDR + 0x30) |
||||
#define WEIM_CTRL_CS4 (WEIM_BASE_ADDR + 0x40) |
||||
#define WEIM_CTRL_CS5 (WEIM_BASE_ADDR + 0x50) |
||||
#define M3IF_BASE_ADDR 0xB8003000 |
||||
#define EMI_BASE_ADDR 0xB8004000 |
||||
|
||||
#define NFC_BASE_ADDR 0xBB000000 |
||||
|
||||
/*
|
||||
* Memory regions and CS |
||||
*/ |
||||
#define IPU_MEM_BASE_ADDR 0x70000000 |
||||
#define CSD0_BASE_ADDR 0x80000000 |
||||
#define CSD1_BASE_ADDR 0x90000000 |
||||
#define CS0_BASE_ADDR 0xA0000000 |
||||
#define CS1_BASE_ADDR 0xA8000000 |
||||
#define CS2_BASE_ADDR 0xB0000000 |
||||
#define CS3_BASE_ADDR 0xB2000000 |
||||
#define CS4_BASE_ADDR 0xB4000000 |
||||
#define CS5_BASE_ADDR 0xB6000000 |
||||
|
||||
/*
|
||||
* IRQ Controller Register Definitions. |
||||
*/ |
||||
#define AVIC_NIMASK 0x04 |
||||
#define AVIC_INTTYPEH 0x18 |
||||
#define AVIC_INTTYPEL 0x1C |
||||
|
||||
/* L210 */ |
||||
#define L2CC_BASE_ADDR 0x30000000 |
||||
#define L2_CACHE_LINE_SIZE 32 |
||||
#define L2_CACHE_CTL_REG 0x100 |
||||
#define L2_CACHE_AUX_CTL_REG 0x104 |
||||
#define L2_CACHE_SYNC_REG 0x730 |
||||
#define L2_CACHE_INV_LINE_REG 0x770 |
||||
#define L2_CACHE_INV_WAY_REG 0x77C |
||||
#define L2_CACHE_CLEAN_LINE_REG 0x7B0 |
||||
#define L2_CACHE_CLEAN_INV_LINE_REG 0x7F0 |
||||
#define L2_CACHE_DBG_CTL_REG 0xF40 |
||||
|
||||
#define CLKMODE_AUTO 0 |
||||
#define CLKMODE_CONSUMER 1 |
||||
|
||||
#define PLL_PD(x) (((x) & 0xf) << 26) |
||||
#define PLL_MFD(x) (((x) & 0x3ff) << 16) |
||||
#define PLL_MFI(x) (((x) & 0xf) << 10) |
||||
#define PLL_MFN(x) (((x) & 0x3ff) << 0) |
||||
|
||||
#define CSCR_U(x) (WEIM_CTRL_CS#x + 0) |
||||
#define CSCR_L(x) (WEIM_CTRL_CS#x + 4) |
||||
#define CSCR_A(x) (WEIM_CTRL_CS#x + 8) |
||||
|
||||
#define IIM_SREV 0x24 |
||||
#define ROMPATCH_REV 0x40 |
||||
|
||||
#define IPU_CONF IPU_CTRL_BASE_ADDR |
||||
|
||||
#define IPU_CONF_PXL_ENDIAN (1<<8) |
||||
#define IPU_CONF_DU_EN (1<<7) |
||||
#define IPU_CONF_DI_EN (1<<6) |
||||
#define IPU_CONF_ADC_EN (1<<5) |
||||
#define IPU_CONF_SDC_EN (1<<4) |
||||
#define IPU_CONF_PF_EN (1<<3) |
||||
#define IPU_CONF_ROT_EN (1<<2) |
||||
#define IPU_CONF_IC_EN (1<<1) |
||||
#define IPU_CONF_SCI_EN (1<<0) |
||||
|
||||
#define GPIO_PORT_NUM 3 |
||||
#define GPIO_NUM_PIN 32 |
||||
|
||||
#define CHIP_REV_1_0 0x10 |
||||
#define CHIP_REV_2_0 0x20 |
||||
|
||||
#define BOARD_REV_1_0 0x0 |
||||
#define BOARD_REV_2_0 0x1 |
||||
|
||||
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) |
||||
#include <asm/types.h> |
||||
|
||||
extern void imx_get_mac_from_fuse(unsigned char *mac); |
||||
|
||||
enum mxc_main_clocks { |
||||
CPU_CLK, |
||||
AHB_CLK, |
||||
IPG_CLK, |
||||
IPG_PER_CLK, |
||||
NFC_CLK, |
||||
USB_CLK, |
||||
HSP_CLK, |
||||
}; |
||||
|
||||
enum mxc_peri_clocks { |
||||
UART1_BAUD, |
||||
UART2_BAUD, |
||||
UART3_BAUD, |
||||
SSI1_BAUD, |
||||
SSI2_BAUD, |
||||
CSI_BAUD, |
||||
MSHC_CLK, |
||||
ESDHC1_CLK, |
||||
ESDHC2_CLK, |
||||
ESDHC3_CLK, |
||||
SPDIF_CLK, |
||||
SPI1_CLK, |
||||
SPI2_CLK, |
||||
}; |
||||
|
||||
/* Clock Control Module (CCM) registers */ |
||||
struct ccm_regs { |
||||
u32 ccmr; /* Control */ |
||||
u32 pdr0; /* Post divider 0 */ |
||||
u32 pdr1; /* Post divider 1 */ |
||||
u32 pdr2; /* Post divider 2 */ |
||||
u32 pdr3; /* Post divider 3 */ |
||||
u32 pdr4; /* Post divider 4 */ |
||||
u32 rcsr; /* CCM Status */ |
||||
u32 mpctl; /* Core PLL Control */ |
||||
u32 ppctl; /* Peripheral PLL Control */ |
||||
u32 acmr; /* Audio clock mux */ |
||||
u32 cosr; /* Clock out source */ |
||||
u32 cgr0; /* Clock Gating Control 0 */ |
||||
u32 cgr1; /* Clock Gating Control 1 */ |
||||
u32 cgr2; /* Clock Gating Control 2 */ |
||||
u32 cgr3; /* Clock Gating Control 3 */ |
||||
u32 reserved; |
||||
u32 dcvr0; /* DPTC Comparator 0 */ |
||||
u32 dcvr1; /* DPTC Comparator 0 */ |
||||
u32 dcvr2; /* DPTC Comparator 0 */ |
||||
u32 dcvr3; /* DPTC Comparator 0 */ |
||||
u32 ltr0; /* Load Tracking 0 */ |
||||
u32 ltr1; /* Load Tracking 1 */ |
||||
u32 ltr2; /* Load Tracking 2 */ |
||||
u32 ltr3; /* Load Tracking 3 */ |
||||
u32 ltbr0; /* Load Tracking Buffer 0 */ |
||||
}; |
||||
|
||||
/* IIM control registers */ |
||||
struct iim_regs { |
||||
u32 iim_stat; |
||||
u32 iim_statm; |
||||
u32 iim_err; |
||||
u32 iim_emask; |
||||
u32 iim_fctl; |
||||
u32 iim_ua; |
||||
u32 iim_la; |
||||
u32 iim_sdat; |
||||
u32 iim_prev; |
||||
u32 iim_srev; |
||||
u32 iim_prog_p; |
||||
u32 iim_scs0; |
||||
u32 iim_scs1; |
||||
u32 iim_scs2; |
||||
u32 iim_scs3; |
||||
}; |
||||
|
||||
/* General Purpose Timer (GPT) registers */ |
||||
struct gpt_regs { |
||||
u32 ctrl; /* control */ |
||||
u32 pre; /* prescaler */ |
||||
u32 stat; /* status */ |
||||
u32 intr; /* interrupt */ |
||||
u32 cmp[3]; /* output compare 1-3 */ |
||||
u32 capt[2]; /* input capture 1-2 */ |
||||
u32 counter; /* counter */ |
||||
}; |
||||
|
||||
/* Watchdog Timer (WDOG) registers */ |
||||
struct wdog_regs { |
||||
u16 wcr; /* Control */ |
||||
u16 wsr; /* Service */ |
||||
u16 wrsr; /* Reset Status */ |
||||
u16 wicr; /* Interrupt Control */ |
||||
u16 wmcr; /* Misc Control */ |
||||
}; |
||||
|
||||
/*
|
||||
* NFMS bit in RCSR register for pagesize of nandflash |
||||
*/ |
||||
#define NFMS_BIT 8 |
||||
#define NFMS_NF_DWIDTH 14 |
||||
#define NFMS_NF_PG_SZ 8 |
||||
|
||||
#define CCM_RCSR_NF_16BIT_SEL (1 << 14) |
||||
|
||||
extern unsigned int get_board_rev(void); |
||||
extern int is_soc_rev(int rev); |
||||
extern int sdhc_init(void); |
||||
|
||||
#endif |
||||
#endif /* __ASM_ARCH_MX35_H */ |
||||
@ -0,0 +1,295 @@ |
||||
/*
|
||||
* (C) Copyright 2011 |
||||
* Stefano Babic, DENX Software Engineering, sbabic@denx.de. |
||||
* |
||||
* Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __MACH_MX35_IOMUX_H__ |
||||
#define __MACH_MX35_IOMUX_H__ |
||||
|
||||
#include <asm/arch/imx-regs.h> |
||||
|
||||
/*
|
||||
* various IOMUX functions |
||||
*/ |
||||
typedef enum iomux_pin_config { |
||||
MUX_CONFIG_FUNC = 0, /* used as function */ |
||||
MUX_CONFIG_ALT1, /* used as alternate function 1 */ |
||||
MUX_CONFIG_ALT2, /* used as alternate function 2 */ |
||||
MUX_CONFIG_ALT3, /* used as alternate function 3 */ |
||||
MUX_CONFIG_ALT4, /* used as alternate function 4 */ |
||||
MUX_CONFIG_ALT5, /* used as alternate function 5 */ |
||||
MUX_CONFIG_ALT6, /* used as alternate function 6 */ |
||||
MUX_CONFIG_ALT7, /* used as alternate function 7 */ |
||||
MUX_CONFIG_SION = 0x1 << 4, /* used as LOOPBACK:MUX SION bit */ |
||||
MUX_CONFIG_GPIO = MUX_CONFIG_ALT5, /* used as GPIO */ |
||||
} iomux_pin_cfg_t; |
||||
|
||||
/*
|
||||
* various IOMUX pad functions |
||||
*/ |
||||
typedef enum iomux_pad_config { |
||||
PAD_CTL_DRV_3_3V = 0x0 << 13, |
||||
PAD_CTL_DRV_1_8V = 0x1 << 13, |
||||
PAD_CTL_HYS_CMOS = 0x0 << 8, |
||||
PAD_CTL_HYS_SCHMITZ = 0x1 << 8, |
||||
PAD_CTL_PKE_NONE = 0x0 << 7, |
||||
PAD_CTL_PKE_ENABLE = 0x1 << 7, |
||||
PAD_CTL_PUE_KEEPER = 0x0 << 6, |
||||
PAD_CTL_PUE_PUD = 0x1 << 6, |
||||
PAD_CTL_100K_PD = 0x0 << 4, |
||||
PAD_CTL_47K_PU = 0x1 << 4, |
||||
PAD_CTL_100K_PU = 0x2 << 4, |
||||
PAD_CTL_22K_PU = 0x3 << 4, |
||||
PAD_CTL_ODE_CMOS = 0x0 << 3, |
||||
PAD_CTL_ODE_OpenDrain = 0x1 << 3, |
||||
PAD_CTL_DRV_NORMAL = 0x0 << 1, |
||||
PAD_CTL_DRV_HIGH = 0x1 << 1, |
||||
PAD_CTL_DRV_MAX = 0x2 << 1, |
||||
PAD_CTL_SRE_SLOW = 0x0 << 0, |
||||
PAD_CTL_SRE_FAST = 0x1 << 0 |
||||
} iomux_pad_config_t; |
||||
|
||||
/*
|
||||
* various IOMUX general purpose functions |
||||
*/ |
||||
typedef enum iomux_gp_func { |
||||
MUX_SDCTL_CSD0_SEL = 0x1 << 0, |
||||
MUX_SDCTL_CSD1_SEL = 0x1 << 1, |
||||
MUX_TAMPER_DETECT_EN = 0x1 << 2, |
||||
} iomux_gp_func_t; |
||||
|
||||
/*
|
||||
* various IOMUX input select register index |
||||
*/ |
||||
typedef enum iomux_input_select { |
||||
MUX_IN_AMX_P5_RXCLK = 0, |
||||
MUX_IN_AMX_P5_RXFS, |
||||
MUX_IN_AMX_P6_DA, |
||||
MUX_IN_AMX_P6_DB, |
||||
MUX_IN_AMX_P6_RXCLK, |
||||
MUX_IN_AMX_P6_RXFS, |
||||
MUX_IN_AMX_P6_TXCLK, |
||||
MUX_IN_AMX_P6_TXFS, |
||||
MUX_IN_CAN1_CANRX, |
||||
MUX_IN_CAN2_CANRX, |
||||
MUX_IN_CCM_32K_MUXED, |
||||
MUX_IN_CCM_PMIC_RDY, |
||||
MUX_IN_CSPI1_SS2_B, |
||||
MUX_IN_CSPI1_SS3_B, |
||||
MUX_IN_CSPI2_CLK_IN, |
||||
MUX_IN_CSPI2_DATAREADY_B, |
||||
MUX_IN_CSPI2_MISO, |
||||
MUX_IN_CSPI2_MOSI, |
||||
MUX_IN_CSPI2_SS0_B, |
||||
MUX_IN_CSPI2_SS1_B, |
||||
MUX_IN_CSPI2_SS2_B, |
||||
MUX_IN_CSPI2_SS3_B, |
||||
MUX_IN_EMI_WEIM_DTACK_B, |
||||
MUX_IN_ESDHC1_DAT4_IN, |
||||
MUX_IN_ESDHC1_DAT5_IN, |
||||
MUX_IN_ESDHC1_DAT6_IN, |
||||
MUX_IN_ESDHC1_DAT7_IN, |
||||
MUX_IN_ESDHC3_CARD_CLK_IN, |
||||
MUX_IN_ESDHC3_CMD_IN, |
||||
MUX_IN_ESDHC3_DAT0, |
||||
MUX_IN_ESDHC3_DAT1, |
||||
MUX_IN_ESDHC3_DAT2, |
||||
MUX_IN_ESDHC3_DAT3, |
||||
MUX_IN_GPIO1_IN_0, |
||||
MUX_IN_GPIO1_IN_10, |
||||
MUX_IN_GPIO1_IN_11, |
||||
MUX_IN_GPIO1_IN_1, |
||||
MUX_IN_GPIO1_IN_20, |
||||
MUX_IN_GPIO1_IN_21, |
||||
MUX_IN_GPIO1_IN_22, |
||||
MUX_IN_GPIO1_IN_2, |
||||
MUX_IN_GPIO1_IN_3, |
||||
MUX_IN_GPIO1_IN_4, |
||||
MUX_IN_GPIO1_IN_5, |
||||
MUX_IN_GPIO1_IN_6, |
||||
MUX_IN_GPIO1_IN_7, |
||||
MUX_IN_GPIO1_IN_8, |
||||
MUX_IN_GPIO1_IN_9, |
||||
MUX_IN_GPIO2_IN_0, |
||||
MUX_IN_GPIO2_IN_10, |
||||
MUX_IN_GPIO2_IN_11, |
||||
MUX_IN_GPIO2_IN_12, |
||||
MUX_IN_GPIO2_IN_13, |
||||
MUX_IN_GPIO2_IN_14, |
||||
MUX_IN_GPIO2_IN_15, |
||||
MUX_IN_GPIO2_IN_16, |
||||
MUX_IN_GPIO2_IN_17, |
||||
MUX_IN_GPIO2_IN_18, |
||||
MUX_IN_GPIO2_IN_19, |
||||
MUX_IN_GPIO2_IN_20, |
||||
MUX_IN_GPIO2_IN_21, |
||||
MUX_IN_GPIO2_IN_22, |
||||
MUX_IN_GPIO2_IN_23, |
||||
MUX_IN_GPIO2_IN_24, |
||||
MUX_IN_GPIO2_IN_25, |
||||
MUX_IN_GPIO2_IN_26, |
||||
MUX_IN_GPIO2_IN_27, |
||||
MUX_IN_GPIO2_IN_28, |
||||
MUX_IN_GPIO2_IN_29, |
||||
MUX_IN_GPIO2_IN_2, |
||||
MUX_IN_GPIO2_IN_30, |
||||
MUX_IN_GPIO2_IN_31, |
||||
MUX_IN_GPIO2_IN_3, |
||||
MUX_IN_GPIO2_IN_4, |
||||
MUX_IN_GPIO2_IN_5, |
||||
MUX_IN_GPIO2_IN_6, |
||||
MUX_IN_GPIO2_IN_7, |
||||
MUX_IN_GPIO2_IN_8, |
||||
MUX_IN_GPIO2_IN_9, |
||||
MUX_IN_GPIO3_IN_0, |
||||
MUX_IN_GPIO3_IN_10, |
||||
MUX_IN_GPIO3_IN_11, |
||||
MUX_IN_GPIO3_IN_12, |
||||
MUX_IN_GPIO3_IN_13, |
||||
MUX_IN_GPIO3_IN_14, |
||||
MUX_IN_GPIO3_IN_15, |
||||
MUX_IN_GPIO3_IN_4, |
||||
MUX_IN_GPIO3_IN_5, |
||||
MUX_IN_GPIO3_IN_6, |
||||
MUX_IN_GPIO3_IN_7, |
||||
MUX_IN_GPIO3_IN_8, |
||||
MUX_IN_GPIO3_IN_9, |
||||
MUX_IN_I2C3_SCL_IN, |
||||
MUX_IN_I2C3_SDA_IN, |
||||
MUX_IN_IPU_DISPB_D0_VSYNC, |
||||
MUX_IN_IPU_DISPB_D12_VSYNC, |
||||
MUX_IN_IPU_DISPB_SD_D, |
||||
MUX_IN_IPU_SENSB_DATA_0, |
||||
MUX_IN_IPU_SENSB_DATA_1, |
||||
MUX_IN_IPU_SENSB_DATA_2, |
||||
MUX_IN_IPU_SENSB_DATA_3, |
||||
MUX_IN_IPU_SENSB_DATA_4, |
||||
MUX_IN_IPU_SENSB_DATA_5, |
||||
MUX_IN_IPU_SENSB_DATA_6, |
||||
MUX_IN_IPU_SENSB_DATA_7, |
||||
MUX_IN_KPP_COL_0, |
||||
MUX_IN_KPP_COL_1, |
||||
MUX_IN_KPP_COL_2, |
||||
MUX_IN_KPP_COL_3, |
||||
MUX_IN_KPP_COL_4, |
||||
MUX_IN_KPP_COL_5, |
||||
MUX_IN_KPP_COL_6, |
||||
MUX_IN_KPP_COL_7, |
||||
MUX_IN_KPP_ROW_0, |
||||
MUX_IN_KPP_ROW_1, |
||||
MUX_IN_KPP_ROW_2, |
||||
MUX_IN_KPP_ROW_3, |
||||
MUX_IN_KPP_ROW_4, |
||||
MUX_IN_KPP_ROW_5, |
||||
MUX_IN_KPP_ROW_6, |
||||
MUX_IN_KPP_ROW_7, |
||||
MUX_IN_OWIRE_BATTERY_LINE, |
||||
MUX_IN_SPDIF_HCKT_CLK2, |
||||
MUX_IN_SPDIF_SPDIF_IN1, |
||||
MUX_IN_UART3_UART_RTS_B, |
||||
MUX_IN_UART3_UART_RXD_MUX, |
||||
MUX_IN_USB_OTG_DATA_0, |
||||
MUX_IN_USB_OTG_DATA_1, |
||||
MUX_IN_USB_OTG_DATA_2, |
||||
MUX_IN_USB_OTG_DATA_3, |
||||
MUX_IN_USB_OTG_DATA_4, |
||||
MUX_IN_USB_OTG_DATA_5, |
||||
MUX_IN_USB_OTG_DATA_6, |
||||
MUX_IN_USB_OTG_DATA_7, |
||||
MUX_IN_USB_OTG_DIR, |
||||
MUX_IN_USB_OTG_NXT, |
||||
MUX_IN_USB_UH2_DATA_0, |
||||
MUX_IN_USB_UH2_DATA_1, |
||||
MUX_IN_USB_UH2_DATA_2, |
||||
MUX_IN_USB_UH2_DATA_3, |
||||
MUX_IN_USB_UH2_DATA_4, |
||||
MUX_IN_USB_UH2_DATA_5, |
||||
MUX_IN_USB_UH2_DATA_6, |
||||
MUX_IN_USB_UH2_DATA_7, |
||||
MUX_IN_USB_UH2_DIR, |
||||
MUX_IN_USB_UH2_NXT, |
||||
MUX_IN_USB_UH2_USB_OC, |
||||
} iomux_input_select_t; |
||||
|
||||
/*
|
||||
* various IOMUX input functions |
||||
*/ |
||||
typedef enum iomux_input_config { |
||||
INPUT_CTL_PATH0 = 0x0, |
||||
INPUT_CTL_PATH1, |
||||
INPUT_CTL_PATH2, |
||||
INPUT_CTL_PATH3, |
||||
INPUT_CTL_PATH4, |
||||
INPUT_CTL_PATH5, |
||||
INPUT_CTL_PATH6, |
||||
INPUT_CTL_PATH7, |
||||
} iomux_input_cfg_t; |
||||
|
||||
/*
|
||||
* Request ownership for an IO pin. This function has to be the first one |
||||
* being called before that pin is used. The caller has to check the |
||||
* return value to make sure it returns 0. |
||||
* |
||||
* @param pin a name defined by iomux_pin_name_t |
||||
* @param cfg an input function as defined in iomux_pin_cfg_t |
||||
* |
||||
* @return 0 if successful; Non-zero otherwise |
||||
*/ |
||||
void mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg); |
||||
|
||||
/*
|
||||
* Release ownership for an IO pin |
||||
* |
||||
* @param pin a name defined by iomux_pin_name_t |
||||
* @param cfg an input function as defined in iomux_pin_cfg_t |
||||
*/ |
||||
void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg); |
||||
|
||||
/*
|
||||
* This function enables/disables the general purpose function for a particular |
||||
* signal. |
||||
* |
||||
* @param gp one signal as defined in iomux_gp_func_t |
||||
* @param en 1 to enable; 0 to disable |
||||
*/ |
||||
void mxc_iomux_set_gpr(iomux_gp_func_t gp, int en); |
||||
|
||||
/*
|
||||
* This function configures the pad value for a IOMUX pin. |
||||
* |
||||
* @param pin a pin number as defined in iomux_pin_name_t |
||||
* @param config the ORed value of elements defined in |
||||
* iomux_pad_config_t |
||||
*/ |
||||
void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config); |
||||
|
||||
/*
|
||||
* This function configures input path. |
||||
* |
||||
* @param input index of input select register as defined in |
||||
* iomux_input_select_t |
||||
* @param config the binary value of elements defined in |
||||
* iomux_input_cfg_t |
||||
*/ |
||||
void mxc_iomux_set_input(iomux_input_select_t input, u32 config); |
||||
#endif |
||||
@ -0,0 +1,355 @@ |
||||
/*
|
||||
* (C) Copyright 2011 |
||||
* Stefano Babic, DENX Software Engineering, sbabic@denx.de. |
||||
* |
||||
* Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __ASM_ARCH_MXC_MX35_PINS_H__ |
||||
#define __ASM_ARCH_MXC_MX35_PINS_H__ |
||||
|
||||
/*!
|
||||
* @file arch-mxc/mx35_pins.h |
||||
* |
||||
* @brief MX35 I/O Pin List |
||||
* |
||||
* @ingroup GPIO_MX35 |
||||
*/ |
||||
|
||||
#ifndef __ASSEMBLY__ |
||||
|
||||
/*!
|
||||
* @name IOMUX/PAD Bit field definitions |
||||
*/ |
||||
|
||||
/*! @{ */ |
||||
|
||||
/*!
|
||||
* In order to identify pins more effectively, each mux-controlled pin's |
||||
* enumerated value is constructed in the following way: |
||||
* |
||||
* ------------------------------------------------------------------- |
||||
* 31-29 | 28 - 24 |23 - 21| 20 - 10| 9 - 0 |
||||
* ------------------------------------------------------------------- |
||||
* IO_P | IO_I | RSVD | PAD_I | MUX_I |
||||
* ------------------------------------------------------------------- |
||||
* |
||||
* Bit 0 to 7 contains MUX_I used to identify the register |
||||
* offset (base is IOMUX_module_base ) defined in the Section |
||||
* "sw_pad_ctl & sw_mux_ctl details" of the IC Spec. The similar field |
||||
* definitions are used for the pad control register.the MX35_PIN_A0 is |
||||
* defined in the enumeration: ( 0x28 << MUX_I) |( 0x368 << PAD_I) |
||||
* So the absolute address is: IOMUX_module_base + 0x28. |
||||
* The pad control register offset is: 0x368. |
||||
*/ |
||||
|
||||
/*!
|
||||
* Starting bit position within each entry of \b iomux_pins to represent the |
||||
* MUX control register offset |
||||
*/ |
||||
#define MUX_I 0 |
||||
/*!
|
||||
* Starting bit position within each entry of \b iomux_pins to represent the |
||||
* PAD control register offset |
||||
*/ |
||||
#define PAD_I 10 |
||||
|
||||
/*!
|
||||
* Starting bit position within each entry of \b iomux_pins to represent the |
||||
* reserved filed |
||||
*/ |
||||
#define RSVD_I 21 |
||||
|
||||
#define MUX_IO_P 29 |
||||
#define MUX_IO_I 24 |
||||
#define IOMUX_TO_GPIO(pin) ((((unsigned int)pin >> MUX_IO_P) * \ |
||||
GPIO_NUM_PIN) + ((pin >> MUX_IO_I) &\
|
||||
((1 << (MUX_IO_P - MUX_IO_I)) - 1))) |
||||
#define IOMUX_TO_IRQ(pin) (MXC_GPIO_INT_BASE + IOMUX_TO_GPIO(pin)) |
||||
#define GPIO_TO_PORT(n) (n / GPIO_NUM_PIN) |
||||
#define GPIO_TO_INDEX(n) (n % GPIO_NUM_PIN) |
||||
|
||||
#define NON_GPIO_I 0x7 |
||||
#define PIN_TO_MUX_MASK ((1<<(PAD_I - MUX_I)) - 1) |
||||
#define PIN_TO_PAD_MASK ((1<<(RSVD_I - PAD_I)) - 1) |
||||
#define NON_MUX_I PIN_TO_MUX_MASK |
||||
|
||||
#define _MXC_BUILD_PIN(gp, gi, mi, pi) \ |
||||
(((gp) << MUX_IO_P) | ((gi) << MUX_IO_I) | \
|
||||
((mi) << MUX_I) | ((pi) << PAD_I)) |
||||
|
||||
#define _MXC_BUILD_GPIO_PIN(gp, gi, mi, pi) \ |
||||
_MXC_BUILD_PIN(gp, gi, mi, pi) |
||||
|
||||
#define _MXC_BUILD_NON_GPIO_PIN(mi, pi) \ |
||||
_MXC_BUILD_PIN(NON_GPIO_I, 0, mi, pi) |
||||
|
||||
#define PIN_TO_IOMUX_MUX(pin) ((pin >> MUX_I) & PIN_TO_MUX_MASK) |
||||
#define PIN_TO_IOMUX_PAD(pin) ((pin >> PAD_I) & PIN_TO_PAD_MASK) |
||||
|
||||
/*! @} End IOMUX/PAD Bit field definitions */ |
||||
|
||||
/*!
|
||||
* This enumeration is constructed based on the Section |
||||
* "sw_pad_ctl & sw_mux_ctl details" of the MX35 IC Spec. Each enumerated |
||||
* value is constructed based on the rules described above. |
||||
*/ |
||||
typedef enum iomux_pins { |
||||
MX35_PIN_CAPTURE = _MXC_BUILD_GPIO_PIN(0, 4, 0x4, 0x328), |
||||
MX35_PIN_COMPARE = _MXC_BUILD_GPIO_PIN(0, 5, 0x8, 0x32C), |
||||
MX35_PIN_WATCHDOG_RST = _MXC_BUILD_GPIO_PIN(0, 6, 0xC, 0x330), |
||||
MX35_PIN_GPIO1_0 = _MXC_BUILD_GPIO_PIN(0, 0, 0x10, 0x334), |
||||
MX35_PIN_GPIO1_1 = _MXC_BUILD_GPIO_PIN(0, 1, 0x14, 0x338), |
||||
MX35_PIN_GPIO2_0 = _MXC_BUILD_GPIO_PIN(1, 0, 0x18, 0x33C), |
||||
MX35_PIN_GPIO3_0 = _MXC_BUILD_GPIO_PIN(2, 1, 0x1C, 0x340), |
||||
MX35_PIN_CLKO = _MXC_BUILD_GPIO_PIN(0, 8, 0x20, 0x34C), |
||||
|
||||
MX35_PIN_POWER_FAIL = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x360), |
||||
MX35_PIN_VSTBY = _MXC_BUILD_GPIO_PIN(0, 7, 0x24, 0x364), |
||||
MX35_PIN_A0 = _MXC_BUILD_NON_GPIO_PIN(0x28, 0x368), |
||||
MX35_PIN_A1 = _MXC_BUILD_NON_GPIO_PIN(0x2C, 0x36C), |
||||
MX35_PIN_A2 = _MXC_BUILD_NON_GPIO_PIN(0x30, 0x370), |
||||
MX35_PIN_A3 = _MXC_BUILD_NON_GPIO_PIN(0x34, 0x374), |
||||
MX35_PIN_A4 = _MXC_BUILD_NON_GPIO_PIN(0x38, 0x378), |
||||
MX35_PIN_A5 = _MXC_BUILD_NON_GPIO_PIN(0x3C, 0x37C), |
||||
MX35_PIN_A6 = _MXC_BUILD_NON_GPIO_PIN(0x40, 0x380), |
||||
MX35_PIN_A7 = _MXC_BUILD_NON_GPIO_PIN(0x44, 0x384), |
||||
MX35_PIN_A8 = _MXC_BUILD_NON_GPIO_PIN(0x48, 0x388), |
||||
MX35_PIN_A9 = _MXC_BUILD_NON_GPIO_PIN(0x4C, 0x38C), |
||||
MX35_PIN_A10 = _MXC_BUILD_NON_GPIO_PIN(0x50, 0x390), |
||||
MX35_PIN_MA10 = _MXC_BUILD_NON_GPIO_PIN(0x54, 0x394), |
||||
MX35_PIN_A11 = _MXC_BUILD_NON_GPIO_PIN(0x58, 0x398), |
||||
MX35_PIN_A12 = _MXC_BUILD_NON_GPIO_PIN(0x5C, 0x39C), |
||||
MX35_PIN_A13 = _MXC_BUILD_NON_GPIO_PIN(0x60, 0x3A0), |
||||
MX35_PIN_A14 = _MXC_BUILD_NON_GPIO_PIN(0x64, 0x3A4), |
||||
MX35_PIN_A15 = _MXC_BUILD_NON_GPIO_PIN(0x68, 0x3A8), |
||||
MX35_PIN_A16 = _MXC_BUILD_NON_GPIO_PIN(0x6C, 0x3AC), |
||||
MX35_PIN_A17 = _MXC_BUILD_NON_GPIO_PIN(0x70, 0x3B0), |
||||
MX35_PIN_A18 = _MXC_BUILD_NON_GPIO_PIN(0x74, 0x3B4), |
||||
MX35_PIN_A19 = _MXC_BUILD_NON_GPIO_PIN(0x78, 0x3B8), |
||||
MX35_PIN_A20 = _MXC_BUILD_NON_GPIO_PIN(0x7C, 0x3BC), |
||||
MX35_PIN_A21 = _MXC_BUILD_NON_GPIO_PIN(0x80, 0x3C0), |
||||
MX35_PIN_A22 = _MXC_BUILD_NON_GPIO_PIN(0x84, 0x3C4), |
||||
MX35_PIN_A23 = _MXC_BUILD_NON_GPIO_PIN(0x88, 0x3C8), |
||||
MX35_PIN_A24 = _MXC_BUILD_NON_GPIO_PIN(0x8C, 0x3CC), |
||||
MX35_PIN_A25 = _MXC_BUILD_NON_GPIO_PIN(0x90, 0x3D0), |
||||
|
||||
MX35_PIN_EB0 = _MXC_BUILD_NON_GPIO_PIN(0x94, 0x46C), |
||||
MX35_PIN_EB1 = _MXC_BUILD_NON_GPIO_PIN(0x98, 0x470), |
||||
MX35_PIN_OE = _MXC_BUILD_NON_GPIO_PIN(0x9C, 0x474), |
||||
MX35_PIN_CS0 = _MXC_BUILD_NON_GPIO_PIN(0xA0, 0x478), |
||||
MX35_PIN_CS1 = _MXC_BUILD_NON_GPIO_PIN(0xA4, 0x47C), |
||||
MX35_PIN_CS2 = _MXC_BUILD_NON_GPIO_PIN(0xA8, 0x480), |
||||
MX35_PIN_CS3 = _MXC_BUILD_NON_GPIO_PIN(0xAC, 0x484), |
||||
MX35_PIN_CS4 = _MXC_BUILD_GPIO_PIN(0, 20, 0xB0, 0x488), |
||||
MX35_PIN_CS5 = _MXC_BUILD_GPIO_PIN(0, 21, 0xB4, 0x48C), |
||||
MX35_PIN_NFCE_B = _MXC_BUILD_GPIO_PIN(0, 22, 0xB8, 0x490), |
||||
|
||||
MX35_PIN_LBA = _MXC_BUILD_NON_GPIO_PIN(0xBC, 0x498), |
||||
MX35_PIN_BCLK = _MXC_BUILD_NON_GPIO_PIN(0xC0, 0x49C), |
||||
MX35_PIN_RW = _MXC_BUILD_NON_GPIO_PIN(0xC4, 0x4A0), |
||||
|
||||
MX35_PIN_NFWE_B = _MXC_BUILD_GPIO_PIN(0, 18, 0xC8, 0x4CC), |
||||
MX35_PIN_NFRE_B = _MXC_BUILD_GPIO_PIN(0, 19, 0xCC, 0x4D0), |
||||
MX35_PIN_NFALE = _MXC_BUILD_GPIO_PIN(0, 20, 0xD0, 0x4D4), |
||||
MX35_PIN_NFCLE = _MXC_BUILD_GPIO_PIN(0, 21, 0xD4, 0x4D8), |
||||
MX35_PIN_NFWP_B = _MXC_BUILD_GPIO_PIN(0, 22, 0xD8, 0x4DC), |
||||
MX35_PIN_NFRB = _MXC_BUILD_GPIO_PIN(0, 23, 0xDC, 0x4E0), |
||||
|
||||
MX35_PIN_D15 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4E4), |
||||
MX35_PIN_D14 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4E8), |
||||
MX35_PIN_D13 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4EC), |
||||
MX35_PIN_D12 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4F0), |
||||
MX35_PIN_D11 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4F4), |
||||
MX35_PIN_D10 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4F8), |
||||
MX35_PIN_D9 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4FC), |
||||
MX35_PIN_D8 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x500), |
||||
MX35_PIN_D7 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x504), |
||||
MX35_PIN_D6 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x508), |
||||
MX35_PIN_D5 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x50C), |
||||
MX35_PIN_D4 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x510), |
||||
MX35_PIN_D3 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x514), |
||||
MX35_PIN_D2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x518), |
||||
MX35_PIN_D1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x51C), |
||||
MX35_PIN_D0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x520), |
||||
|
||||
MX35_PIN_CSI_D8 = _MXC_BUILD_GPIO_PIN(0, 20, 0xE0, 0x524), |
||||
MX35_PIN_CSI_D9 = _MXC_BUILD_GPIO_PIN(0, 21, 0xE4, 0x528), |
||||
MX35_PIN_CSI_D10 = _MXC_BUILD_GPIO_PIN(0, 22, 0xE8, 0x52C), |
||||
MX35_PIN_CSI_D11 = _MXC_BUILD_GPIO_PIN(0, 23, 0xEC, 0x530), |
||||
MX35_PIN_CSI_D12 = _MXC_BUILD_GPIO_PIN(0, 24, 0xF0, 0x534), |
||||
MX35_PIN_CSI_D13 = _MXC_BUILD_GPIO_PIN(0, 25, 0xF4, 0x538), |
||||
MX35_PIN_CSI_D14 = _MXC_BUILD_GPIO_PIN(0, 26, 0xF8, 0x53C), |
||||
MX35_PIN_CSI_D15 = _MXC_BUILD_GPIO_PIN(0, 27, 0xFC, 0x540), |
||||
MX35_PIN_CSI_MCLK = _MXC_BUILD_GPIO_PIN(0, 28, 0x100, 0x544), |
||||
MX35_PIN_CSI_VSYNC = _MXC_BUILD_GPIO_PIN(0, 29, 0x104, 0x548), |
||||
MX35_PIN_CSI_HSYNC = _MXC_BUILD_GPIO_PIN(0, 30, 0x108, 0x54C), |
||||
MX35_PIN_CSI_PIXCLK = _MXC_BUILD_GPIO_PIN(0, 31, 0x10C, 0x550), |
||||
|
||||
MX35_PIN_I2C1_CLK = _MXC_BUILD_GPIO_PIN(1, 24, 0x110, 0x554), |
||||
MX35_PIN_I2C1_DAT = _MXC_BUILD_GPIO_PIN(1, 25, 0x114, 0x558), |
||||
MX35_PIN_I2C2_CLK = _MXC_BUILD_GPIO_PIN(1, 26, 0x118, 0x55C), |
||||
MX35_PIN_I2C2_DAT = _MXC_BUILD_GPIO_PIN(1, 27, 0x11C, 0x560), |
||||
|
||||
MX35_PIN_STXD4 = _MXC_BUILD_GPIO_PIN(1, 28, 0x120, 0x564), |
||||
MX35_PIN_SRXD4 = _MXC_BUILD_GPIO_PIN(1, 29, 0x124, 0x568), |
||||
MX35_PIN_SCK4 = _MXC_BUILD_GPIO_PIN(1, 30, 0x128, 0x56C), |
||||
MX35_PIN_STXFS4 = _MXC_BUILD_GPIO_PIN(1, 31, 0x12C, 0x570), |
||||
MX35_PIN_STXD5 = _MXC_BUILD_GPIO_PIN(0, 0, 0x130, 0x574), |
||||
MX35_PIN_SRXD5 = _MXC_BUILD_GPIO_PIN(0, 1, 0x134, 0x578), |
||||
MX35_PIN_SCK5 = _MXC_BUILD_GPIO_PIN(0, 2, 0x138, 0x57C), |
||||
MX35_PIN_STXFS5 = _MXC_BUILD_GPIO_PIN(0, 3, 0x13C, 0x580), |
||||
|
||||
MX35_PIN_SCKR = _MXC_BUILD_GPIO_PIN(0, 4, 0x140, 0x584), |
||||
MX35_PIN_FSR = _MXC_BUILD_GPIO_PIN(0, 5, 0x144, 0x588), |
||||
MX35_PIN_HCKR = _MXC_BUILD_GPIO_PIN(0, 6, 0x148, 0x58C), |
||||
MX35_PIN_SCKT = _MXC_BUILD_GPIO_PIN(0, 7, 0x14C, 0x590), |
||||
MX35_PIN_FST = _MXC_BUILD_GPIO_PIN(0, 8, 0x150, 0x594), |
||||
MX35_PIN_HCKT = _MXC_BUILD_GPIO_PIN(0, 9, 0x154, 0x598), |
||||
MX35_PIN_TX5_RX0 = _MXC_BUILD_GPIO_PIN(0, 10, 0x158, 0x59C), |
||||
MX35_PIN_TX4_RX1 = _MXC_BUILD_GPIO_PIN(0, 11, 0x15C, 0x5A0), |
||||
MX35_PIN_TX3_RX2 = _MXC_BUILD_GPIO_PIN(0, 12, 0x160, 0x5A4), |
||||
MX35_PIN_TX2_RX3 = _MXC_BUILD_GPIO_PIN(0, 13, 0x164, 0x5A8), |
||||
MX35_PIN_TX1 = _MXC_BUILD_GPIO_PIN(0, 14, 0x168, 0x5AC), |
||||
MX35_PIN_TX0 = _MXC_BUILD_GPIO_PIN(0, 15, 0x16C, 0x5B0), |
||||
|
||||
MX35_PIN_CSPI1_MOSI = _MXC_BUILD_GPIO_PIN(0, 16, 0x170, 0x5B4), |
||||
MX35_PIN_CSPI1_MISO = _MXC_BUILD_GPIO_PIN(0, 17, 0x174, 0x5B8), |
||||
MX35_PIN_CSPI1_SS0 = _MXC_BUILD_GPIO_PIN(0, 18, 0x178, 0x5BC), |
||||
MX35_PIN_CSPI1_SS1 = _MXC_BUILD_GPIO_PIN(0, 19, 0x17C, 0x5C0), |
||||
MX35_PIN_CSPI1_SCLK = _MXC_BUILD_GPIO_PIN(2, 4, 0x180, 0x5C4), |
||||
MX35_PIN_CSPI1_SPI_RDY = _MXC_BUILD_GPIO_PIN(2, 5, 0x184, 0x5C8), |
||||
|
||||
MX35_PIN_RXD1 = _MXC_BUILD_GPIO_PIN(2, 6, 0x188, 0x5CC), |
||||
MX35_PIN_TXD1 = _MXC_BUILD_GPIO_PIN(2, 7, 0x18C, 0x5D0), |
||||
MX35_PIN_RTS1 = _MXC_BUILD_GPIO_PIN(2, 8, 0x190, 0x5D4), |
||||
MX35_PIN_CTS1 = _MXC_BUILD_GPIO_PIN(2, 9, 0x194, 0x5D8), |
||||
MX35_PIN_RXD2 = _MXC_BUILD_GPIO_PIN(2, 10, 0x198, 0x5DC), |
||||
MX35_PIN_TXD2 = _MXC_BUILD_GPIO_PIN(1, 11, 0x19C, 0x5E0), |
||||
MX35_PIN_RTS2 = _MXC_BUILD_GPIO_PIN(1, 12, 0x1A0, 0x5E4), |
||||
MX35_PIN_CTS2 = _MXC_BUILD_GPIO_PIN(1, 13, 0x1A4, 0x5E8), |
||||
|
||||
MX35_PIN_USBOTG_PWR = _MXC_BUILD_GPIO_PIN(2, 14, 0x1A8, 0x60C), |
||||
MX35_PIN_USBOTG_OC = _MXC_BUILD_GPIO_PIN(2, 15, 0x1AC, 0x610), |
||||
|
||||
MX35_PIN_LD0 = _MXC_BUILD_GPIO_PIN(1, 0, 0x1B0, 0x614), |
||||
MX35_PIN_LD1 = _MXC_BUILD_GPIO_PIN(1, 1, 0x1B4, 0x618), |
||||
MX35_PIN_LD2 = _MXC_BUILD_GPIO_PIN(1, 2, 0x1B8, 0x61C), |
||||
MX35_PIN_LD3 = _MXC_BUILD_GPIO_PIN(1, 3, 0x1BC, 0x620), |
||||
MX35_PIN_LD4 = _MXC_BUILD_GPIO_PIN(1, 4, 0x1C0, 0x624), |
||||
MX35_PIN_LD5 = _MXC_BUILD_GPIO_PIN(1, 5, 0x1C4, 0x628), |
||||
MX35_PIN_LD6 = _MXC_BUILD_GPIO_PIN(1, 6, 0x1C8, 0x62C), |
||||
MX35_PIN_LD7 = _MXC_BUILD_GPIO_PIN(1, 7, 0x1CC, 0x630), |
||||
MX35_PIN_LD8 = _MXC_BUILD_GPIO_PIN(1, 8, 0x1D0, 0x634), |
||||
MX35_PIN_LD9 = _MXC_BUILD_GPIO_PIN(1, 9, 0x1D4, 0x638), |
||||
MX35_PIN_LD10 = _MXC_BUILD_GPIO_PIN(1, 10, 0x1D8, 0x63C), |
||||
MX35_PIN_LD11 = _MXC_BUILD_GPIO_PIN(1, 11, 0x1DC, 0x640), |
||||
MX35_PIN_LD12 = _MXC_BUILD_GPIO_PIN(1, 12, 0x1E0, 0x644), |
||||
MX35_PIN_LD13 = _MXC_BUILD_GPIO_PIN(1, 13, 0x1E4, 0x648), |
||||
MX35_PIN_LD14 = _MXC_BUILD_GPIO_PIN(1, 14, 0x1E8, 0x64C), |
||||
MX35_PIN_LD15 = _MXC_BUILD_GPIO_PIN(1, 15, 0x1EC, 0x650), |
||||
MX35_PIN_LD16 = _MXC_BUILD_GPIO_PIN(1, 16, 0x1F0, 0x654), |
||||
MX35_PIN_LD17 = _MXC_BUILD_GPIO_PIN(1, 17, 0x1F4, 0x658), |
||||
MX35_PIN_LD18 = _MXC_BUILD_GPIO_PIN(2, 24, 0x1F8, 0x65C), |
||||
MX35_PIN_LD19 = _MXC_BUILD_GPIO_PIN(2, 25, 0x1FC, 0x660), |
||||
MX35_PIN_LD20 = _MXC_BUILD_GPIO_PIN(2, 26, 0x200, 0x664), |
||||
MX35_PIN_LD21 = _MXC_BUILD_GPIO_PIN(2, 27, 0x204, 0x668), |
||||
MX35_PIN_LD22 = _MXC_BUILD_GPIO_PIN(2, 28, 0x208, 0x66C), |
||||
MX35_PIN_LD23 = _MXC_BUILD_GPIO_PIN(2, 29, 0x20C, 0x670), |
||||
|
||||
MX35_PIN_D3_HSYNC = _MXC_BUILD_GPIO_PIN(2, 30, 0x210, 0x674), |
||||
MX35_PIN_D3_FPSHIFT = _MXC_BUILD_GPIO_PIN(2, 31, 0x214, 0x678), |
||||
MX35_PIN_D3_DRDY = _MXC_BUILD_GPIO_PIN(0, 0, 0x218, 0x67C), |
||||
MX35_PIN_CONTRAST = _MXC_BUILD_GPIO_PIN(0, 1, 0x21C, 0x680), |
||||
MX35_PIN_D3_VSYNC = _MXC_BUILD_GPIO_PIN(0, 2, 0x220, 0x684), |
||||
MX35_PIN_D3_REV = _MXC_BUILD_GPIO_PIN(0, 3, 0x224, 0x688), |
||||
MX35_PIN_D3_CLS = _MXC_BUILD_GPIO_PIN(0, 4, 0x228, 0x68C), |
||||
MX35_PIN_D3_SPL = _MXC_BUILD_GPIO_PIN(0, 5, 0x22C, 0x690), |
||||
|
||||
MX35_PIN_SD1_CMD = _MXC_BUILD_GPIO_PIN(0, 6, 0x230, 0x694), |
||||
MX35_PIN_SD1_CLK = _MXC_BUILD_GPIO_PIN(0, 7, 0x234, 0x698), |
||||
MX35_PIN_SD1_DATA0 = _MXC_BUILD_GPIO_PIN(0, 8, 0x238, 0x69C), |
||||
MX35_PIN_SD1_DATA1 = _MXC_BUILD_GPIO_PIN(0, 9, 0x23C, 0x6A0), |
||||
MX35_PIN_SD1_DATA2 = _MXC_BUILD_GPIO_PIN(0, 10, 0x240, 0x6A4), |
||||
MX35_PIN_SD1_DATA3 = _MXC_BUILD_GPIO_PIN(0, 11, 0x244, 0x6A8), |
||||
MX35_PIN_SD2_CMD = _MXC_BUILD_GPIO_PIN(1, 0, 0x248, 0x6AC), |
||||
MX35_PIN_SD2_CLK = _MXC_BUILD_GPIO_PIN(1, 1, 0x24C, 0x6B0), |
||||
MX35_PIN_SD2_DATA0 = _MXC_BUILD_GPIO_PIN(1, 2, 0x250, 0x6B4), |
||||
MX35_PIN_SD2_DATA1 = _MXC_BUILD_GPIO_PIN(1, 3, 0x254, 0x6B8), |
||||
MX35_PIN_SD2_DATA2 = _MXC_BUILD_GPIO_PIN(1, 4, 0x258, 0x6BC), |
||||
MX35_PIN_SD2_DATA3 = _MXC_BUILD_GPIO_PIN(1, 5, 0x25C, 0x6C0), |
||||
|
||||
MX35_PIN_ATA_CS0 = _MXC_BUILD_GPIO_PIN(1, 6, 0x260, 0x6C4), |
||||
MX35_PIN_ATA_CS1 = _MXC_BUILD_GPIO_PIN(1, 7, 0x264, 0x6C8), |
||||
MX35_PIN_ATA_DIOR = _MXC_BUILD_GPIO_PIN(1, 8, 0x268, 0x6CC), |
||||
MX35_PIN_ATA_DIOW = _MXC_BUILD_GPIO_PIN(1, 9, 0x26C, 0x6D0), |
||||
MX35_PIN_ATA_DMACK = _MXC_BUILD_GPIO_PIN(1, 10, 0x270, 0x6D4), |
||||
MX35_PIN_ATA_RESET_B = _MXC_BUILD_GPIO_PIN(1, 11, 0x274, 0x6D8), |
||||
MX35_PIN_ATA_IORDY = _MXC_BUILD_GPIO_PIN(1, 12, 0x278, 0x6DC), |
||||
MX35_PIN_ATA_DATA0 = _MXC_BUILD_GPIO_PIN(1, 13, 0x27C, 0x6E0), |
||||
MX35_PIN_ATA_DATA1 = _MXC_BUILD_GPIO_PIN(1, 14, 0x280, 0x6E4), |
||||
MX35_PIN_ATA_DATA2 = _MXC_BUILD_GPIO_PIN(1, 15, 0x284, 0x6E8), |
||||
MX35_PIN_ATA_DATA3 = _MXC_BUILD_GPIO_PIN(1, 16, 0x288, 0x6EC), |
||||
MX35_PIN_ATA_DATA4 = _MXC_BUILD_GPIO_PIN(1, 17, 0x28C, 0x6F0), |
||||
MX35_PIN_ATA_DATA5 = _MXC_BUILD_GPIO_PIN(1, 18, 0x290, 0x6F4), |
||||
MX35_PIN_ATA_DATA6 = _MXC_BUILD_GPIO_PIN(1, 19, 0x294, 0x6F8), |
||||
MX35_PIN_ATA_DATA7 = _MXC_BUILD_GPIO_PIN(1, 20, 0x298, 0x6FC), |
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MX35_PIN_ATA_DATA8 = _MXC_BUILD_GPIO_PIN(1, 21, 0x29C, 0x700), |
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MX35_PIN_ATA_DATA9 = _MXC_BUILD_GPIO_PIN(1, 22, 0x2A0, 0x704), |
||||
MX35_PIN_ATA_DATA10 = _MXC_BUILD_GPIO_PIN(1, 23, 0x2A4, 0x708), |
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MX35_PIN_ATA_DATA11 = _MXC_BUILD_GPIO_PIN(1, 24, 0x2A8, 0x70C), |
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MX35_PIN_ATA_DATA12 = _MXC_BUILD_GPIO_PIN(1, 25, 0x2AC, 0x710), |
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MX35_PIN_ATA_DATA13 = _MXC_BUILD_GPIO_PIN(1, 26, 0x2B0, 0x714), |
||||
MX35_PIN_ATA_DATA14 = _MXC_BUILD_GPIO_PIN(1, 27, 0x2B4, 0x718), |
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MX35_PIN_ATA_DATA15 = _MXC_BUILD_GPIO_PIN(1, 28, 0x2B8, 0x71C), |
||||
MX35_PIN_ATA_INTRQ = _MXC_BUILD_GPIO_PIN(1, 29, 0x2BC, 0x720), |
||||
MX35_PIN_ATA_BUFF_EN = _MXC_BUILD_GPIO_PIN(1, 30, 0x2C0, 0x724), |
||||
MX35_PIN_ATA_DMARQ = _MXC_BUILD_GPIO_PIN(1, 31, 0x2C4, 0x728), |
||||
MX35_PIN_ATA_DA0 = _MXC_BUILD_GPIO_PIN(2, 0, 0x2C8, 0x72C), |
||||
MX35_PIN_ATA_DA1 = _MXC_BUILD_GPIO_PIN(2, 1, 0x2CC, 0x730), |
||||
MX35_PIN_ATA_DA2 = _MXC_BUILD_GPIO_PIN(2, 2, 0x2D0, 0x734), |
||||
|
||||
MX35_PIN_MLB_CLK = _MXC_BUILD_GPIO_PIN(2, 3, 0x2D4, 0x738), |
||||
MX35_PIN_MLB_DAT = _MXC_BUILD_GPIO_PIN(2, 4, 0x2D8, 0x73C), |
||||
MX35_PIN_MLB_SIG = _MXC_BUILD_GPIO_PIN(2, 5, 0x2DC, 0x740), |
||||
|
||||
MX35_PIN_FEC_TX_CLK = _MXC_BUILD_GPIO_PIN(2, 6, 0x2E0, 0x744), |
||||
MX35_PIN_FEC_RX_CLK = _MXC_BUILD_GPIO_PIN(2, 7, 0x2E4, 0x748), |
||||
MX35_PIN_FEC_RX_DV = _MXC_BUILD_GPIO_PIN(2, 8, 0x2E8, 0x74C), |
||||
MX35_PIN_FEC_COL = _MXC_BUILD_GPIO_PIN(2, 9, 0x2EC, 0x750), |
||||
MX35_PIN_FEC_RDATA0 = _MXC_BUILD_GPIO_PIN(2, 10, 0x2F0, 0x754), |
||||
MX35_PIN_FEC_TDATA0 = _MXC_BUILD_GPIO_PIN(2, 11, 0x2F4, 0x758), |
||||
MX35_PIN_FEC_TX_EN = _MXC_BUILD_GPIO_PIN(2, 12, 0x2F8, 0x75C), |
||||
MX35_PIN_FEC_MDC = _MXC_BUILD_GPIO_PIN(2, 13, 0x2FC, 0x760), |
||||
MX35_PIN_FEC_MDIO = _MXC_BUILD_GPIO_PIN(2, 14, 0x300, 0x764), |
||||
MX35_PIN_FEC_TX_ERR = _MXC_BUILD_GPIO_PIN(2, 15, 0x304, 0x768), |
||||
MX35_PIN_FEC_RX_ERR = _MXC_BUILD_GPIO_PIN(2, 16, 0x308, 0x76C), |
||||
MX35_PIN_FEC_CRS = _MXC_BUILD_GPIO_PIN(2, 17, 0x30C, 0x770), |
||||
MX35_PIN_FEC_RDATA1 = _MXC_BUILD_GPIO_PIN(2, 18, 0x310, 0x774), |
||||
MX35_PIN_FEC_TDATA1 = _MXC_BUILD_GPIO_PIN(2, 19, 0x314, 0x778), |
||||
MX35_PIN_FEC_RDATA2 = _MXC_BUILD_GPIO_PIN(2, 20, 0x318, 0x77C), |
||||
MX35_PIN_FEC_TDATA2 = _MXC_BUILD_GPIO_PIN(2, 21, 0x31C, 0x780), |
||||
MX35_PIN_FEC_RDATA3 = _MXC_BUILD_GPIO_PIN(2, 22, 0x320, 0x784), |
||||
MX35_PIN_FEC_TDATA3 = _MXC_BUILD_GPIO_PIN(2, 23, 0x324, 0x788), |
||||
} iomux_pin_name_t; |
||||
|
||||
#endif |
||||
#endif |
||||
@ -0,0 +1,31 @@ |
||||
/*
|
||||
* (C) Copyright 2011 |
||||
* Stefano Babic, DENX Software Engineering, sbabic@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef _SYS_PROTO_H_ |
||||
#define _SYS_PROTO_H_ |
||||
|
||||
u32 get_cpu_rev(void); |
||||
#define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev) |
||||
void sdelay(unsigned long); |
||||
|
||||
#endif |
||||
Loading…
Reference in new issue