commit
b9d51fbb18
@ -0,0 +1,45 @@ |
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/*
|
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* (C) Copyright 2010 |
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* Texas Instruments, <www.ti.com> |
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* |
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* Steve Sakoman <steve@sakoman.com> |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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|
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#include <asm/arch/cpu.h> |
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#include <asm/arch/sys_proto.h> |
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struct gpmc *gpmc_cfg; |
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/*****************************************************
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* gpmc_init(): init gpmc bus |
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* This code can only be executed from SRAM or SDRAM. |
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*****************************************************/ |
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void gpmc_init(void) |
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{ |
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gpmc_cfg = (struct gpmc *)GPMC_BASE; |
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|
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/* global settings */ |
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writel(0, &gpmc_cfg->irqenable); /* isr's sources masked */ |
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writel(0, &gpmc_cfg->timeout_control);/* timeout disable */ |
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|
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/*
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* Disable the GPMC0 config set by ROM code |
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* It conflicts with our MPDB (both at 0x08000000) |
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*/ |
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writel(0, &gpmc_cfg->cs[0].config7); |
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} |
@ -0,0 +1,344 @@ |
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/*
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* (C) Copyright 2004-2009 |
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* Texas Instruments Incorporated |
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* Richard Woodruff <r-woodruff2@ti.com> |
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* Aneesh V <aneesh@ti.com> |
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* Balaji Krishnamoorthy <balajitk@ti.com> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#ifndef _MUX_OMAP4_H_ |
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#define _MUX_OMAP4_H_ |
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#include <asm/types.h> |
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struct pad_conf_entry { |
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u16 offset; |
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u16 val; |
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} __attribute__ ((packed)); |
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#ifdef CONFIG_OFF_PADCONF |
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#define OFF_PD (1 << 12) |
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#define OFF_PU (3 << 12) |
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#define OFF_OUT_PTD (0 << 10) |
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#define OFF_OUT_PTU (2 << 10) |
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#define OFF_IN (1 << 10) |
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#define OFF_OUT (0 << 10) |
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#define OFF_EN (1 << 9) |
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#else |
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#define OFF_PD (0 << 12) |
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#define OFF_PU (0 << 12) |
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#define OFF_OUT_PTD (0 << 10) |
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#define OFF_OUT_PTU (0 << 10) |
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#define OFF_IN (0 << 10) |
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#define OFF_OUT (0 << 10) |
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#define OFF_EN (0 << 9) |
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#endif |
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|
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#define IEN (1 << 8) |
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#define IDIS (0 << 8) |
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#define PTU (3 << 3) |
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#define PTD (1 << 3) |
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#define EN (1 << 3) |
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#define DIS (0 << 3) |
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#define M0 0 |
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#define M1 1 |
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#define M2 2 |
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#define M3 3 |
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#define M4 4 |
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#define M5 5 |
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#define M6 6 |
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#define M7 7 |
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#define SAFE_MODE M7 |
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#ifdef CONFIG_OFF_PADCONF |
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#define OFF_IN_PD (OFF_PD | OFF_IN | OFF_EN) |
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#define OFF_IN_PU (OFF_PU | OFF_IN | OFF_EN) |
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#define OFF_OUT_PD (OFF_OUT_PTD | OFF_OUT | OFF_EN) |
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#define OFF_OUT_PU (OFF_OUT_PTU | OFF_OUT | OFF_EN) |
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#else |
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#define OFF_IN_PD 0 |
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#define OFF_IN_PU 0 |
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#define OFF_OUT_PD 0 |
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#define OFF_OUT_PU 0 |
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#endif |
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#define CORE_REVISION 0x0000 |
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#define CORE_HWINFO 0x0004 |
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#define CORE_SYSCONFIG 0x0010 |
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#define GPMC_AD0 0x0040 |
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#define GPMC_AD1 0x0042 |
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#define GPMC_AD2 0x0044 |
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#define GPMC_AD3 0x0046 |
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#define GPMC_AD4 0x0048 |
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#define GPMC_AD5 0x004A |
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#define GPMC_AD6 0x004C |
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#define GPMC_AD7 0x004E |
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#define GPMC_AD8 0x0050 |
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#define GPMC_AD9 0x0052 |
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#define GPMC_AD10 0x0054 |
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#define GPMC_AD11 0x0056 |
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#define GPMC_AD12 0x0058 |
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#define GPMC_AD13 0x005A |
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#define GPMC_AD14 0x005C |
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#define GPMC_AD15 0x005E |
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#define GPMC_A16 0x0060 |
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#define GPMC_A17 0x0062 |
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#define GPMC_A18 0x0064 |
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#define GPMC_A19 0x0066 |
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#define GPMC_A20 0x0068 |
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#define GPMC_A21 0x006A |
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#define GPMC_A22 0x006C |
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#define GPMC_A23 0x006E |
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#define GPMC_A24 0x0070 |
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#define GPMC_A25 0x0072 |
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#define GPMC_NCS0 0x0074 |
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#define GPMC_NCS1 0x0076 |
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#define GPMC_NCS2 0x0078 |
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#define GPMC_NCS3 0x007A |
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#define GPMC_NWP 0x007C |
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#define GPMC_CLK 0x007E |
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#define GPMC_NADV_ALE 0x0080 |
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#define GPMC_NOE 0x0082 |
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#define GPMC_NWE 0x0084 |
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#define GPMC_NBE0_CLE 0x0086 |
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#define GPMC_NBE1 0x0088 |
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#define GPMC_WAIT0 0x008A |
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#define GPMC_WAIT1 0x008C |
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#define C2C_DATA11 0x008E |
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#define C2C_DATA12 0x0090 |
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#define C2C_DATA13 0x0092 |
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#define C2C_DATA14 0x0094 |
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#define C2C_DATA15 0x0096 |
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#define HDMI_HPD 0x0098 |
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#define HDMI_CEC 0x009A |
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#define HDMI_DDC_SCL 0x009C |
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#define HDMI_DDC_SDA 0x009E |
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#define CSI21_DX0 0x00A0 |
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#define CSI21_DY0 0x00A2 |
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#define CSI21_DX1 0x00A4 |
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#define CSI21_DY1 0x00A6 |
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#define CSI21_DX2 0x00A8 |
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#define CSI21_DY2 0x00AA |
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#define CSI21_DX3 0x00AC |
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#define CSI21_DY3 0x00AE |
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#define CSI21_DX4 0x00B0 |
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#define CSI21_DY4 0x00B2 |
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#define CSI22_DX0 0x00B4 |
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#define CSI22_DY0 0x00B6 |
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#define CSI22_DX1 0x00B8 |
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#define CSI22_DY1 0x00BA |
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#define CAM_SHUTTER 0x00BC |
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#define CAM_STROBE 0x00BE |
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#define CAM_GLOBALRESET 0x00C0 |
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#define USBB1_ULPITLL_CLK 0x00C2 |
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#define USBB1_ULPITLL_STP 0x00C4 |
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#define USBB1_ULPITLL_DIR 0x00C6 |
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#define USBB1_ULPITLL_NXT 0x00C8 |
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#define USBB1_ULPITLL_DAT0 0x00CA |
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#define USBB1_ULPITLL_DAT1 0x00CC |
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#define USBB1_ULPITLL_DAT2 0x00CE |
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#define USBB1_ULPITLL_DAT3 0x00D0 |
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#define USBB1_ULPITLL_DAT4 0x00D2 |
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#define USBB1_ULPITLL_DAT5 0x00D4 |
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#define USBB1_ULPITLL_DAT6 0x00D6 |
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#define USBB1_ULPITLL_DAT7 0x00D8 |
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#define USBB1_HSIC_DATA 0x00DA |
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#define USBB1_HSIC_STROBE 0x00DC |
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#define USBC1_ICUSB_DP 0x00DE |
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#define USBC1_ICUSB_DM 0x00E0 |
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#define SDMMC1_CLK 0x00E2 |
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#define SDMMC1_CMD 0x00E4 |
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#define SDMMC1_DAT0 0x00E6 |
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#define SDMMC1_DAT1 0x00E8 |
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#define SDMMC1_DAT2 0x00EA |
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#define SDMMC1_DAT3 0x00EC |
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#define SDMMC1_DAT4 0x00EE |
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#define SDMMC1_DAT5 0x00F0 |
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#define SDMMC1_DAT6 0x00F2 |
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#define SDMMC1_DAT7 0x00F4 |
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#define ABE_MCBSP2_CLKX 0x00F6 |
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#define ABE_MCBSP2_DR 0x00F8 |
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#define ABE_MCBSP2_DX 0x00FA |
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#define ABE_MCBSP2_FSX 0x00FC |
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#define ABE_MCBSP1_CLKX 0x00FE |
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#define ABE_MCBSP1_DR 0x0100 |
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#define ABE_MCBSP1_DX 0x0102 |
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#define ABE_MCBSP1_FSX 0x0104 |
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#define ABE_PDM_UL_DATA 0x0106 |
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#define ABE_PDM_DL_DATA 0x0108 |
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#define ABE_PDM_FRAME 0x010A |
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#define ABE_PDM_LB_CLK 0x010C |
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#define ABE_CLKS 0x010E |
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#define ABE_DMIC_CLK1 0x0110 |
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#define ABE_DMIC_DIN1 0x0112 |
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#define ABE_DMIC_DIN2 0x0114 |
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#define ABE_DMIC_DIN3 0x0116 |
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#define UART2_CTS 0x0118 |
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#define UART2_RTS 0x011A |
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#define UART2_RX 0x011C |
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#define UART2_TX 0x011E |
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#define HDQ_SIO 0x0120 |
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#define I2C1_SCL 0x0122 |
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#define I2C1_SDA 0x0124 |
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#define I2C2_SCL 0x0126 |
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#define I2C2_SDA 0x0128 |
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#define I2C3_SCL 0x012A |
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#define I2C3_SDA 0x012C |
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#define I2C4_SCL 0x012E |
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#define I2C4_SDA 0x0130 |
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#define MCSPI1_CLK 0x0132 |
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#define MCSPI1_SOMI 0x0134 |
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#define MCSPI1_SIMO 0x0136 |
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#define MCSPI1_CS0 0x0138 |
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#define MCSPI1_CS1 0x013A |
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#define MCSPI1_CS2 0x013C |
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#define MCSPI1_CS3 0x013E |
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#define UART3_CTS_RCTX 0x0140 |
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#define UART3_RTS_SD 0x0142 |
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#define UART3_RX_IRRX 0x0144 |
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#define UART3_TX_IRTX 0x0146 |
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#define SDMMC5_CLK 0x0148 |
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#define SDMMC5_CMD 0x014A |
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#define SDMMC5_DAT0 0x014C |
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#define SDMMC5_DAT1 0x014E |
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#define SDMMC5_DAT2 0x0150 |
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#define SDMMC5_DAT3 0x0152 |
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#define MCSPI4_CLK 0x0154 |
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#define MCSPI4_SIMO 0x0156 |
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#define MCSPI4_SOMI 0x0158 |
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#define MCSPI4_CS0 0x015A |
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#define UART4_RX 0x015C |
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#define UART4_TX 0x015E |
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#define USBB2_ULPITLL_CLK 0x0160 |
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#define USBB2_ULPITLL_STP 0x0162 |
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#define USBB2_ULPITLL_DIR 0x0164 |
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#define USBB2_ULPITLL_NXT 0x0166 |
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#define USBB2_ULPITLL_DAT0 0x0168 |
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#define USBB2_ULPITLL_DAT1 0x016A |
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#define USBB2_ULPITLL_DAT2 0x016C |
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#define USBB2_ULPITLL_DAT3 0x016E |
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#define USBB2_ULPITLL_DAT4 0x0170 |
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#define USBB2_ULPITLL_DAT5 0x0172 |
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#define USBB2_ULPITLL_DAT6 0x0174 |
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#define USBB2_ULPITLL_DAT7 0x0176 |
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#define USBB2_HSIC_DATA 0x0178 |
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#define USBB2_HSIC_STROBE 0x017A |
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#define UNIPRO_TX0 0x017C |
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#define UNIPRO_TY0 0x017E |
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#define UNIPRO_TX1 0x0180 |
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#define UNIPRO_TY1 0x0182 |
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#define UNIPRO_TX2 0x0184 |
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#define UNIPRO_TY2 0x0186 |
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#define UNIPRO_RX0 0x0188 |
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#define UNIPRO_RY0 0x018A |
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#define UNIPRO_RX1 0x018C |
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#define UNIPRO_RY1 0x018E |
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#define UNIPRO_RX2 0x0190 |
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#define UNIPRO_RY2 0x0192 |
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#define USBA0_OTG_CE 0x0194 |
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#define USBA0_OTG_DP 0x0196 |
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#define USBA0_OTG_DM 0x0198 |
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#define FREF_CLK1_OUT 0x019A |
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#define FREF_CLK2_OUT 0x019C |
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#define SYS_NIRQ1 0x019E |
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#define SYS_NIRQ2 0x01A0 |
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#define SYS_BOOT0 0x01A2 |
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#define SYS_BOOT1 0x01A4 |
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#define SYS_BOOT2 0x01A6 |
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#define SYS_BOOT3 0x01A8 |
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#define SYS_BOOT4 0x01AA |
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#define SYS_BOOT5 0x01AC |
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#define DPM_EMU0 0x01AE |
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#define DPM_EMU1 0x01B0 |
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#define DPM_EMU2 0x01B2 |
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#define DPM_EMU3 0x01B4 |
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#define DPM_EMU4 0x01B6 |
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#define DPM_EMU5 0x01B8 |
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#define DPM_EMU6 0x01BA |
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#define DPM_EMU7 0x01BC |
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#define DPM_EMU8 0x01BE |
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#define DPM_EMU9 0x01C0 |
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#define DPM_EMU10 0x01C2 |
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#define DPM_EMU11 0x01C4 |
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#define DPM_EMU12 0x01C6 |
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#define DPM_EMU13 0x01C8 |
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#define DPM_EMU14 0x01CA |
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#define DPM_EMU15 0x01CC |
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#define DPM_EMU16 0x01CE |
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#define DPM_EMU17 0x01D0 |
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#define DPM_EMU18 0x01D2 |
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#define DPM_EMU19 0x01D4 |
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#define WAKEUPEVENT_0 0x01D8 |
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#define WAKEUPEVENT_1 0x01DC |
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#define WAKEUPEVENT_2 0x01E0 |
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#define WAKEUPEVENT_3 0x01E4 |
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#define WAKEUPEVENT_4 0x01E8 |
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#define WAKEUPEVENT_5 0x01EC |
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#define WAKEUPEVENT_6 0x01F0 |
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|
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#define WKUP_REVISION 0x0000 |
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#define WKUP_HWINFO 0x0004 |
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#define WKUP_SYSCONFIG 0x0010 |
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#define PAD0_SIM_IO 0x0040 |
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#define PAD1_SIM_CLK 0x0042 |
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#define PAD0_SIM_RESET 0x0044 |
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#define PAD1_SIM_CD 0x0046 |
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#define PAD0_SIM_PWRCTRL 0x0048 |
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#define PAD1_SR_SCL 0x004A |
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#define PAD0_SR_SDA 0x004C |
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#define PAD1_FREF_XTAL_IN 0x004E |
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#define PAD0_FREF_SLICER_IN 0x0050 |
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#define PAD1_FREF_CLK_IOREQ 0x0052 |
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#define PAD0_FREF_CLK0_OUT 0x0054 |
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#define PAD1_FREF_CLK3_REQ 0x0056 |
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#define PAD0_FREF_CLK3_OUT 0x0058 |
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#define PAD1_FREF_CLK4_REQ 0x005A |
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#define PAD0_FREF_CLK4_OUT 0x005C |
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#define PAD1_SYS_32K 0x005E |
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#define PAD0_SYS_NRESPWRON 0x0060 |
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#define PAD1_SYS_NRESWARM 0x0062 |
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#define PAD0_SYS_PWR_REQ 0x0064 |
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#define PAD1_SYS_PWRON_RESET 0x0066 |
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#define PAD0_SYS_BOOT6 0x0068 |
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#define PAD1_SYS_BOOT7 0x006A |
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#define PAD0_JTAG_NTRST 0x006C |
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#define PAD1_JTAG_TCK 0x006D |
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#define PAD0_JTAG_RTCK 0x0070 |
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#define PAD1_JTAG_TMS_TMSC 0x0072 |
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#define PAD0_JTAG_TDI 0x0074 |
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#define PAD1_JTAG_TDO 0x0076 |
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#define PADCONF_WAKEUPEVENT_0 0x007C |
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#define CONTROL_SMART1NOPMIO_PADCONF_0 0x05A0 |
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#define CONTROL_SMART1NOPMIO_PADCONF_1 0x05A4 |
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#define PADCONF_MODE 0x05A8 |
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#define CONTROL_XTAL_OSCILLATOR 0x05AC |
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#define CONTROL_CONTROL_I2C_2 0x0604 |
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#define CONTROL_CONTROL_JTAG 0x0608 |
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#define CONTROL_CONTROL_SYS 0x060C |
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#define CONTROL_SPARE_RW 0x0614 |
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#define CONTROL_SPARE_R 0x0618 |
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#define CONTROL_SPARE_R_C0 0x061C |
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|
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#endif /* _MUX_OMAP4_H_ */ |
@ -0,0 +1,71 @@ |
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/*
|
||||
* (C) Copyright 2009 SAMSUNG Electronics |
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* Minkyu Kang <mk7.kang@samsung.com> |
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* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or |
||||
* (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
||||
* |
||||
*/ |
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|
||||
#ifndef __ASM_ARCH_MMC_H_ |
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#define __ASM_ARCH_MMC_H_ |
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|
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#ifndef __ASSEMBLY__ |
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struct s5p_mmc { |
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unsigned int sysad; |
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unsigned short blksize; |
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unsigned short blkcnt; |
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unsigned int argument; |
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unsigned short trnmod; |
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unsigned short cmdreg; |
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unsigned int rspreg0; |
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unsigned int rspreg1; |
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unsigned int rspreg2; |
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unsigned int rspreg3; |
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unsigned int bdata; |
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unsigned int prnsts; |
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unsigned char hostctl; |
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unsigned char pwrcon; |
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unsigned char blkgap; |
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unsigned char wakcon; |
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unsigned short clkcon; |
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unsigned char timeoutcon; |
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unsigned char swrst; |
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unsigned int norintsts; /* errintsts */ |
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unsigned int norintstsen; /* errintstsen */ |
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unsigned int norintsigen; /* errintsigen */ |
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unsigned short acmd12errsts; |
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unsigned char res1[2]; |
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unsigned int capareg; |
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unsigned char res2[4]; |
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unsigned int maxcurr; |
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unsigned char res3[0x34]; |
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unsigned int control2; |
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unsigned int control3; |
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unsigned int control4; |
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unsigned char res4[0x6e]; |
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unsigned short hcver; |
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unsigned char res5[0xFFF00]; |
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}; |
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|
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struct mmc_host { |
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struct s5p_mmc *reg; |
||||
unsigned int version; /* SDHCI spec. version */ |
||||
unsigned int clock; /* Current clock (MHz) */ |
||||
}; |
||||
|
||||
int s5p_mmc_init(int dev_index); |
||||
|
||||
#endif /* __ASSEMBLY__ */ |
||||
#endif |
@ -0,0 +1,265 @@ |
||||
/*
|
||||
* (C) Copyright 2010 |
||||
* Texas Instruments Incorporated, <www.ti.com> |
||||
* |
||||
* Balaji Krishnamoorthy <balajitk@ti.com> |
||||
* Aneesh V <aneesh@ti.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef _PANDA_H_ |
||||
#define _PANDA_H_ |
||||
|
||||
#include <asm/io.h> |
||||
#include <asm/arch/mux_omap4.h> |
||||
|
||||
const struct pad_conf_entry core_padconf_array[] = { |
||||
{GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */ |
||||
{GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */ |
||||
{GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */ |
||||
{GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */ |
||||
{GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */ |
||||
{GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */ |
||||
{GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */ |
||||
{GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */ |
||||
{GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* gpio_32 */ |
||||
{GPMC_AD9, (PTU | IEN | M3)}, /* gpio_33 */ |
||||
{GPMC_AD10, (PTU | IEN | M3)}, /* gpio_34 */ |
||||
{GPMC_AD11, (PTU | IEN | M3)}, /* gpio_35 */ |
||||
{GPMC_AD12, (PTU | IEN | M3)}, /* gpio_36 */ |
||||
{GPMC_AD13, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_37 */ |
||||
{GPMC_AD14, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_38 */ |
||||
{GPMC_AD15, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_39 */ |
||||
{GPMC_A16, (M3)}, /* gpio_40 */ |
||||
{GPMC_A17, (PTD | M3)}, /* gpio_41 */ |
||||
{GPMC_A18, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row6 */ |
||||
{GPMC_A19, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row7 */ |
||||
{GPMC_A20, (IEN | M3)}, /* gpio_44 */ |
||||
{GPMC_A21, (M3)}, /* gpio_45 */ |
||||
{GPMC_A22, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col6 */ |
||||
{GPMC_A23, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col7 */ |
||||
{GPMC_A24, (PTD | M3)}, /* gpio_48 */ |
||||
{GPMC_A25, (PTD | M3)}, /* gpio_49 */ |
||||
{GPMC_NCS0, (M3)}, /* gpio_50 */ |
||||
{GPMC_NCS1, (IEN | M3)}, /* gpio_51 */ |
||||
{GPMC_NCS2, (IEN | M3)}, /* gpio_52 */ |
||||
{GPMC_NCS3, (IEN | M3)}, /* gpio_53 */ |
||||
{GPMC_NWP, (M3)}, /* gpio_54 */ |
||||
{GPMC_CLK, (PTD | M3)}, /* gpio_55 */ |
||||
{GPMC_NADV_ALE, (M3)}, /* gpio_56 */ |
||||
{GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)}, /* sdmmc2_clk */ |
||||
{GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */ |
||||
{GPMC_NBE0_CLE, (M3)}, /* gpio_59 */ |
||||
{GPMC_NBE1, (PTD | M3)}, /* gpio_60 */ |
||||
{GPMC_WAIT0, (PTU | IEN | M3)}, /* gpio_61 */ |
||||
{GPMC_WAIT1, (IEN | M3)}, /* gpio_62 */ |
||||
{C2C_DATA11, (PTD | M3)}, /* gpio_100 */ |
||||
{C2C_DATA12, (M1)}, /* dsi1_te0 */ |
||||
{C2C_DATA13, (PTD | M3)}, /* gpio_102 */ |
||||
{C2C_DATA14, (M1)}, /* dsi2_te0 */ |
||||
{C2C_DATA15, (PTD | M3)}, /* gpio_104 */ |
||||
{HDMI_HPD, (M0)}, /* hdmi_hpd */ |
||||
{HDMI_CEC, (M0)}, /* hdmi_cec */ |
||||
{HDMI_DDC_SCL, (PTU | M0)}, /* hdmi_ddc_scl */ |
||||
{HDMI_DDC_SDA, (PTU | IEN | M0)}, /* hdmi_ddc_sda */ |
||||
{CSI21_DX0, (IEN | M0)}, /* csi21_dx0 */ |
||||
{CSI21_DY0, (IEN | M0)}, /* csi21_dy0 */ |
||||
{CSI21_DX1, (IEN | M0)}, /* csi21_dx1 */ |
||||
{CSI21_DY1, (IEN | M0)}, /* csi21_dy1 */ |
||||
{CSI21_DX2, (IEN | M0)}, /* csi21_dx2 */ |
||||
{CSI21_DY2, (IEN | M0)}, /* csi21_dy2 */ |
||||
{CSI21_DX3, (PTD | M7)}, /* csi21_dx3 */ |
||||
{CSI21_DY3, (PTD | M7)}, /* csi21_dy3 */ |
||||
{CSI21_DX4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dx4 */ |
||||
{CSI21_DY4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dy4 */ |
||||
{CSI22_DX0, (IEN | M0)}, /* csi22_dx0 */ |
||||
{CSI22_DY0, (IEN | M0)}, /* csi22_dy0 */ |
||||
{CSI22_DX1, (IEN | M0)}, /* csi22_dx1 */ |
||||
{CSI22_DY1, (IEN | M0)}, /* csi22_dy1 */ |
||||
{CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_shutter */ |
||||
{CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_strobe */ |
||||
{CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_83 */ |
||||
{USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */ |
||||
{USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)}, /* usbb1_ulpiphy_stp */ |
||||
{USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dir */ |
||||
{USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_nxt */ |
||||
{USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat0 */ |
||||
{USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat1 */ |
||||
{USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat2 */ |
||||
{USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat3 */ |
||||
{USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat4 */ |
||||
{USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat5 */ |
||||
{USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat6 */ |
||||
{USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat7 */ |
||||
{USBB1_HSIC_DATA, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_data */ |
||||
{USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_strobe */ |
||||
{USBC1_ICUSB_DP, (IEN | M0)}, /* usbc1_icusb_dp */ |
||||
{USBC1_ICUSB_DM, (IEN | M0)}, /* usbc1_icusb_dm */ |
||||
{SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc1_clk */ |
||||
{SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */ |
||||
{SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */ |
||||
{SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */ |
||||
{SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */ |
||||
{SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */ |
||||
{SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat4 */ |
||||
{SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat5 */ |
||||
{SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat6 */ |
||||
{SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat7 */ |
||||
{ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_clkx */ |
||||
{ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dr */ |
||||
{ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dx */ |
||||
{ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_fsx */ |
||||
{ABE_MCBSP1_CLKX, (IEN | M1)}, /* abe_slimbus1_clock */ |
||||
{ABE_MCBSP1_DR, (IEN | M1)}, /* abe_slimbus1_data */ |
||||
{ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp1_dx */ |
||||
{ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp1_fsx */ |
||||
{ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_ul_data */ |
||||
{ABE_PDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_dl_data */ |
||||
{ABE_PDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_frame */ |
||||
{ABE_PDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_lb_clk */ |
||||
{ABE_CLKS, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_clks */ |
||||
{ABE_DMIC_CLK1, (M0)}, /* abe_dmic_clk1 */ |
||||
{ABE_DMIC_DIN1, (IEN | M0)}, /* abe_dmic_din1 */ |
||||
{ABE_DMIC_DIN2, (IEN | M0)}, /* abe_dmic_din2 */ |
||||
{ABE_DMIC_DIN3, (IEN | M0)}, /* abe_dmic_din3 */ |
||||
{UART2_CTS, (PTU | IEN | M0)}, /* uart2_cts */ |
||||
{UART2_RTS, (M0)}, /* uart2_rts */ |
||||
{UART2_RX, (PTU | IEN | M0)}, /* uart2_rx */ |
||||
{UART2_TX, (M0)}, /* uart2_tx */ |
||||
{HDQ_SIO, (M3)}, /* gpio_127 */ |
||||
{I2C1_SCL, (PTU | IEN | M0)}, /* i2c1_scl */ |
||||
{I2C1_SDA, (PTU | IEN | M0)}, /* i2c1_sda */ |
||||
{I2C2_SCL, (PTU | IEN | M0)}, /* i2c2_scl */ |
||||
{I2C2_SDA, (PTU | IEN | M0)}, /* i2c2_sda */ |
||||
{I2C3_SCL, (PTU | IEN | M0)}, /* i2c3_scl */ |
||||
{I2C3_SDA, (PTU | IEN | M0)}, /* i2c3_sda */ |
||||
{I2C4_SCL, (PTU | IEN | M0)}, /* i2c4_scl */ |
||||
{I2C4_SDA, (PTU | IEN | M0)}, /* i2c4_sda */ |
||||
{MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_clk */ |
||||
{MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_somi */ |
||||
{MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_simo */ |
||||
{MCSPI1_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_cs0 */ |
||||
{MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* mcspi1_cs1 */ |
||||
{MCSPI1_CS2, (PTU | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_139 */ |
||||
{MCSPI1_CS3, (PTU | IEN | M3)}, /* gpio_140 */ |
||||
{UART3_CTS_RCTX, (PTU | IEN | M0)}, /* uart3_tx */ |
||||
{UART3_RTS_SD, (M0)}, /* uart3_rts_sd */ |
||||
{UART3_RX_IRRX, (IEN | M0)}, /* uart3_rx */ |
||||
{UART3_TX_IRTX, (M0)}, /* uart3_tx */ |
||||
{SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc5_clk */ |
||||
{SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_cmd */ |
||||
{SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat0 */ |
||||
{SDMMC5_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat1 */ |
||||
{SDMMC5_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat2 */ |
||||
{SDMMC5_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat3 */ |
||||
{MCSPI4_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_clk */ |
||||
{MCSPI4_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_simo */ |
||||
{MCSPI4_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_somi */ |
||||
{MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_cs0 */ |
||||
{UART4_RX, (IEN | M0)}, /* uart4_rx */ |
||||
{UART4_TX, (M0)}, /* uart4_tx */ |
||||
{USBB2_ULPITLL_CLK, (IEN | M3)}, /* gpio_157 */ |
||||
{USBB2_ULPITLL_STP, (IEN | M5)}, /* dispc2_data23 */ |
||||
{USBB2_ULPITLL_DIR, (IEN | M5)}, /* dispc2_data22 */ |
||||
{USBB2_ULPITLL_NXT, (IEN | M5)}, /* dispc2_data21 */ |
||||
{USBB2_ULPITLL_DAT0, (IEN | M5)}, /* dispc2_data20 */ |
||||
{USBB2_ULPITLL_DAT1, (IEN | M5)}, /* dispc2_data19 */ |
||||
{USBB2_ULPITLL_DAT2, (IEN | M5)}, /* dispc2_data18 */ |
||||
{USBB2_ULPITLL_DAT3, (IEN | M5)}, /* dispc2_data15 */ |
||||
{USBB2_ULPITLL_DAT4, (IEN | M5)}, /* dispc2_data14 */ |
||||
{USBB2_ULPITLL_DAT5, (IEN | M5)}, /* dispc2_data13 */ |
||||
{USBB2_ULPITLL_DAT6, (IEN | M5)}, /* dispc2_data12 */ |
||||
{USBB2_ULPITLL_DAT7, (IEN | M5)}, /* dispc2_data11 */ |
||||
{USBB2_HSIC_DATA, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_169 */ |
||||
{USBB2_HSIC_STROBE, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_170 */ |
||||
{UNIPRO_TX0, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col0 */ |
||||
{UNIPRO_TY0, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col1 */ |
||||
{UNIPRO_TX1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col2 */ |
||||
{UNIPRO_TY1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col3 */ |
||||
{UNIPRO_TX2, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* gpio_0 */ |
||||
{UNIPRO_TY2, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* gpio_1 */ |
||||
{UNIPRO_RX0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row0 */ |
||||
{UNIPRO_RY0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row1 */ |
||||
{UNIPRO_RX1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row2 */ |
||||
{UNIPRO_RY1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row3 */ |
||||
{UNIPRO_RX2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row4 */ |
||||
{UNIPRO_RY2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row5 */ |
||||
{USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* usba0_otg_ce */ |
||||
{USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dp */ |
||||
{USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dm */ |
||||
{FREF_CLK1_OUT, (M0)}, /* fref_clk1_out */ |
||||
{FREF_CLK2_OUT, (M0)}, /* fref_clk2_out */ |
||||
{SYS_NIRQ1, (PTU | IEN | M0)}, /* sys_nirq1 */ |
||||
{SYS_NIRQ2, (PTU | IEN | M0)}, /* sys_nirq2 */ |
||||
{SYS_BOOT0, (PTU | IEN | M3)}, /* gpio_184 */ |
||||
{SYS_BOOT1, (M3)}, /* gpio_185 */ |
||||
{SYS_BOOT2, (PTD | IEN | M3)}, /* gpio_186 */ |
||||
{SYS_BOOT3, (M3)}, /* gpio_187 */ |
||||
{SYS_BOOT4, (M3)}, /* gpio_188 */ |
||||
{SYS_BOOT5, (PTD | IEN | M3)}, /* gpio_189 */ |
||||
{DPM_EMU0, (IEN | M0)}, /* dpm_emu0 */ |
||||
{DPM_EMU1, (IEN | M0)}, /* dpm_emu1 */ |
||||
{DPM_EMU2, (IEN | M0)}, /* dpm_emu2 */ |
||||
{DPM_EMU3, (IEN | M5)}, /* dispc2_data10 */ |
||||
{DPM_EMU4, (IEN | M5)}, /* dispc2_data9 */ |
||||
{DPM_EMU5, (IEN | M5)}, /* dispc2_data16 */ |
||||
{DPM_EMU6, (IEN | M5)}, /* dispc2_data17 */ |
||||
{DPM_EMU7, (IEN | M5)}, /* dispc2_hsync */ |
||||
{DPM_EMU8, (IEN | M5)}, /* dispc2_pclk */ |
||||
{DPM_EMU9, (IEN | M5)}, /* dispc2_vsync */ |
||||
{DPM_EMU10, (IEN | M5)}, /* dispc2_de */ |
||||
{DPM_EMU11, (IEN | M5)}, /* dispc2_data8 */ |
||||
{DPM_EMU12, (IEN | M5)}, /* dispc2_data7 */ |
||||
{DPM_EMU13, (IEN | M5)}, /* dispc2_data6 */ |
||||
{DPM_EMU14, (IEN | M5)}, /* dispc2_data5 */ |
||||
{DPM_EMU15, (IEN | M5)}, /* dispc2_data4 */ |
||||
{DPM_EMU16, (IEN | M5)}, /* dispc2_data3 */ |
||||
{DPM_EMU17, (IEN | M5)}, /* dispc2_data2 */ |
||||
{DPM_EMU18, (IEN | M5)}, /* dispc2_data1 */ |
||||
{DPM_EMU19, (IEN | M5)}, /* dispc2_data0 */ |
||||
}; |
||||
|
||||
const struct pad_conf_entry wkup_padconf_array[] = { |
||||
{PAD0_SIM_IO, (IEN | M0)}, /* sim_io */ |
||||
{PAD1_SIM_CLK, (M0)}, /* sim_clk */ |
||||
{PAD0_SIM_RESET, (M0)}, /* sim_reset */ |
||||
{PAD1_SIM_CD, (PTU | IEN | M0)}, /* sim_cd */ |
||||
{PAD0_SIM_PWRCTRL, (M0)}, /* sim_pwrctrl */ |
||||
{PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */ |
||||
{PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */ |
||||
{PAD1_FREF_XTAL_IN, (M0)}, /* # */ |
||||
{PAD0_FREF_SLICER_IN, (M0)}, /* fref_slicer_in */ |
||||
{PAD1_FREF_CLK_IOREQ, (M0)}, /* fref_clk_ioreq */ |
||||
{PAD0_FREF_CLK0_OUT, (M2)}, /* sys_drm_msecure */ |
||||
{PAD1_FREF_CLK3_REQ, (PTU | IEN | M0)}, /* # */ |
||||
{PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */ |
||||
{PAD1_FREF_CLK4_REQ, (PTU | IEN | M0)}, /* # */ |
||||
{PAD0_FREF_CLK4_OUT, (M0)}, /* # */ |
||||
{PAD1_SYS_32K, (IEN | M0)}, /* sys_32k */ |
||||
{PAD0_SYS_NRESPWRON, (M0)}, /* sys_nrespwron */ |
||||
{PAD1_SYS_NRESWARM, (M0)}, /* sys_nreswarm */ |
||||
{PAD0_SYS_PWR_REQ, (PTU | M0)}, /* sys_pwr_req */ |
||||
{PAD1_SYS_PWRON_RESET, (M3)}, /* gpio_wk29 */ |
||||
{PAD0_SYS_BOOT6, (IEN | M3)}, /* gpio_wk9 */ |
||||
{PAD1_SYS_BOOT7, (IEN | M3)}, /* gpio_wk10 */ |
||||
}; |
||||
|
||||
#endif |
||||
|
@ -0,0 +1,265 @@ |
||||
/*
|
||||
* (C) Copyright 2010 |
||||
* Texas Instruments Incorporated, <www.ti.com> |
||||
* |
||||
* Balaji Krishnamoorthy <balajitk@ti.com> |
||||
* Aneesh V <aneesh@ti.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef _SDP_H_ |
||||
#define _SDP_H_ |
||||
|
||||
#include <asm/io.h> |
||||
#include <asm/arch/mux_omap4.h> |
||||
|
||||
const struct pad_conf_entry core_padconf_array[] = { |
||||
{GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */ |
||||
{GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */ |
||||
{GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */ |
||||
{GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */ |
||||
{GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */ |
||||
{GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */ |
||||
{GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */ |
||||
{GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */ |
||||
{GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* gpio_32 */ |
||||
{GPMC_AD9, (PTU | IEN | M3)}, /* gpio_33 */ |
||||
{GPMC_AD10, (PTU | IEN | M3)}, /* gpio_34 */ |
||||
{GPMC_AD11, (PTU | IEN | M3)}, /* gpio_35 */ |
||||
{GPMC_AD12, (PTU | IEN | M3)}, /* gpio_36 */ |
||||
{GPMC_AD13, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_37 */ |
||||
{GPMC_AD14, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_38 */ |
||||
{GPMC_AD15, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_39 */ |
||||
{GPMC_A16, (M3)}, /* gpio_40 */ |
||||
{GPMC_A17, (PTD | M3)}, /* gpio_41 */ |
||||
{GPMC_A18, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row6 */ |
||||
{GPMC_A19, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row7 */ |
||||
{GPMC_A20, (IEN | M3)}, /* gpio_44 */ |
||||
{GPMC_A21, (M3)}, /* gpio_45 */ |
||||
{GPMC_A22, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col6 */ |
||||
{GPMC_A23, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col7 */ |
||||
{GPMC_A24, (PTD | M3)}, /* gpio_48 */ |
||||
{GPMC_A25, (PTD | M3)}, /* gpio_49 */ |
||||
{GPMC_NCS0, (M3)}, /* gpio_50 */ |
||||
{GPMC_NCS1, (IEN | M3)}, /* gpio_51 */ |
||||
{GPMC_NCS2, (IEN | M3)}, /* gpio_52 */ |
||||
{GPMC_NCS3, (IEN | M3)}, /* gpio_53 */ |
||||
{GPMC_NWP, (M3)}, /* gpio_54 */ |
||||
{GPMC_CLK, (PTD | M3)}, /* gpio_55 */ |
||||
{GPMC_NADV_ALE, (M3)}, /* gpio_56 */ |
||||
{GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)}, /* sdmmc2_clk */ |
||||
{GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */ |
||||
{GPMC_NBE0_CLE, (M3)}, /* gpio_59 */ |
||||
{GPMC_NBE1, (PTD | M3)}, /* gpio_60 */ |
||||
{GPMC_WAIT0, (PTU | IEN | M3)}, /* gpio_61 */ |
||||
{GPMC_WAIT1, (IEN | M3)}, /* gpio_62 */ |
||||
{C2C_DATA11, (PTD | M3)}, /* gpio_100 */ |
||||
{C2C_DATA12, (M1)}, /* dsi1_te0 */ |
||||
{C2C_DATA13, (PTD | M3)}, /* gpio_102 */ |
||||
{C2C_DATA14, (M1)}, /* dsi2_te0 */ |
||||
{C2C_DATA15, (PTD | M3)}, /* gpio_104 */ |
||||
{HDMI_HPD, (M0)}, /* hdmi_hpd */ |
||||
{HDMI_CEC, (M0)}, /* hdmi_cec */ |
||||
{HDMI_DDC_SCL, (PTU | M0)}, /* hdmi_ddc_scl */ |
||||
{HDMI_DDC_SDA, (PTU | IEN | M0)}, /* hdmi_ddc_sda */ |
||||
{CSI21_DX0, (IEN | M0)}, /* csi21_dx0 */ |
||||
{CSI21_DY0, (IEN | M0)}, /* csi21_dy0 */ |
||||
{CSI21_DX1, (IEN | M0)}, /* csi21_dx1 */ |
||||
{CSI21_DY1, (IEN | M0)}, /* csi21_dy1 */ |
||||
{CSI21_DX2, (IEN | M0)}, /* csi21_dx2 */ |
||||
{CSI21_DY2, (IEN | M0)}, /* csi21_dy2 */ |
||||
{CSI21_DX3, (PTD | M7)}, /* csi21_dx3 */ |
||||
{CSI21_DY3, (PTD | M7)}, /* csi21_dy3 */ |
||||
{CSI21_DX4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dx4 */ |
||||
{CSI21_DY4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dy4 */ |
||||
{CSI22_DX0, (IEN | M0)}, /* csi22_dx0 */ |
||||
{CSI22_DY0, (IEN | M0)}, /* csi22_dy0 */ |
||||
{CSI22_DX1, (IEN | M0)}, /* csi22_dx1 */ |
||||
{CSI22_DY1, (IEN | M0)}, /* csi22_dy1 */ |
||||
{CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_shutter */ |
||||
{CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_strobe */ |
||||
{CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_83 */ |
||||
{USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */ |
||||
{USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)}, /* usbb1_ulpiphy_stp */ |
||||
{USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dir */ |
||||
{USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_nxt */ |
||||
{USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat0 */ |
||||
{USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat1 */ |
||||
{USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat2 */ |
||||
{USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat3 */ |
||||
{USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat4 */ |
||||
{USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat5 */ |
||||
{USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat6 */ |
||||
{USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat7 */ |
||||
{USBB1_HSIC_DATA, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_data */ |
||||
{USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_strobe */ |
||||
{USBC1_ICUSB_DP, (IEN | M0)}, /* usbc1_icusb_dp */ |
||||
{USBC1_ICUSB_DM, (IEN | M0)}, /* usbc1_icusb_dm */ |
||||
{SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc1_clk */ |
||||
{SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */ |
||||
{SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */ |
||||
{SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */ |
||||
{SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */ |
||||
{SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */ |
||||
{SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat4 */ |
||||
{SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat5 */ |
||||
{SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat6 */ |
||||
{SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat7 */ |
||||
{ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_clkx */ |
||||
{ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dr */ |
||||
{ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dx */ |
||||
{ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_fsx */ |
||||
{ABE_MCBSP1_CLKX, (IEN | M1)}, /* abe_slimbus1_clock */ |
||||
{ABE_MCBSP1_DR, (IEN | M1)}, /* abe_slimbus1_data */ |
||||
{ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp1_dx */ |
||||
{ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp1_fsx */ |
||||
{ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_ul_data */ |
||||
{ABE_PDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_dl_data */ |
||||
{ABE_PDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_frame */ |
||||
{ABE_PDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_lb_clk */ |
||||
{ABE_CLKS, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_clks */ |
||||
{ABE_DMIC_CLK1, (M0)}, /* abe_dmic_clk1 */ |
||||
{ABE_DMIC_DIN1, (IEN | M0)}, /* abe_dmic_din1 */ |
||||
{ABE_DMIC_DIN2, (IEN | M0)}, /* abe_dmic_din2 */ |
||||
{ABE_DMIC_DIN3, (IEN | M0)}, /* abe_dmic_din3 */ |
||||
{UART2_CTS, (PTU | IEN | M0)}, /* uart2_cts */ |
||||
{UART2_RTS, (M0)}, /* uart2_rts */ |
||||
{UART2_RX, (PTU | IEN | M0)}, /* uart2_rx */ |
||||
{UART2_TX, (M0)}, /* uart2_tx */ |
||||
{HDQ_SIO, (M3)}, /* gpio_127 */ |
||||
{I2C1_SCL, (PTU | IEN | M0)}, /* i2c1_scl */ |
||||
{I2C1_SDA, (PTU | IEN | M0)}, /* i2c1_sda */ |
||||
{I2C2_SCL, (PTU | IEN | M0)}, /* i2c2_scl */ |
||||
{I2C2_SDA, (PTU | IEN | M0)}, /* i2c2_sda */ |
||||
{I2C3_SCL, (PTU | IEN | M0)}, /* i2c3_scl */ |
||||
{I2C3_SDA, (PTU | IEN | M0)}, /* i2c3_sda */ |
||||
{I2C4_SCL, (PTU | IEN | M0)}, /* i2c4_scl */ |
||||
{I2C4_SDA, (PTU | IEN | M0)}, /* i2c4_sda */ |
||||
{MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_clk */ |
||||
{MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_somi */ |
||||
{MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_simo */ |
||||
{MCSPI1_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_cs0 */ |
||||
{MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* mcspi1_cs1 */ |
||||
{MCSPI1_CS2, (PTU | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_139 */ |
||||
{MCSPI1_CS3, (PTU | IEN | M3)}, /* gpio_140 */ |
||||
{UART3_CTS_RCTX, (PTU | IEN | M0)}, /* uart3_tx */ |
||||
{UART3_RTS_SD, (M0)}, /* uart3_rts_sd */ |
||||
{UART3_RX_IRRX, (IEN | M0)}, /* uart3_rx */ |
||||
{UART3_TX_IRTX, (M0)}, /* uart3_tx */ |
||||
{SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc5_clk */ |
||||
{SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_cmd */ |
||||
{SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat0 */ |
||||
{SDMMC5_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat1 */ |
||||
{SDMMC5_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat2 */ |
||||
{SDMMC5_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat3 */ |
||||
{MCSPI4_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_clk */ |
||||
{MCSPI4_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_simo */ |
||||
{MCSPI4_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_somi */ |
||||
{MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_cs0 */ |
||||
{UART4_RX, (IEN | M0)}, /* uart4_rx */ |
||||
{UART4_TX, (M0)}, /* uart4_tx */ |
||||
{USBB2_ULPITLL_CLK, (IEN | M3)}, /* gpio_157 */ |
||||
{USBB2_ULPITLL_STP, (IEN | M5)}, /* dispc2_data23 */ |
||||
{USBB2_ULPITLL_DIR, (IEN | M5)}, /* dispc2_data22 */ |
||||
{USBB2_ULPITLL_NXT, (IEN | M5)}, /* dispc2_data21 */ |
||||
{USBB2_ULPITLL_DAT0, (IEN | M5)}, /* dispc2_data20 */ |
||||
{USBB2_ULPITLL_DAT1, (IEN | M5)}, /* dispc2_data19 */ |
||||
{USBB2_ULPITLL_DAT2, (IEN | M5)}, /* dispc2_data18 */ |
||||
{USBB2_ULPITLL_DAT3, (IEN | M5)}, /* dispc2_data15 */ |
||||
{USBB2_ULPITLL_DAT4, (IEN | M5)}, /* dispc2_data14 */ |
||||
{USBB2_ULPITLL_DAT5, (IEN | M5)}, /* dispc2_data13 */ |
||||
{USBB2_ULPITLL_DAT6, (IEN | M5)}, /* dispc2_data12 */ |
||||
{USBB2_ULPITLL_DAT7, (IEN | M5)}, /* dispc2_data11 */ |
||||
{USBB2_HSIC_DATA, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_169 */ |
||||
{USBB2_HSIC_STROBE, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_170 */ |
||||
{UNIPRO_TX0, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col0 */ |
||||
{UNIPRO_TY0, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col1 */ |
||||
{UNIPRO_TX1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col2 */ |
||||
{UNIPRO_TY1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col3 */ |
||||
{UNIPRO_TX2, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col4 */ |
||||
{UNIPRO_TY2, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col5 */ |
||||
{UNIPRO_RX0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row0 */ |
||||
{UNIPRO_RY0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row1 */ |
||||
{UNIPRO_RX1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row2 */ |
||||
{UNIPRO_RY1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row3 */ |
||||
{UNIPRO_RX2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row4 */ |
||||
{UNIPRO_RY2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row5 */ |
||||
{USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* usba0_otg_ce */ |
||||
{USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dp */ |
||||
{USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dm */ |
||||
{FREF_CLK1_OUT, (M0)}, /* fref_clk1_out */ |
||||
{FREF_CLK2_OUT, (M0)}, /* fref_clk2_out */ |
||||
{SYS_NIRQ1, (PTU | IEN | M0)}, /* sys_nirq1 */ |
||||
{SYS_NIRQ2, (PTU | IEN | M0)}, /* sys_nirq2 */ |
||||
{SYS_BOOT0, (PTU | IEN | M3)}, /* gpio_184 */ |
||||
{SYS_BOOT1, (M3)}, /* gpio_185 */ |
||||
{SYS_BOOT2, (PTD | IEN | M3)}, /* gpio_186 */ |
||||
{SYS_BOOT3, (M3)}, /* gpio_187 */ |
||||
{SYS_BOOT4, (M3)}, /* gpio_188 */ |
||||
{SYS_BOOT5, (PTD | IEN | M3)}, /* gpio_189 */ |
||||
{DPM_EMU0, (IEN | M0)}, /* dpm_emu0 */ |
||||
{DPM_EMU1, (IEN | M0)}, /* dpm_emu1 */ |
||||
{DPM_EMU2, (IEN | M0)}, /* dpm_emu2 */ |
||||
{DPM_EMU3, (IEN | M5)}, /* dispc2_data10 */ |
||||
{DPM_EMU4, (IEN | M5)}, /* dispc2_data9 */ |
||||
{DPM_EMU5, (IEN | M5)}, /* dispc2_data16 */ |
||||
{DPM_EMU6, (IEN | M5)}, /* dispc2_data17 */ |
||||
{DPM_EMU7, (IEN | M5)}, /* dispc2_hsync */ |
||||
{DPM_EMU8, (IEN | M5)}, /* dispc2_pclk */ |
||||
{DPM_EMU9, (IEN | M5)}, /* dispc2_vsync */ |
||||
{DPM_EMU10, (IEN | M5)}, /* dispc2_de */ |
||||
{DPM_EMU11, (IEN | M5)}, /* dispc2_data8 */ |
||||
{DPM_EMU12, (IEN | M5)}, /* dispc2_data7 */ |
||||
{DPM_EMU13, (IEN | M5)}, /* dispc2_data6 */ |
||||
{DPM_EMU14, (IEN | M5)}, /* dispc2_data5 */ |
||||
{DPM_EMU15, (IEN | M5)}, /* dispc2_data4 */ |
||||
{DPM_EMU16, (M3)}, /* gpio_27 */ |
||||
{DPM_EMU17, (IEN | M5)}, /* dispc2_data2 */ |
||||
{DPM_EMU18, (IEN | M5)}, /* dispc2_data1 */ |
||||
{DPM_EMU19, (IEN | M5)}, /* dispc2_data0 */ |
||||
}; |
||||
|
||||
const struct pad_conf_entry wkup_padconf_array[] = { |
||||
{PAD0_SIM_IO, (IEN | M0)}, /* sim_io */ |
||||
{PAD1_SIM_CLK, (M0)}, /* sim_clk */ |
||||
{PAD0_SIM_RESET, (M0)}, /* sim_reset */ |
||||
{PAD1_SIM_CD, (PTU | IEN | M0)}, /* sim_cd */ |
||||
{PAD0_SIM_PWRCTRL, (M0)}, /* sim_pwrctrl */ |
||||
{PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */ |
||||
{PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */ |
||||
{PAD1_FREF_XTAL_IN, (M0)}, /* # */ |
||||
{PAD0_FREF_SLICER_IN, (M0)}, /* fref_slicer_in */ |
||||
{PAD1_FREF_CLK_IOREQ, (M0)}, /* fref_clk_ioreq */ |
||||
{PAD0_FREF_CLK0_OUT, (M2)}, /* sys_drm_msecure */ |
||||
{PAD1_FREF_CLK3_REQ, (PTU | IEN | M0)}, /* # */ |
||||
{PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */ |
||||
{PAD1_FREF_CLK4_REQ, (PTU | IEN | M0)}, /* # */ |
||||
{PAD0_FREF_CLK4_OUT, (M0)}, /* # */ |
||||
{PAD1_SYS_32K, (IEN | M0)}, /* sys_32k */ |
||||
{PAD0_SYS_NRESPWRON, (M0)}, /* sys_nrespwron */ |
||||
{PAD1_SYS_NRESWARM, (M0)}, /* sys_nreswarm */ |
||||
{PAD0_SYS_PWR_REQ, (PTU | M0)}, /* sys_pwr_req */ |
||||
{PAD1_SYS_PWRON_RESET, (M3)}, /* gpio_wk29 */ |
||||
{PAD0_SYS_BOOT6, (IEN | M3)}, /* gpio_wk9 */ |
||||
{PAD1_SYS_BOOT7, (IEN | M3)}, /* gpio_wk10 */ |
||||
}; |
||||
|
||||
#endif |
||||
|
@ -0,0 +1,140 @@ |
||||
/*
|
||||
* Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr> |
||||
* |
||||
* Written-by: Albert ARIBAUD <albert.aribaud@free.fr> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, |
||||
* MA 02110-1301 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/io.h> |
||||
|
||||
#if defined(CONFIG_ORION5X) |
||||
#include <asm/arch/orion5x.h> |
||||
#elif defined(CONFIG_KIRKWOOD) |
||||
#include <asm/arch/kirkwood.h> |
||||
#endif |
||||
|
||||
/* SATA port registers */ |
||||
struct mvsata_port_registers { |
||||
u32 reserved1[192]; |
||||
/* offset 0x300 : ATA Interface registers */ |
||||
u32 sstatus; |
||||
u32 serror; |
||||
u32 scontrol; |
||||
u32 ltmode; |
||||
u32 phymode3; |
||||
u32 phymode4; |
||||
u32 reserved2[5]; |
||||
u32 phymode1; |
||||
u32 phymode2; |
||||
u32 bist_cr; |
||||
u32 bist_dw1; |
||||
u32 bist_dw2; |
||||
u32 serrorintrmask; |
||||
}; |
||||
|
||||
/*
|
||||
* Sanity checks: |
||||
* - to compile at all, we need CONFIG_SYS_ATA_BASE_ADDR. |
||||
* - for ide_preinit to make sense, we need at least one of |
||||
* CONFIG_SYS_ATA_IDE0_OFFSET or CONFIG_SYS_ATA_IDE0_OFFSET; |
||||
* - for inde_preinit to be called, we need CONFIG_IDE_PREINIT. |
||||
* Fail with an explanation message if these conditions are not met. |
||||
* This is particularly important for CONFIG_IDE_PREINIT, because |
||||
* its lack would not cause a build error. |
||||
*/ |
||||
|
||||
#if !defined(CONFIG_SYS_ATA_BASE_ADDR) |
||||
#error CONFIG_SYS_ATA_BASE_ADDR must be defined |
||||
#elif !defined(CONFIG_SYS_ATA_IDE0_OFFSET) \ |
||||
&& !defined(CONFIG_SYS_ATA_IDE1_OFFSET) |
||||
#error CONFIG_SYS_ATA_IDE0_OFFSET or CONFIG_SYS_ATA_IDE1_OFFSET \ |
||||
must be defined |
||||
#elif !defined(CONFIG_IDE_PREINIT) |
||||
#error CONFIG_IDE_PREINIT must be defined |
||||
#endif |
||||
|
||||
/*
|
||||
* Masks and values for SControl DETection and Interface Power Management, |
||||
* and for SStatus DETection. |
||||
*/ |
||||
|
||||
#define MVSATA_SCONTROL_DET_MASK 0x0000000F |
||||
#define MVSATA_SCONTROL_DET_NONE 0x00000000 |
||||
#define MVSATA_SCONTROL_DET_INIT 0x00000001 |
||||
#define MVSATA_SCONTROL_IPM_MASK 0x00000F00 |
||||
#define MVSATA_SCONTROL_IPM_NO_LP_ALLOWED 0x00000300 |
||||
#define MVSATA_SCONTROL_MASK \ |
||||
(MVSATA_SCONTROL_DET_MASK|MVSATA_SCONTROL_IPM_MASK) |
||||
#define MVSATA_PORT_INIT \ |
||||
(MVSATA_SCONTROL_DET_INIT|MVSATA_SCONTROL_IPM_NO_LP_ALLOWED) |
||||
#define MVSATA_PORT_USE \ |
||||
(MVSATA_SCONTROL_DET_NONE|MVSATA_SCONTROL_IPM_NO_LP_ALLOWED) |
||||
#define MVSATA_SSTATUS_DET_MASK 0x0000000F |
||||
#define MVSATA_SSTATUS_DET_DEVCOMM 0x00000003 |
||||
|
||||
/*
|
||||
* Initialize one MVSATAHC port: set SControl's IPM to "always active" |
||||
* and DET to "reset", then wait for SStatus's DET to become "device and |
||||
* comm ok" (or time out after 50 us if no device), then set SControl's |
||||
* DET back to "no action". |
||||
*/ |
||||
|
||||
static void mvsata_ide_initialize_port(struct mvsata_port_registers *port) |
||||
{ |
||||
u32 control; |
||||
u32 status; |
||||
u32 tout = 50; /* wait at most 50 us for SATA reset to complete */ |
||||
|
||||
control = readl(&port->scontrol); |
||||
control = (control & ~MVSATA_SCONTROL_MASK) | MVSATA_PORT_INIT; |
||||
writel(control, &port->scontrol); |
||||
while (--tout) { |
||||
status = readl(&port->sstatus) & MVSATA_SSTATUS_DET_MASK; |
||||
if (status == MVSATA_SSTATUS_DET_DEVCOMM) |
||||
break; |
||||
udelay(1); |
||||
} |
||||
control = (control & ~MVSATA_SCONTROL_MASK) | MVSATA_PORT_USE; |
||||
writel(control, &port->scontrol); |
||||
} |
||||
|
||||
/*
|
||||
* ide_preinit() will be called by ide_init in cmd_ide.c and will |
||||
* reset the MVSTATHC ports needed by the board. |
||||
*/ |
||||
|
||||
int ide_preinit(void) |
||||
{ |
||||
/* Enable ATA port 0 (could be SATA port 0 or 1) if declared */ |
||||
#if defined(CONFIG_SYS_ATA_IDE0_OFFSET) |
||||
mvsata_ide_initialize_port( |
||||
(struct mvsata_port_registers *) |
||||
(CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET)); |
||||
#endif |
||||
/* Enable ATA port 1 (could be SATA port 0 or 1) if declared */ |
||||
#if defined(CONFIG_SYS_ATA_IDE1_OFFSET) |
||||
mvsata_ide_initialize_port( |
||||
(struct mvsata_port_registers *) |
||||
(CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE1_OFFSET)); |
||||
#endif |
||||
/* return 0 as we always succeed */ |
||||
return 0; |
||||
} |
@ -0,0 +1,478 @@ |
||||
/*
|
||||
* (C) Copyright 2009 SAMSUNG Electronics |
||||
* Minkyu Kang <mk7.kang@samsung.com> |
||||
* Jaehoon Chung <jh80.chung@samsung.com> |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or |
||||
* (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <mmc.h> |
||||
#include <asm/io.h> |
||||
#include <asm/arch/mmc.h> |
||||
|
||||
#ifdef DEBUG_S5P_HSMMC |
||||
#define dbg(x...) printf(x) |
||||
#else |
||||
#define dbg(x...) do { } while (0) |
||||
#endif |
||||
|
||||
/* support 4 mmc hosts */ |
||||
struct mmc mmc_dev[4]; |
||||
struct mmc_host mmc_host[4]; |
||||
|
||||
static inline struct s5p_mmc *s5p_get_base_mmc(int dev_index) |
||||
{ |
||||
unsigned long offset = dev_index * sizeof(struct s5p_mmc); |
||||
|
||||
if (cpu_is_s5pc100()) |
||||
return (struct s5p_mmc *)(S5PC100_MMC_BASE + offset); |
||||
else |
||||
return (struct s5p_mmc *)(S5PC110_MMC_BASE + offset); |
||||
} |
||||
|
||||
static void mmc_prepare_data(struct mmc_host *host, struct mmc_data *data) |
||||
{ |
||||
unsigned char ctrl; |
||||
|
||||
dbg("data->dest: %08x\n", (u32)data->dest); |
||||
writel((u32)data->dest, &host->reg->sysad); |
||||
/*
|
||||
* DMASEL[4:3] |
||||
* 00 = Selects SDMA |
||||
* 01 = Reserved |
||||
* 10 = Selects 32-bit Address ADMA2 |
||||
* 11 = Selects 64-bit Address ADMA2 |
||||
*/ |
||||
ctrl = readb(&host->reg->hostctl); |
||||
ctrl &= ~(3 << 3); |
||||
writeb(ctrl, &host->reg->hostctl); |
||||
|
||||
/* We do not handle DMA boundaries, so set it to max (512 KiB) */ |
||||
writew((7 << 12) | (512 << 0), &host->reg->blksize); |
||||
writew(data->blocks, &host->reg->blkcnt); |
||||
} |
||||
|
||||
static void mmc_set_transfer_mode(struct mmc_host *host, struct mmc_data *data) |
||||
{ |
||||
unsigned short mode; |
||||
|
||||
/*
|
||||
* TRNMOD |
||||
* MUL1SIN0[5] : Multi/Single Block Select |
||||
* RD1WT0[4] : Data Transfer Direction Select |
||||
* 1 = read |
||||
* 0 = write |
||||
* ENACMD12[2] : Auto CMD12 Enable |
||||
* ENBLKCNT[1] : Block Count Enable |
||||
* ENDMA[0] : DMA Enable |
||||
*/ |
||||
mode = (1 << 1) | (1 << 0); |
||||
if (data->blocks > 1) |
||||
mode |= (1 << 5); |
||||
if (data->flags & MMC_DATA_READ) |
||||
mode |= (1 << 4); |
||||
|
||||
writew(mode, &host->reg->trnmod); |
||||
} |
||||
|
||||
static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, |
||||
struct mmc_data *data) |
||||
{ |
||||
struct mmc_host *host = (struct mmc_host *)mmc->priv; |
||||
int flags, i; |
||||
unsigned int timeout; |
||||
unsigned int mask; |
||||
unsigned int retry = 0x100000; |
||||
|
||||
/* Wait max 10 ms */ |
||||
timeout = 10; |
||||
|
||||
/*
|
||||
* PRNSTS |
||||
* CMDINHDAT[1] : Command Inhibit (DAT) |
||||
* CMDINHCMD[0] : Command Inhibit (CMD) |
||||
*/ |
||||
mask = (1 << 0); |
||||
if ((data != NULL) || (cmd->resp_type & MMC_RSP_BUSY)) |
||||
mask |= (1 << 1); |
||||
|
||||
/*
|
||||
* We shouldn't wait for data inihibit for stop commands, even |
||||
* though they might use busy signaling |
||||
*/ |
||||
if (data) |
||||
mask &= ~(1 << 1); |
||||
|
||||
while (readl(&host->reg->prnsts) & mask) { |
||||
if (timeout == 0) { |
||||
printf("%s: timeout error\n", __func__); |
||||
return -1; |
||||
} |
||||
timeout--; |
||||
udelay(1000); |
||||
} |
||||
|
||||
if (data) |
||||
mmc_prepare_data(host, data); |
||||
|
||||
dbg("cmd->arg: %08x\n", cmd->cmdarg); |
||||
writel(cmd->cmdarg, &host->reg->argument); |
||||
|
||||
if (data) |
||||
mmc_set_transfer_mode(host, data); |
||||
|
||||
if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY)) |
||||
return -1; |
||||
|
||||
/*
|
||||
* CMDREG |
||||
* CMDIDX[13:8] : Command index |
||||
* DATAPRNT[5] : Data Present Select |
||||
* ENCMDIDX[4] : Command Index Check Enable |
||||
* ENCMDCRC[3] : Command CRC Check Enable |
||||
* RSPTYP[1:0] |
||||
* 00 = No Response |
||||
* 01 = Length 136 |
||||
* 10 = Length 48 |
||||
* 11 = Length 48 Check busy after response |
||||
*/ |
||||
if (!(cmd->resp_type & MMC_RSP_PRESENT)) |
||||
flags = 0; |
||||
else if (cmd->resp_type & MMC_RSP_136) |
||||
flags = (1 << 0); |
||||
else if (cmd->resp_type & MMC_RSP_BUSY) |
||||
flags = (3 << 0); |
||||
else |
||||
flags = (2 << 0); |
||||
|
||||
if (cmd->resp_type & MMC_RSP_CRC) |
||||
flags |= (1 << 3); |
||||
if (cmd->resp_type & MMC_RSP_OPCODE) |
||||
flags |= (1 << 4); |
||||
if (data) |
||||
flags |= (1 << 5); |
||||
|
||||
dbg("cmd: %d\n", cmd->cmdidx); |
||||
|
||||
writew((cmd->cmdidx << 8) | flags, &host->reg->cmdreg); |
||||
|
||||
for (i = 0; i < retry; i++) { |
||||
mask = readl(&host->reg->norintsts); |
||||
/* Command Complete */ |
||||
if (mask & (1 << 0)) { |
||||
if (!data) |
||||
writel(mask, &host->reg->norintsts); |
||||
break; |
||||
} |
||||
} |
||||
|
||||
if (i == retry) { |
||||
printf("%s: waiting for status update\n", __func__); |
||||
return TIMEOUT; |
||||
} |
||||
|
||||
if (mask & (1 << 16)) { |
||||
/* Timeout Error */ |
||||
dbg("timeout: %08x cmd %d\n", mask, cmd->cmdidx); |
||||
return TIMEOUT; |
||||
} else if (mask & (1 << 15)) { |
||||
/* Error Interrupt */ |
||||
dbg("error: %08x cmd %d\n", mask, cmd->cmdidx); |
||||
return -1; |
||||
} |
||||
|
||||
if (cmd->resp_type & MMC_RSP_PRESENT) { |
||||
if (cmd->resp_type & MMC_RSP_136) { |
||||
/* CRC is stripped so we need to do some shifting. */ |
||||
for (i = 0; i < 4; i++) { |
||||
unsigned int offset = |
||||
(unsigned int)(&host->reg->rspreg3 - i); |
||||
cmd->response[i] = readl(offset) << 8; |
||||
|
||||
if (i != 3) { |
||||
cmd->response[i] |= |
||||
readb(offset - 1); |
||||
} |
||||
dbg("cmd->resp[%d]: %08x\n", |
||||
i, cmd->response[i]); |
||||
} |
||||
} else if (cmd->resp_type & MMC_RSP_BUSY) { |
||||
for (i = 0; i < retry; i++) { |
||||
/* PRNTDATA[23:20] : DAT[3:0] Line Signal */ |
||||
if (readl(&host->reg->prnsts) |
||||
& (1 << 20)) /* DAT[0] */ |
||||
break; |
||||
} |
||||
|
||||
if (i == retry) { |
||||
printf("%s: card is still busy\n", __func__); |
||||
return TIMEOUT; |
||||
} |
||||
|
||||
cmd->response[0] = readl(&host->reg->rspreg0); |
||||
dbg("cmd->resp[0]: %08x\n", cmd->response[0]); |
||||
} else { |
||||
cmd->response[0] = readl(&host->reg->rspreg0); |
||||
dbg("cmd->resp[0]: %08x\n", cmd->response[0]); |
||||
} |
||||
} |
||||
|
||||
if (data) { |
||||
while (1) { |
||||
mask = readl(&host->reg->norintsts); |
||||
|
||||
if (mask & (1 << 15)) { |
||||
/* Error Interrupt */ |
||||
writel(mask, &host->reg->norintsts); |
||||
printf("%s: error during transfer: 0x%08x\n", |
||||
__func__, mask); |
||||
return -1; |
||||
} else if (mask & (1 << 3)) { |
||||
/* DMA Interrupt */ |
||||
dbg("DMA end\n"); |
||||
break; |
||||
} else if (mask & (1 << 1)) { |
||||
/* Transfer Complete */ |
||||
dbg("r/w is done\n"); |
||||
break; |
||||
} |
||||
} |
||||
writel(mask, &host->reg->norintsts); |
||||
} |
||||
|
||||
udelay(1000); |
||||
return 0; |
||||
} |
||||
|
||||
static void mmc_change_clock(struct mmc_host *host, uint clock) |
||||
{ |
||||
int div; |
||||
unsigned short clk; |
||||
unsigned long timeout; |
||||
unsigned long ctrl2; |
||||
|
||||
/*
|
||||
* SELBASECLK[5:4] |
||||
* 00/01 = HCLK |
||||
* 10 = EPLL |
||||
* 11 = XTI or XEXTCLK |
||||
*/ |
||||
ctrl2 = readl(&host->reg->control2); |
||||
ctrl2 &= ~(3 << 4); |
||||
ctrl2 |= (2 << 4); |
||||
writel(ctrl2, &host->reg->control2); |
||||
|
||||
writew(0, &host->reg->clkcon); |
||||
|
||||
/* XXX: we assume that clock is between 40MHz and 50MHz */ |
||||
if (clock == 0) |
||||
goto out; |
||||
else if (clock <= 400000) |
||||
div = 0x100; |
||||
else if (clock <= 20000000) |
||||
div = 4; |
||||
else if (clock <= 26000000) |
||||
div = 2; |
||||
else |
||||
div = 1; |
||||
dbg("div: %d\n", div); |
||||
|
||||
div >>= 1; |
||||
/*
|
||||
* CLKCON |
||||
* SELFREQ[15:8] : base clock divied by value |
||||
* ENSDCLK[2] : SD Clock Enable |
||||
* STBLINTCLK[1] : Internal Clock Stable |
||||
* ENINTCLK[0] : Internal Clock Enable |
||||
*/ |
||||
clk = (div << 8) | (1 << 0); |
||||
writew(clk, &host->reg->clkcon); |
||||
|
||||
/* Wait max 10 ms */ |
||||
timeout = 10; |
||||
while (!(readw(&host->reg->clkcon) & (1 << 1))) { |
||||
if (timeout == 0) { |
||||
printf("%s: timeout error\n", __func__); |
||||
return; |
||||
} |
||||
timeout--; |
||||
udelay(1000); |
||||
} |
||||
|
||||
clk |= (1 << 2); |
||||
writew(clk, &host->reg->clkcon); |
||||
|
||||
out: |
||||
host->clock = clock; |
||||
} |
||||
|
||||
static void mmc_set_ios(struct mmc *mmc) |
||||
{ |
||||
struct mmc_host *host = mmc->priv; |
||||
unsigned char ctrl; |
||||
unsigned long val; |
||||
|
||||
dbg("set_ios: bus_width: %x, clock: %d\n", mmc->bus_width, mmc->clock); |
||||
|
||||
/*
|
||||
* SELCLKPADDS[17:16] |
||||
* 00 = 2mA |
||||
* 01 = 4mA |
||||
* 10 = 7mA |
||||
* 11 = 9mA |
||||
*/ |
||||
writel(0x3 << 16, &host->reg->control4); |
||||
|
||||
val = readl(&host->reg->control2); |
||||
val &= (0x3 << 4); |
||||
|
||||
val |= (1 << 31) | /* write status clear async mode enable */ |
||||
(1 << 30) | /* command conflict mask enable */ |
||||
(1 << 14) | /* Feedback Clock Enable for Rx Clock */ |
||||
(1 << 8); /* SDCLK hold enable */ |
||||
|
||||
writel(val, &host->reg->control2); |
||||
|
||||
/*
|
||||
* FCSEL1[15] FCSEL0[7] |
||||
* FCSel[1:0] : Rx Feedback Clock Delay Control |
||||
* Inverter delay means10ns delay if SDCLK 50MHz setting |
||||
* 01 = Delay1 (basic delay) |
||||
* 11 = Delay2 (basic delay + 2ns) |
||||
* 00 = Delay3 (inverter delay) |
||||
* 10 = Delay4 (inverter delay + 2ns) |
||||
*/ |
||||
writel(0x8080, &host->reg->control3); |
||||
|
||||
mmc_change_clock(host, mmc->clock); |
||||
|
||||
ctrl = readb(&host->reg->hostctl); |
||||
|
||||
/*
|
||||
* WIDE4[1] |
||||
* 1 = 4-bit mode |
||||
* 0 = 1-bit mode |
||||
*/ |
||||
if (mmc->bus_width == 4) |
||||
ctrl |= (1 << 1); |
||||
else |
||||
ctrl &= ~(1 << 1); |
||||
|
||||
/*
|
||||
* OUTEDGEINV[2] |
||||
* 1 = Riging edge output |
||||
* 0 = Falling edge output |
||||
*/ |
||||
ctrl &= ~(1 << 2); |
||||
|
||||
writeb(ctrl, &host->reg->hostctl); |
||||
} |
||||
|
||||
static void mmc_reset(struct mmc_host *host) |
||||
{ |
||||
unsigned int timeout; |
||||
|
||||
/*
|
||||
* RSTALL[0] : Software reset for all |
||||
* 1 = reset |
||||
* 0 = work |
||||
*/ |
||||
writeb((1 << 0), &host->reg->swrst); |
||||
|
||||
host->clock = 0; |
||||
|
||||
/* Wait max 100 ms */ |
||||
timeout = 100; |
||||
|
||||
/* hw clears the bit when it's done */ |
||||
while (readb(&host->reg->swrst) & (1 << 0)) { |
||||
if (timeout == 0) { |
||||
printf("%s: timeout error\n", __func__); |
||||
return; |
||||
} |
||||
timeout--; |
||||
udelay(1000); |
||||
} |
||||
} |
||||
|
||||
static int mmc_core_init(struct mmc *mmc) |
||||
{ |
||||
struct mmc_host *host = (struct mmc_host *)mmc->priv; |
||||
unsigned int mask; |
||||
|
||||
mmc_reset(host); |
||||
|
||||
host->version = readw(&host->reg->hcver); |
||||
|
||||
/* mask all */ |
||||
writel(0xffffffff, &host->reg->norintstsen); |
||||
writel(0xffffffff, &host->reg->norintsigen); |
||||
|
||||
writeb(0xe, &host->reg->timeoutcon); /* TMCLK * 2^27 */ |
||||
|
||||
/*
|
||||
* NORMAL Interrupt Status Enable Register init |
||||
* [5] ENSTABUFRDRDY : Buffer Read Ready Status Enable |
||||
* [4] ENSTABUFWTRDY : Buffer write Ready Status Enable |
||||
* [1] ENSTASTANSCMPLT : Transfre Complete Status Enable |
||||
* [0] ENSTACMDCMPLT : Command Complete Status Enable |
||||
*/ |
||||
mask = readl(&host->reg->norintstsen); |
||||
mask &= ~(0xffff); |
||||
mask |= (1 << 5) | (1 << 4) | (1 << 1) | (1 << 0); |
||||
writel(mask, &host->reg->norintstsen); |
||||
|
||||
/*
|
||||
* NORMAL Interrupt Signal Enable Register init |
||||
* [1] ENSTACMDCMPLT : Transfer Complete Signal Enable |
||||
*/ |
||||
mask = readl(&host->reg->norintsigen); |
||||
mask &= ~(0xffff); |
||||
mask |= (1 << 1); |
||||
writel(mask, &host->reg->norintsigen); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int s5p_mmc_initialize(int dev_index) |
||||
{ |
||||
struct mmc *mmc; |
||||
|
||||
mmc = &mmc_dev[dev_index]; |
||||
|
||||
sprintf(mmc->name, "SAMSUNG SD/MMC"); |
||||
mmc->priv = &mmc_host[dev_index]; |
||||
mmc->send_cmd = mmc_send_cmd; |
||||
mmc->set_ios = mmc_set_ios; |
||||
mmc->init = mmc_core_init; |
||||
|
||||
mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; |
||||
mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS; |
||||
|
||||
mmc->f_min = 400000; |
||||
mmc->f_max = 52000000; |
||||
|
||||
mmc_host[dev_index].clock = 0; |
||||
mmc_host[dev_index].reg = s5p_get_base_mmc(dev_index); |
||||
mmc_register(mmc); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int s5p_mmc_init(int dev_index) |
||||
{ |
||||
return s5p_mmc_initialize(dev_index); |
||||
} |
@ -0,0 +1,78 @@ |
||||
/*
|
||||
* (C) Copyright 2010 |
||||
* Texas Instruments, <www.ti.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
#include <config.h> |
||||
#ifdef CONFIG_TWL6030_POWER |
||||
|
||||
#include <twl6030.h> |
||||
|
||||
/* Functions to read and write from TWL6030 */ |
||||
static inline int twl6030_i2c_write_u8(u8 chip_no, u8 val, u8 reg) |
||||
{ |
||||
return i2c_write(chip_no, reg, 1, &val, 1); |
||||
} |
||||
|
||||
static inline int twl6030_i2c_read_u8(u8 chip_no, u8 *val, u8 reg) |
||||
{ |
||||
return i2c_read(chip_no, reg, 1, val, 1); |
||||
} |
||||
|
||||
void twl6030_start_usb_charging(void) |
||||
{ |
||||
twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, CHARGERUSB_VICHRG_1500, |
||||
CHARGERUSB_VICHRG); |
||||
twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, CHARGERUSB_CIN_LIMIT_NONE, |
||||
CHARGERUSB_CINLIMIT); |
||||
twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, MBAT_TEMP, |
||||
CONTROLLER_INT_MASK); |
||||
twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, MASK_MCHARGERUSB_THMREG, |
||||
CHARGERUSB_INT_MASK); |
||||
twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, CHARGERUSB_VOREG_4P0, |
||||
CHARGERUSB_VOREG); |
||||
twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, CHARGERUSB_CTRL2_VITERM_100, |
||||
CHARGERUSB_CTRL2); |
||||
/* Enable USB charging */ |
||||
twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, CONTROLLER_CTRL1_EN_CHARGER, |
||||
CONTROLLER_CTRL1); |
||||
return; |
||||
} |
||||
|
||||
void twl6030_init_battery_charging(void) |
||||
{ |
||||
twl6030_start_usb_charging(); |
||||
return; |
||||
} |
||||
|
||||
void twl6030_usb_device_settings() |
||||
{ |
||||
u8 data = 0; |
||||
|
||||
/* Select APP Group and set state to ON */ |
||||
twl6030_i2c_write_u8(TWL6030_CHIP_PM, 0x21, VUSB_CFG_STATE); |
||||
|
||||
twl6030_i2c_read_u8(TWL6030_CHIP_PM, &data, MISC2); |
||||
data |= 0x10; |
||||
|
||||
/* Select the input supply for VBUS regulator */ |
||||
twl6030_i2c_write_u8(TWL6030_CHIP_PM, data, MISC2); |
||||
} |
||||
#endif |
@ -0,0 +1,91 @@ |
||||
/*
|
||||
* (C) Copyright 2010 |
||||
* Texas Instruments, <www.ti.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <i2c.h> |
||||
|
||||
/* I2C chip addresses */ |
||||
#define TWL6030_CHIP_PM 0x48 |
||||
|
||||
#define TWL6030_CHIP_USB 0x49 |
||||
#define TWL6030_CHIP_ADC 0x49 |
||||
#define TWL6030_CHIP_CHARGER 0x49 |
||||
#define TWL6030_CHIP_PWM 0x49 |
||||
|
||||
/* Battery CHARGER REGISTERS */ |
||||
#define CONTROLLER_INT_MASK 0xE0 |
||||
#define CONTROLLER_CTRL1 0xE1 |
||||
#define CONTROLLER_WDG 0xE2 |
||||
#define CONTROLLER_STAT1 0xE3 |
||||
#define CHARGERUSB_INT_STATUS 0xE4 |
||||
#define CHARGERUSB_INT_MASK 0xE5 |
||||
#define CHARGERUSB_STATUS_INT1 0xE6 |
||||
#define CHARGERUSB_STATUS_INT2 0xE7 |
||||
#define CHARGERUSB_CTRL1 0xE8 |
||||
#define CHARGERUSB_CTRL2 0xE9 |
||||
#define CHARGERUSB_CTRL3 0xEA |
||||
#define CHARGERUSB_STAT1 0xEB |
||||
#define CHARGERUSB_VOREG 0xEC |
||||
#define CHARGERUSB_VICHRG 0xED |
||||
#define CHARGERUSB_CINLIMIT 0xEE |
||||
#define CHARGERUSB_CTRLLIMIT1 0xEF |
||||
|
||||
/* CHARGERUSB_VICHRG */ |
||||
#define CHARGERUSB_VICHRG_500 0x4 |
||||
#define CHARGERUSB_VICHRG_1500 0xE |
||||
/* CHARGERUSB_CINLIMIT */ |
||||
#define CHARGERUSB_CIN_LIMIT_100 0x1 |
||||
#define CHARGERUSB_CIN_LIMIT_300 0x5 |
||||
#define CHARGERUSB_CIN_LIMIT_500 0x9 |
||||
#define CHARGERUSB_CIN_LIMIT_NONE 0xF |
||||
/* CONTROLLER_INT_MASK */ |
||||
#define MVAC_FAULT (1 << 6) |
||||
#define MAC_EOC (1 << 5) |
||||
#define MBAT_REMOVED (1 << 4) |
||||
#define MFAULT_WDG (1 << 3) |
||||
#define MBAT_TEMP (1 << 2) |
||||
#define MVBUS_DET (1 << 1) |
||||
#define MVAC_DET (1 << 0) |
||||
/* CHARGERUSB_INT_MASK */ |
||||
#define MASK_MCURRENT_TERM (1 << 3) |
||||
#define MASK_MCHARGERUSB_STAT (1 << 2) |
||||
#define MASK_MCHARGERUSB_THMREG (1 << 1) |
||||
#define MASK_MCHARGERUSB_FAULT (1 << 0) |
||||
/* CHARGERUSB_VOREG */ |
||||
#define CHARGERUSB_VOREG_3P52 0x01 |
||||
#define CHARGERUSB_VOREG_4P0 0x19 |
||||
#define CHARGERUSB_VOREG_4P2 0x23 |
||||
#define CHARGERUSB_VOREG_4P76 0x3F |
||||
/* CHARGERUSB_CTRL2 */ |
||||
#define CHARGERUSB_CTRL2_VITERM_50 (0 << 5) |
||||
#define CHARGERUSB_CTRL2_VITERM_100 (1 << 5) |
||||
#define CHARGERUSB_CTRL2_VITERM_150 (2 << 5) |
||||
/* CONTROLLER_CTRL1 */ |
||||
#define CONTROLLER_CTRL1_EN_CHARGER (1 << 4) |
||||
#define CONTROLLER_CTRL1_SEL_CHARGER (1 << 3) |
||||
|
||||
#define VUSB_CFG_STATE 0xA2 |
||||
#define MISC2 0xE5 |
||||
|
||||
void twl6030_init_battery_charging(void); |
||||
void twl6030_usb_device_settings(void); |
Loading…
Reference in new issue