parent
2eab48f511
commit
ba91e26a19
@ -0,0 +1,46 @@ |
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#
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# (C) Copyright 2001
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
|
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
|
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = lib$(BOARD).a
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OBJS := $(BOARD).o flash.o m88e6060.o
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$(LIB): $(OBJS) $(SOBJS) |
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$(AR) crv $@ $(OBJS)
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clean: |
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rm -f $(SOBJS) $(OBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) |
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$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
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-include .depend |
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#########################################################################
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@ -0,0 +1,21 @@ |
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# (C) Copyright 2004
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# Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de)
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#
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# Support for the Elmeg VoVPN Gateway Module
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
|
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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TEXT_BASE = 0xfff00000
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@ -0,0 +1,506 @@ |
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/*
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* (C) Copyright 2004 |
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* Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de) |
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* |
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* Support for the Elmeg VoVPN Gateway Module |
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* ------------------------------------------ |
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* This is a signle bank flashdriver for INTEL 28F320J3, 28F640J3 |
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* and 28F128J3A flashs working in 8 Bit mode.
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* |
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* Most of this code is taken from existing u-boot source code. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; |
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#define FLASH_CMD_READ_ID 0x90 |
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#define FLASH_CMD_READ_STATUS 0x70 |
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#define FLASH_CMD_RESET 0xff |
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#define FLASH_CMD_BLOCK_ERASE 0x20 |
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#define FLASH_CMD_ERASE_CONFIRM 0xd0 |
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#define FLASH_CMD_CLEAR_STATUS 0x50 |
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#define FLASH_CMD_SUSPEND_ERASE 0xb0 |
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#define FLASH_CMD_WRITE 0x40 |
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#define FLASH_CMD_WRITE_BUFF 0xe8 |
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#define FLASH_CMD_PROG_RESUME 0xd0 |
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#define FLASH_CMD_PROTECT 0x60 |
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#define FLASH_CMD_PROTECT_SET 0x01 |
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#define FLASH_CMD_PROTECT_CLEAR 0xd0 |
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#define FLASH_STATUS_DONE 0x80 |
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#define FLASH_WRITE_BUFFER_SIZE 32 |
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#ifdef CFG_FLASH_16BIT |
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#define FLASH_WORD_SIZE unsigned short |
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#define FLASH_ID_MASK 0xffff |
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#define FLASH_CMD_ADDR_SHIFT 0 |
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#else |
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#define FLASH_WORD_SIZE unsigned char |
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#define FLASH_ID_MASK 0xff |
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/* A0 is not used in either 8x or 16x for READ ID */ |
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#define FLASH_CMD_ADDR_SHIFT 1 |
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#endif |
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static unsigned long |
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flash_get(volatile FLASH_WORD_SIZE *addr, flash_info_t *info) |
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{ |
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volatile FLASH_WORD_SIZE *p; |
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FLASH_WORD_SIZE value; |
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int i; |
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addr[0] = FLASH_CMD_READ_ID; |
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/* manufactor */ |
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value = addr[0 << FLASH_CMD_ADDR_SHIFT]; |
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switch (value) { |
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case (INTEL_MANUFACT & FLASH_ID_MASK): |
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info->flash_id = FLASH_MAN_INTEL; |
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break; |
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default: |
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info->flash_id = FLASH_UNKNOWN; |
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info->sector_count = 0; |
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info->size = 0; |
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*addr = FLASH_CMD_RESET; |
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return (0); |
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} |
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/* device */ |
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value = addr[1 << FLASH_CMD_ADDR_SHIFT]; |
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switch (value) { |
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case (INTEL_ID_28F320J3A & FLASH_ID_MASK): |
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info->flash_id += FLASH_28F320J3A; |
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info->sector_count = 32; |
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info->size = 0x00400000; |
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break; |
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case (INTEL_ID_28F640J3A & FLASH_ID_MASK): |
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info->flash_id += FLASH_28F640J3A; |
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info->sector_count = 64; |
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info->size = 0x00800000; |
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break; |
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case (INTEL_ID_28F128J3A & FLASH_ID_MASK): |
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info->flash_id += FLASH_28F128J3A; |
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info->sector_count = 128; |
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info->size = 0x01000000; |
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break; |
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default: |
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info->flash_id = FLASH_UNKNOWN; |
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info->sector_count = 0; |
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info->size = 0; |
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*addr = FLASH_CMD_RESET; |
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return (0); |
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} |
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/* setup sectors */ |
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for (i = 0; i < info->sector_count; i++) { |
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info->start[i] = (unsigned long)addr + (i * info->size/info->sector_count); |
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} |
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/* check protected sectors */ |
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for (i = 0; i < info->sector_count; i++) { |
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p = (volatile FLASH_WORD_SIZE *)(info->start[i]); |
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info->protect[i] = p[2 << FLASH_CMD_ADDR_SHIFT] & 1; |
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} |
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/* reset bank */ |
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*addr = FLASH_CMD_RESET; |
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return (info->size); |
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} |
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unsigned long |
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flash_init(void) |
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{ |
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unsigned long size; |
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int i; |
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for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { |
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flash_info[i].flash_id = FLASH_UNKNOWN; |
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} |
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size = flash_get((volatile FLASH_WORD_SIZE *)CFG_FLASH_BASE, &flash_info[0]); |
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if (flash_info[0].flash_id == FLASH_UNKNOWN) { |
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printf ("## Unknown FLASH Size=0x%08lx\n", size); |
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return (0); |
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} |
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/* always protect 1 sector containing the HRCW */ |
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flash_protect(FLAG_PROTECT_SET, |
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flash_info[0].start[0], |
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flash_info[0].start[1] - 1, |
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&flash_info[0]); |
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#if CFG_MONITOR_BASE >= CFG_FLASH_BASE |
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flash_protect(FLAG_PROTECT_SET, |
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CFG_MONITOR_FLASH, |
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CFG_MONITOR_FLASH+CFG_MONITOR_LEN-1, |
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&flash_info[0]); |
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#endif |
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#ifdef CFG_ENV_IS_IN_FLASH |
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flash_protect(FLAG_PROTECT_SET, |
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CFG_ENV_ADDR, |
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CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, |
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&flash_info[0]); |
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#endif |
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return (size); |
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} |
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void |
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flash_print_info(flash_info_t *info) |
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{ |
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int i; |
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if (info->flash_id == FLASH_UNKNOWN) { |
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printf ("missing or unknown FLASH type\n"); |
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return; |
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} |
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switch (info->flash_id & FLASH_VENDMASK) { |
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case FLASH_MAN_INTEL: printf ("INTEL "); break; |
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default: printf ("Unknown Vendor "); break; |
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} |
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switch (info->flash_id & FLASH_TYPEMASK) { |
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case FLASH_28F320J3A: printf ("28F320JA3 (32 Mbit)\n"); |
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break; |
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case FLASH_28F640J3A: printf ("28F640JA3 (64 Mbit)\n"); |
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break; |
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case FLASH_28F128J3A: printf ("28F128JA3 (128 Mbit)\n"); |
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break; |
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default: printf ("Unknown Chip Type"); |
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break; |
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} |
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printf (" Size: %ld MB in %d Sectors\n", |
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info->size >> 20, info->sector_count); |
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printf (" Sector Start Addresses:"); |
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for (i=0; i<info->sector_count; ++i) { |
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if ((i % 5) == 0) |
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printf ("\n "); |
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printf (" %08lX%s", |
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info->start[i], |
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info->protect[i] ? " (RO)" : " " |
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); |
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} |
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printf ("\n"); |
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} |
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int |
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flash_erase(flash_info_t *info, int s_first, int s_last) |
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{ |
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unsigned long start, now, last; |
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int flag, prot, sect; |
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volatile FLASH_WORD_SIZE *addr; |
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FLASH_WORD_SIZE status; |
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if ((s_first < 0) || (s_first > s_last)) { |
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if (info->flash_id == FLASH_UNKNOWN) { |
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printf ("- missing\n"); |
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} else { |
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printf ("- no sectors to erase\n"); |
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} |
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return (1); |
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} |
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if (info->flash_id == FLASH_UNKNOWN) { |
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printf ("Cannot erase unknown flash - aborted\n"); |
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return (1); |
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} |
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prot = 0; |
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for (sect=s_first; sect<=s_last; ++sect) { |
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if (info->protect[sect]) { |
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prot++; |
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} |
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} |
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if (prot) { |
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printf ("- Warning: %d protected sectors will not be erased!\n", prot); |
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} else { |
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printf ("\n"); |
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} |
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start = get_timer (0); |
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last = start; |
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for (sect = s_first; sect<=s_last; sect++) { |
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if (info->protect[sect]) { |
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continue; |
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} |
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addr = (volatile FLASH_WORD_SIZE *)(info->start[sect]); |
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/* Disable interrupts which might cause a timeout here */ |
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flag = disable_interrupts(); |
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#ifdef DEBUG |
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printf("Erase sector %d at start addr 0x%08X", sect, (unsigned int)info->start[sect]); |
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#endif |
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*addr = FLASH_CMD_CLEAR_STATUS; |
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*addr = FLASH_CMD_BLOCK_ERASE; |
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*addr = FLASH_CMD_ERASE_CONFIRM; |
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/* re-enable interrupts if necessary */ |
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if (flag) { |
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enable_interrupts(); |
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} |
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/* wait at least 80us - let's wait 1 ms */ |
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udelay (1000); |
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while (((status = *addr) & FLASH_STATUS_DONE) != FLASH_STATUS_DONE) { |
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if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { |
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printf("Flash erase timeout at address %lx\n", info->start[sect]); |
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*addr = FLASH_CMD_SUSPEND_ERASE; |
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*addr = FLASH_CMD_RESET; |
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return (1); |
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} |
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/* show that we're waiting */ |
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if ((now - last) > 1000) { /* every second */ |
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putc ('.'); |
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last = now; |
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} |
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} |
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*addr = FLASH_CMD_RESET; |
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} |
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printf (" done\n"); |
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return (0); |
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} |
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static int |
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write_buff2( volatile FLASH_WORD_SIZE *dst, |
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volatile FLASH_WORD_SIZE *src, |
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unsigned long cnt ) |
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{ |
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unsigned long start; |
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FLASH_WORD_SIZE status; |
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int flag, i; |
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start = get_timer (0); |
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while (1) { |
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/* Disable interrupts which might cause a timeout here */ |
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flag = disable_interrupts(); |
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dst[0] = FLASH_CMD_WRITE_BUFF; |
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if ((status = *dst) & FLASH_STATUS_DONE) { |
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break; |
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} |
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/* re-enable interrupts if necessary */ |
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if (flag) { |
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enable_interrupts(); |
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} |
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if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { |
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return (-1); |
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} |
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} |
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dst[0] = (FLASH_WORD_SIZE)(cnt - 1); |
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for (i=0; i<cnt; i++) { |
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dst[i] = src[i]; |
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} |
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dst[0] = FLASH_CMD_PROG_RESUME; |
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if (flag) { |
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enable_interrupts(); |
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} |
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return( 0 ); |
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} |
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static int |
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poll_status( volatile FLASH_WORD_SIZE *addr ) |
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{ |
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unsigned long start; |
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start = get_timer (0); |
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/* wait for error or finish */ |
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while (1) { |
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if (*addr == FLASH_STATUS_DONE) { |
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if (*addr == FLASH_STATUS_DONE) { |
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break; |
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} |
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} |
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if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { |
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*addr = FLASH_CMD_RESET; |
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return (-1); |
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} |
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} |
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*addr = FLASH_CMD_RESET; |
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return (0); |
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} |
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|
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/*
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* write_buff return values: |
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* 0 - OK |
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* 1 - write timeout |
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* 2 - Flash not erased |
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* 4 - Flash not identified |
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*/ |
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int |
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write_buff(flash_info_t *info, uchar *src, ulong udst, ulong cnt) |
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{ |
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volatile FLASH_WORD_SIZE *addr, *dst; |
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unsigned long bcnt; |
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int flag, i; |
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|
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if (info->flash_id == FLASH_UNKNOWN) { |
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return (4); |
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} |
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|
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addr = (volatile FLASH_WORD_SIZE *)(info->start[0]); |
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dst = (volatile FLASH_WORD_SIZE *) udst; |
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|
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#ifdef CFG_FLASH_16BIT |
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#error NYI |
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#else |
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while (cnt > 0) { |
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/* Check if buffer write is possible */ |
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if (cnt > 1 && (((unsigned long)dst & (FLASH_WRITE_BUFFER_SIZE - 1)) == 0)) { |
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bcnt = cnt > FLASH_WRITE_BUFFER_SIZE ? FLASH_WRITE_BUFFER_SIZE : cnt; |
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/* Check if Flash is (sufficiently) erased */ |
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for (i=0; i<bcnt; i++) { |
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if ((dst[i] & src[i]) != src[i]) { |
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return (2); |
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} |
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} |
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if (write_buff2( dst,src,bcnt ) != 0) { |
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addr[0] = FLASH_CMD_READ_STATUS; |
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} |
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if (poll_status( dst ) != 0) { |
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return (1); |
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} |
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cnt -= bcnt; |
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dst += bcnt; |
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src += bcnt; |
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continue; |
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} |
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|
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/* Check if Flash is (sufficiently) erased */ |
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if ((*dst & *src) != *src) { |
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return (2); |
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} |
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|
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/* Disable interrupts which might cause a timeout here */ |
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flag = disable_interrupts(); |
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addr[0] = FLASH_CMD_ERASE_CONFIRM; |
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addr[0] = FLASH_CMD_WRITE; |
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*dst++ = *src++; |
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/* re-enable interrupts if necessary */ |
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if (flag) { |
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enable_interrupts(); |
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} |
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|
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if (poll_status( dst ) != 0) { |
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return (1); |
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} |
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cnt --; |
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} |
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#endif |
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return (0); |
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} |
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|
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int |
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flash_real_protect(flash_info_t *info, long sector, int prot) |
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{ |
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volatile FLASH_WORD_SIZE *addr; |
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unsigned long start; |
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|
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addr = (volatile FLASH_WORD_SIZE *)(info->start[sector]); |
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*addr = FLASH_CMD_CLEAR_STATUS; |
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*addr = FLASH_CMD_PROTECT; |
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|
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if(prot) { |
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*addr = FLASH_CMD_PROTECT_SET; |
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} else { |
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*addr = FLASH_CMD_PROTECT_CLEAR; |
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} |
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|
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/* wait for error or finish */ |
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start = get_timer (0); |
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while(!(addr[0] & FLASH_STATUS_DONE)){ |
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if (get_timer(start) > CFG_FLASH_ERASE_TOUT) { |
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printf("Flash protect timeout at address %lx\n", info->start[sector]); |
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addr[0] = FLASH_CMD_RESET; |
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return (1); |
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} |
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} |
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|
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/* Set software protect flag */ |
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info->protect[sector] = prot; |
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*addr = FLASH_CMD_RESET; |
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return (0); |
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} |
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|
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/*-----------------------------------------------------------------------
|
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* Support for flash file system (JFFS2) |
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* |
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* We use custom partition info function because we have to fit the |
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* file system image between first sector (containing hard reset |
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* configuration word) and the sector containing U-Boot image. Standard |
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* partition info function does not allow for last sector specification |
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* and assumes that the file system occupies flash bank up to and |
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* including bank's last sector. |
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*/ |
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#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CFG_JFFS_CUSTOM_PART) |
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#error TODO |
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|
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#ifndef CFG_JFFS2_FIRST_SECTOR |
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#define CFG_JFFS2_FIRST_SECTOR 0 |
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#endif |
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#ifndef CFG_JFFS2_FIRST_BANK |
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#define CFG_JFFS2_FIRST_BANK 0 |
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#endif |
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#ifndef CFG_JFFS2_NUM_BANKS |
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#define CFG_JFFS2_NUM_BANKS 1 |
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#endif |
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#define CFG_JFFS2_LAST_BANK (CFG_JFFS2_FIRST_BANK + CFG_JFFS2_NUM_BANKS - 1) |
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|
||||
#include <jffs2/jffs2.h> |
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|
||||
static struct part_info partition; |
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|
||||
struct part_info *jffs2_part_info(int part_num) |
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{ |
||||
int i; |
||||
|
||||
if (part_num == 0) { |
||||
if (partition.usr_priv == 0) { |
||||
partition.offset = |
||||
(unsigned char *) flash_info[CFG_JFFS2_FIRST_BANK].start[CFG_JFFS2_FIRST_SECTOR]; |
||||
for (i = CFG_JFFS2_FIRST_BANK; i <= CFG_JFFS2_LAST_BANK; i++) |
||||
partition.size += flash_info[i].size; |
||||
partition.size -= |
||||
flash_info[CFG_JFFS2_FIRST_BANK].start[CFG_JFFS2_FIRST_SECTOR] - |
||||
flash_info[CFG_JFFS2_FIRST_BANK].start[0]; |
||||
#ifdef CFG_JFFS2_LAST_SECTOR |
||||
i = flash_info[CFG_JFFS2_LAST_BANK].sector_count - 1; |
||||
partition.size -= |
||||
flash_info[CFG_JFFS2_LAST_BANK].start[i] - |
||||
flash_info[CFG_JFFS2_LAST_BANK].start[CFG_JFFS2_LAST_SECTOR]; |
||||
#endif |
||||
|
||||
partition.usr_priv = (void *)1; |
||||
} |
||||
return &partition; |
||||
} |
||||
return 0; |
||||
} |
||||
|
||||
#endif /* JFFS2 */ |
@ -0,0 +1,262 @@ |
||||
/*
|
||||
* (C) Copyright 2004 |
||||
* Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de) |
||||
* |
||||
* Support for the Elmeg VoVPN Gateway Module |
||||
* ------------------------------------------ |
||||
* Initialize Marvell M88E6060 Switch |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <ioports.h> |
||||
#include <mpc8260.h> |
||||
#include <asm/m8260_pci.h> |
||||
#include <net.h> |
||||
#include <miiphy.h> |
||||
|
||||
#include "m88e6060.h" |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_NET) |
||||
static int prtTab[M88X_PRT_CNT] = { 8, 9, 10, 11, 12, 13 }; |
||||
static int phyTab[M88X_PHY_CNT] = { 0, 1, 2, 3, 4 }; |
||||
|
||||
static m88x_regCfg_t prtCfg0[] = { |
||||
{ 4, 0x3e7c, 0x8000 }, |
||||
{ 4, 0x3e7c, 0x8003 }, |
||||
{ 6, 0x0fc0, 0x001e }, |
||||
{ -1, 0xffff, 0x0000 } |
||||
}; |
||||
|
||||
static m88x_regCfg_t prtCfg1[] = { |
||||
{ 4, 0x3e7c, 0x8000 }, |
||||
{ 4, 0x3e7c, 0x8003 }, |
||||
{ 6, 0x0fc0, 0x001d }, |
||||
{ -1, 0xffff, 0x0000 } |
||||
}; |
||||
|
||||
static m88x_regCfg_t prtCfg2[] = { |
||||
{ 4, 0x3e7c, 0x8000 }, |
||||
{ 4, 0x3e7c, 0x8003 }, |
||||
{ 6, 0x0fc0, 0x001b }, |
||||
{ -1, 0xffff, 0x0000 } |
||||
}; |
||||
|
||||
static m88x_regCfg_t prtCfg3[] = { |
||||
{ 4, 0x3e7c, 0x8000 }, |
||||
{ 4, 0x3e7c, 0x8003 }, |
||||
{ 6, 0x0fc0, 0x0017 }, |
||||
{ -1, 0xffff, 0x0000 } |
||||
}; |
||||
|
||||
static m88x_regCfg_t prtCfg4[] = { |
||||
{ 4, 0x3e7c, 0x8000 }, |
||||
{ 4, 0x3e7c, 0x8003 }, |
||||
{ 6, 0x0fc0, 0x000f }, |
||||
{ -1, 0xffff, 0x0000 } |
||||
}; |
||||
|
||||
static m88x_regCfg_t *prtCfg[M88X_PRT_CNT] = { |
||||
prtCfg0,prtCfg1,prtCfg2,prtCfg3,prtCfg4,NULL |
||||
}; |
||||
|
||||
static m88x_regCfg_t phyCfgX[] = { |
||||
{ 4, 0xfa1f, 0x01e0 }, |
||||
{ 0, 0x213f, 0x1200 }, |
||||
{ 24, 0x81ff, 0x1200 }, |
||||
{ -1, 0xffff, 0x0000 } |
||||
}; |
||||
|
||||
static m88x_regCfg_t *phyCfg[M88X_PHY_CNT] = { |
||||
phyCfgX,phyCfgX,phyCfgX,phyCfgX,NULL |
||||
}; |
||||
|
||||
#if 0 |
||||
static void |
||||
m88e6060_dump( int devAddr ) |
||||
{ |
||||
int i, j; |
||||
unsigned short val[6]; |
||||
|
||||
printf( "M88E6060 Register Dump\n" ); |
||||
printf( "====================================\n" ); |
||||
printf( "PortNo 0 1 2 3 4 5\n" ); |
||||
for (i=0; i<6; i++) |
||||
miiphy_read( devAddr+prtTab[i],M88X_PRT_STAT,&val[i] ); |
||||
printf( "STAT %04hx %04hx %04hx %04hx %04hx %04hx\n", |
||||
val[0],val[1],val[2],val[3],val[4],val[5] ); |
||||
|
||||
for (i=0; i<6; i++) |
||||
miiphy_read( devAddr+prtTab[i],M88X_PRT_ID,&val[i] ); |
||||
printf( "ID %04hx %04hx %04hx %04hx %04hx %04hx\n", |
||||
val[0],val[1],val[2],val[3],val[4],val[5] ); |
||||
|
||||
for (i=0; i<6; i++) |
||||
miiphy_read( devAddr+prtTab[i],M88X_PRT_CNTL,&val[i] ); |
||||
printf( "CNTL %04hx %04hx %04hx %04hx %04hx %04hx\n", |
||||
val[0],val[1],val[2],val[3],val[4],val[5] ); |
||||
|
||||
for (i=0; i<6; i++) |
||||
miiphy_read( devAddr+prtTab[i],M88X_PRT_VLAN,&val[i] ); |
||||
printf( "VLAN %04hx %04hx %04hx %04hx %04hx %04hx\n", |
||||
val[0],val[1],val[2],val[3],val[4],val[5] ); |
||||
|
||||
for (i=0; i<6; i++) |
||||
miiphy_read( devAddr+prtTab[i],M88X_PRT_PAV,&val[i] ); |
||||
printf( "PAV %04hx %04hx %04hx %04hx %04hx %04hx\n", |
||||
val[0],val[1],val[2],val[3],val[4],val[5] ); |
||||
|
||||
for (i=0; i<6; i++) |
||||
miiphy_read( devAddr+prtTab[i],M88X_PRT_RX,&val[i] ); |
||||
printf( "RX %04hx %04hx %04hx %04hx %04hx %04hx\n", |
||||
val[0],val[1],val[2],val[3],val[4],val[5] ); |
||||
|
||||
for (i=0; i<6; i++) |
||||
miiphy_read( devAddr+prtTab[i],M88X_PRT_TX,&val[i] ); |
||||
printf( "TX %04hx %04hx %04hx %04hx %04hx %04hx\n", |
||||
val[0],val[1],val[2],val[3],val[4],val[5] ); |
||||
|
||||
printf( "------------------------------------\n" ); |
||||
printf( "PhyNo 0 1 2 3 4\n" ); |
||||
for (i=0; i<9; i++) { |
||||
for (j=0; j<5; j++) { |
||||
miiphy_read( devAddr+phyTab[j],i,&val[j] ); |
||||
} |
||||
printf( "0x%02x %04hx %04hx %04hx %04hx %04hx\n", |
||||
i,val[0],val[1],val[2],val[3],val[4] ); |
||||
} |
||||
for (i=0x10; i<0x1d; i++) { |
||||
for (j=0; j<5; j++) { |
||||
miiphy_read( devAddr+phyTab[j],i,&val[j] ); |
||||
} |
||||
printf( "0x%02x %04hx %04hx %04hx %04hx %04hx\n", |
||||
i,val[0],val[1],val[2],val[3],val[4] ); |
||||
} |
||||
} |
||||
#endif |
||||
|
||||
int |
||||
m88e6060_initialize( int devAddr ) |
||||
{ |
||||
static char *_f = "m88e6060_initialize:"; |
||||
m88x_regCfg_t *p; |
||||
int err; |
||||
int i; |
||||
unsigned short val; |
||||
|
||||
/*** reset all phys into powerdown ************************************/ |
||||
for (i=0, err=0; i<M88X_PHY_CNT; i++) { |
||||
err += miiphy_read( devAddr+phyTab[i],M88X_PHY_CNTL,&val ); |
||||
/* keep SpeedLSB, Duplex */ |
||||
val &= 0x2100; |
||||
/* set SWReset, AnegEn, PwrDwn, RestartAneg */ |
||||
val |= 0x9a00; |
||||
err += miiphy_write( devAddr+phyTab[i],M88X_PHY_CNTL,val ); |
||||
} |
||||
if (err) { |
||||
printf( "%s [ERR] reset phys\n",_f ); |
||||
return( -1 ); |
||||
} |
||||
|
||||
/*** disable all ports ************************************************/ |
||||
for (i=0, err=0; i<M88X_PRT_CNT; i++) { |
||||
err += miiphy_read( devAddr+prtTab[i],M88X_PRT_CNTL,&val ); |
||||
val &= 0xfffc; |
||||
err += miiphy_write( devAddr+prtTab[i],M88X_PRT_CNTL,val ); |
||||
} |
||||
if (err) { |
||||
printf( "%s [ERR] disable ports\n",_f ); |
||||
return( -1 ); |
||||
} |
||||
|
||||
/*** initialize switch ************************************************/ |
||||
/* set switch mac addr */ |
||||
#define ea eth_get_dev()->enetaddr |
||||
val = (ea[4] << 8) | ea[5]; |
||||
err = miiphy_write( devAddr+15,M88X_GLB_MAC45,val ); |
||||
val = (ea[2] << 8) | ea[3]; |
||||
err += miiphy_write( devAddr+15,M88X_GLB_MAC23,val ); |
||||
val = (ea[0] << 8) | ea[1]; |
||||
#undef ea |
||||
val &= 0xfeff; /* clear DiffAddr */ |
||||
err += miiphy_write( devAddr+15,M88X_GLB_MAC01,val ); |
||||
if (err) { |
||||
printf( "%s [ERR] switch mac address register\n",_f ); |
||||
return( -1 ); |
||||
} |
||||
|
||||
/* !DiscardExcessive, MaxFrameSize, CtrMode */ |
||||
err = miiphy_read( devAddr+15,M88X_GLB_CNTL,&val ); |
||||
val &= 0xd870; |
||||
val |= 0x0500; |
||||
err += miiphy_write( devAddr+15,M88X_GLB_CNTL,val ); |
||||
if (err) { |
||||
printf( "%s [ERR] switch global control register\n",_f ); |
||||
return( -1 ); |
||||
} |
||||
|
||||
/* LernDis off, ATUSize 1024, AgeTime 5min */ |
||||
err = miiphy_read( devAddr+15,M88X_ATU_CNTL,&val ); |
||||
val &= 0x000f; |
||||
val |= 0x2130; |
||||
err += miiphy_write( devAddr+15,M88X_ATU_CNTL,val ); |
||||
if (err) { |
||||
printf( "%s [ERR] atu control register\n",_f ); |
||||
return( -1 ); |
||||
} |
||||
|
||||
/*** initialize ports *************************************************/ |
||||
for (i=0; i<M88X_PRT_CNT; i++) { |
||||
if ((p = prtCfg[i]) == NULL) { |
||||
continue; |
||||
} |
||||
while (p->reg != -1) { |
||||
err = 0; |
||||
err += miiphy_read( devAddr+prtTab[i],p->reg,&val ); |
||||
val &= p->msk; |
||||
val |= p->val; |
||||
err += miiphy_write( devAddr+prtTab[i],p->reg,val ); |
||||
if (err) { |
||||
printf( "%s [ERR] config port %d register %d\n",_f,i,p->reg ); |
||||
/* XXX what todo */ |
||||
} |
||||
p++; |
||||
} |
||||
} |
||||
|
||||
/*** initialize phys **************************************************/ |
||||
for (i=0; i<M88X_PHY_CNT; i++) { |
||||
if ((p = phyCfg[i]) == NULL) { |
||||
continue; |
||||
} |
||||
while (p->reg != -1) { |
||||
err = 0; |
||||
err += miiphy_read( devAddr+phyTab[i],p->reg,&val ); |
||||
val &= p->msk; |
||||
val |= p->val; |
||||
err += miiphy_write( devAddr+phyTab[i],p->reg,val ); |
||||
if (err) { |
||||
printf( "%s [ERR] config phy %d register %d\n",_f,i,p->reg ); |
||||
/* XXX what todo */ |
||||
} |
||||
p++; |
||||
} |
||||
} |
||||
udelay(100000); |
||||
return( 0 ); |
||||
} |
||||
#endif |
@ -0,0 +1,94 @@ |
||||
/*
|
||||
* (C) Copyright 2004 |
||||
* Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de) |
||||
* |
||||
* Support for the Elmeg VoVPN Gateway Module |
||||
* ------------------------------------------ |
||||
* Initialize Marvell M88E6060 Switch |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef _INC_m88e6060_h_ |
||||
#define _INC_m88e6060_h_ |
||||
|
||||
/* ************************************************************************** */ |
||||
/* *** DEFINES ************************************************************** */ |
||||
|
||||
/* switch hw */ |
||||
#define M88X_PRT_CNT 6 |
||||
#define M88X_PHY_CNT 5 |
||||
|
||||
/* phy register offsets */ |
||||
#define M88X_PHY_CNTL 0x00 |
||||
#define M88X_PHY_STAT 0x00 |
||||
#define M88X_PHY_ID0 0x02 |
||||
#define M88X_PHY_ID1 0x03 |
||||
#define M88X_PHY_ANEG_ADV 0x04 |
||||
#define M88X_PHY_LPA 0x05 |
||||
#define M88X_PHY_ANEG_EXP 0x06 |
||||
#define M88X_PHY_NPT 0x07 |
||||
#define M88X_PHY_LPNP 0x08 |
||||
|
||||
/* port register offsets */ |
||||
#define M88X_PRT_STAT 0x00 |
||||
#define M88X_PRT_ID 0x03 |
||||
#define M88X_PRT_CNTL 0x04 |
||||
#define M88X_PRT_VLAN 0x06 |
||||
#define M88X_PRT_PAV 0x0b |
||||
#define M88X_PRT_RX 0x10 |
||||
#define M88X_PRT_TX 0x11 |
||||
|
||||
/* global/atu register offsets */ |
||||
#define M88X_GLB_STAT 0x00 |
||||
#define M88X_GLB_MAC01 0x01 |
||||
#define M88X_GLB_MAC23 0x02 |
||||
#define M88X_GLB_MAC45 0x03 |
||||
#define M88X_GLB_CNTL 0x04 |
||||
#define M88X_ATU_CNTL 0x0a |
||||
#define M88X_ATU_OP 0x0b |
||||
|
||||
/* id0 register - 0x02 */ |
||||
#define M88X_PHY_ID0_VALUE 0x0141 |
||||
|
||||
/* id1 register - 0x03 */ |
||||
#define M88X_PHY_ID1_VALUE 0x0c80 /* without revision ! */ |
||||
|
||||
|
||||
/* misc */ |
||||
#define M88E6060_ID ((M88X_PHY_ID0_VALUE<<16) | M88X_PHY_ID1_VALUE) |
||||
|
||||
|
||||
|
||||
/* ************************************************************************** */ |
||||
/* *** TYPEDEFS ************************************************************* */ |
||||
|
||||
typedef struct { |
||||
int reg; |
||||
unsigned short msk; |
||||
unsigned short val; |
||||
} m88x_regCfg_t; |
||||
|
||||
|
||||
|
||||
/* ************************************************************************** */ |
||||
/* *** PROTOTYPES *********************************************************** */ |
||||
|
||||
extern int m88e6060_initialize( int ); |
||||
|
||||
|
||||
|
||||
#endif /* _INC_m88e6060_h_ */ |
@ -0,0 +1,122 @@ |
||||
/* |
||||
* (C) Copyright 2001-2003 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* Modified by Yuli Barcohen <yuli@arabellasw.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
SECTIONS |
||||
{ |
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
cpu/mpc8260/start.o (.text) |
||||
*(.text) |
||||
*(.fixup) |
||||
*(.got1) |
||||
. = ALIGN(16); |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
*(.rodata.str1.4) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x0FFF) & 0xFFFFF000; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_) >> 2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
|
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(4096); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(4096); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
} |
||||
_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
||||
ENTRY(_start) |
@ -0,0 +1,375 @@ |
||||
/*
|
||||
* (C) Copyright 2004 |
||||
* Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de) |
||||
* |
||||
* Support for the Elmeg VoVPN Gateway Module |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <ioports.h> |
||||
#include <mpc8260.h> |
||||
#include <asm/m8260_pci.h> |
||||
#include <miiphy.h> |
||||
|
||||
#include "m88e6060.h" |
||||
|
||||
/*
|
||||
* I/O Port configuration table |
||||
* |
||||
* if conf is 1, then that port pin will be configured at boot time |
||||
* according to the five values podr/pdir/ppar/psor/pdat for that entry |
||||
*/ |
||||
|
||||
const iop_conf_t iop_conf_tab[4][32] = { |
||||
/* Port A configuration */ |
||||
{ /* conf ppar psor pdir podr pdat */ |
||||
/* PA31 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1252 */ |
||||
/* PA30 */ { 1, 0, 0, 0, 0, 0 }, /* GPI BP_RES */ |
||||
/* PA29 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1253 */ |
||||
/* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 RMII TX_EN */ |
||||
/* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RMII CRS_DV */ |
||||
/* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RMII RX_ERR */ |
||||
/* PA25 */ { 1, 0, 0, 0, 0, 0 }, /* GPI HWID */ |
||||
/* PA24 */ { 1, 0, 0, 0, 0, 0 }, /* GPI HWID */ |
||||
/* PA23 */ { 1, 0, 0, 0, 0, 0 }, /* GPI HWID */ |
||||
/* PA22 */ { 1, 0, 0, 0, 0, 0 }, /* GPI HWID */ |
||||
/* PA21 */ { 1, 0, 0, 0, 0, 0 }, /* GPI HWID */ |
||||
/* PA20 */ { 1, 0, 0, 1, 0, 1 }, /* GPO LED STATUS */ |
||||
/* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 RMII TxD[1] */ |
||||
/* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 RMII TxD[0] */ |
||||
/* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RMII RxD[0] */ |
||||
/* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RMII RxD[1] */ |
||||
/* PA15 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1255 */ |
||||
/* PA14 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP???? */ |
||||
/* PA13 */ { 1, 0, 0, 1, 0, 1 }, /* GPO EN_BCTL1 XXX jse */ |
||||
/* PA12 */ { 1, 0, 0, 1, 0, 0 }, /* GPO SWITCH RESET */ |
||||
/* PA11 */ { 1, 0, 0, 1, 0, 0 }, /* GPO DSP SL1 RESET */ |
||||
/* PA10 */ { 1, 0, 0, 1, 0, 0 }, /* GPO DSP SL2 RESET */ |
||||
/* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */ |
||||
/* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */ |
||||
/* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */ |
||||
/* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */ |
||||
/* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */ |
||||
/* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */ |
||||
/* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */ |
||||
/* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */ |
||||
/* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */ |
||||
/* PA0 */ { 0, 0, 0, 0, 0, 0 } /* pin does not exit */ |
||||
}, |
||||
|
||||
/* Port B configuration */ |
||||
{ /* conf ppar psor pdir podr pdat */ |
||||
/* PB31 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1257 */ |
||||
/* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RMII CRS_DV */ |
||||
/* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 RMII TX_EN */ |
||||
/* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RMII RX_ERR */ |
||||
/* PB27 */ { 1, 1, 1, 0, 1, 0 }, /* TDM_B2 L1TXD XXX val=0 */ |
||||
/* PB26 */ { 1, 1, 1, 0, 1, 0 }, /* TDM_B2 L1RXD XXX val,dr */ |
||||
/* PB25 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1259 */ |
||||
/* PB24 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_B2 L1RSYNC */ |
||||
/* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 RMII TxD[1] */ |
||||
/* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 RMII TxD[0] */ |
||||
/* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RMII RxD[0] */ |
||||
/* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RMII RxD[1] */ |
||||
/* PB19 */ { 1, 0, 0, 1, 0, 1 }, /* GPO PHY MDC */ |
||||
/* PB18 */ { 1, 0, 0, 0, 0, 0 }, /* GPIO PHY MDIO */ |
||||
/* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ |
||||
/* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ |
||||
/* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ |
||||
/* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ |
||||
/* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ |
||||
/* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ |
||||
/* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ |
||||
/* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ |
||||
/* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ |
||||
/* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ |
||||
/* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ |
||||
/* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ |
||||
/* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ |
||||
/* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ |
||||
/* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ |
||||
/* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ |
||||
/* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ |
||||
/* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin does not exist */ |
||||
}, |
||||
|
||||
/* Port C */ |
||||
{ /* conf ppar psor pdir podr pdat */ |
||||
/* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ |
||||
/* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ |
||||
/* PC29 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1183 */ |
||||
/* PC28 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1184 */ |
||||
/* PC27 */ { 1, 1, 0, 0, 0, 0 }, /* CLK5 TDM_A1 RX */ |
||||
/* PC26 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1185 */ |
||||
/* PC25 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1178 */ |
||||
/* PC24 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1186 */ |
||||
/* PC23 */ { 1, 1, 0, 0, 0, 0 }, /* CLK9 TDM_B2 RX */ |
||||
/* PC22 */ { 1, 1, 0, 0, 0, 0 }, /* CLK10 FCC1 RMII REFCLK */ |
||||
/* PC21 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1187 */ |
||||
/* PC20 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1182 */ |
||||
/* PC19 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1188 */ |
||||
/* PC18 */ { 1, 0, 0, 1, 0, 0 }, /* GPO HW RESET */ |
||||
/* PC17 */ { 1, 1, 0, 1, 0, 0 }, /* BRG8 SWITCH CLKIN */ |
||||
/* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* CLK16 FCC2 RMII REFCLK */ |
||||
/* PC15 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL1_MTYPE_3 */ |
||||
/* PC14 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL1_MTYPE_2 */ |
||||
/* PC13 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL1_MTYPE_1 */ |
||||
/* PC12 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL1_MTYPE_0 */ |
||||
/* PC11 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1176 */ |
||||
/* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1177 */ |
||||
/* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL2_MTYPE_3 */ |
||||
/* PC8 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL2_MTYPE_2 */ |
||||
/* PC7 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL2_MTYPE_1 */ |
||||
/* PC6 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL2_MTYPE_0 */ |
||||
/* PC5 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ |
||||
/* PC4 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ |
||||
/* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ |
||||
/* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ |
||||
/* PC1 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1192 */ |
||||
/* PC0 */ { 1, 0, 0, 0, 0, 0 }, /* GPI RACK */ |
||||
}, |
||||
|
||||
/* Port D */ |
||||
{ /* conf ppar psor pdir podr pdat */ |
||||
/* PD31 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1193 */ |
||||
/* PD30 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1194 */ |
||||
/* PD29 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1195 */ |
||||
/* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ |
||||
/* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ |
||||
/* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ |
||||
/* PD25 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1179 */ |
||||
/* PD24 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1180 */ |
||||
/* PD23 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1181 */ |
||||
/* PD22 */ { 1, 1, 1, 0, 1, 0 }, /* TDM_A2 L1TXD */ |
||||
/* PD21 */ { 1, 1, 1, 0, 1, 0 }, /* TDM_A2 L1RXD */ |
||||
/* PD20 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A2 L1RSYNC */ |
||||
/* PD19 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1196 */ |
||||
/* PD18 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1197 */ |
||||
/* PD17 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1198 */ |
||||
/* PD16 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1199 */ |
||||
/* PD15 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1250 */ |
||||
/* PD14 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1251 */ |
||||
/* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ |
||||
/* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ |
||||
/* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ |
||||
/* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ |
||||
/* PD9 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ |
||||
/* PD8 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ |
||||
/* PD7 */ { 0, 0, 0, 1, 0, 0 }, /* GPO FL_BYTE */ |
||||
/* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ |
||||
/* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ |
||||
/* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ |
||||
/* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ |
||||
/* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ |
||||
/* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ |
||||
/* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin does not exist */ |
||||
} |
||||
}; |
||||
|
||||
void reset_phy (void) |
||||
{ |
||||
volatile ioport_t *iop; |
||||
#if (CONFIG_COMMANDS & CFG_CMD_NET) |
||||
int i; |
||||
unsigned short val; |
||||
#endif |
||||
|
||||
iop = ioport_addr((immap_t *)CFG_IMMR, 0); |
||||
|
||||
/* Reset the PHY */ |
||||
iop->pdat &= 0xfff7ffff; /* PA12 = |SWITCH_RESET */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_NET) |
||||
udelay(20000); |
||||
iop->pdat |= 0x00080000; |
||||
for (i=0; i<100; i++) { |
||||
udelay(20000); |
||||
if (miiphy_read( CFG_PHY_ADDR,2,&val ) == 0) { |
||||
break; |
||||
} |
||||
} |
||||
/* initialize switch */ |
||||
m88e6060_initialize( CFG_PHY_ADDR ); |
||||
#endif |
||||
} |
||||
|
||||
static unsigned long UPMATable[] = { |
||||
0x8fffec00, 0x0ffcfc00, 0x0ffcfc00, 0x0ffcfc00, //Words 0 to 3
|
||||
0x0ffcfc04, 0x3ffdfc00, 0xfffffc01, 0xfffffc01, //Words 4 to 7
|
||||
0xfffffc00, 0xfffffc04, 0xfffffc01, 0xfffffc00, //Words 8 to 11
|
||||
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, //Words 12 to 15
|
||||
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, //Words 16 to 19
|
||||
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, //Words 20 to 23
|
||||
0x8fffec00, 0x00fffc00, 0x00fffc00, 0x00fffc00, //Words 24 to 27
|
||||
0x0ffffc04, 0xfffffc01, 0xfffffc01, 0xfffffc01, //Words 28 to 31
|
||||
0xfffffc00, 0xfffffc01, 0xfffffc01, 0xfffffc00, //Words 32 to 35
|
||||
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, //Words 36 to 39
|
||||
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, //Words 40 to 43
|
||||
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, //Words 44 to 47
|
||||
0xfffffc00, 0xfffffc04, 0xfffffc01, 0xfffffc00, //Words 48 to 51
|
||||
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, //Words 52 to 55
|
||||
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, //Words 56 to 59
|
||||
0xffffec00, 0xffffec04, 0xffffec00, 0xfffffc01 //Words 60 to 63
|
||||
}; |
||||
|
||||
int board_early_init_f (void) |
||||
{ |
||||
volatile immap_t *immap; |
||||
volatile memctl8260_t *memctl; |
||||
volatile unsigned char *dummy; |
||||
int i; |
||||
|
||||
immap = (immap_t *) CFG_IMMR; |
||||
memctl = &immap->im_memctl; |
||||
|
||||
#if 0 |
||||
/* CS2-5 - DSP via UPMA */ |
||||
dummy = (volatile unsigned char *) (memctl->memc_br2 & BRx_BA_MSK); |
||||
memctl->memc_mar = 0; |
||||
memctl->memc_mamr = MxMR_OP_WARR; |
||||
for (i = 0; i < 64; i++) { |
||||
memctl->memc_mdr = UPMATable[i]; |
||||
*dummy = 0; |
||||
} |
||||
memctl->memc_mamr = 0x00044440; |
||||
#else |
||||
/* CS7 - DPRAM via UPMA */ |
||||
dummy = (volatile unsigned char *) (memctl->memc_br7 & BRx_BA_MSK); |
||||
memctl->memc_mar = 0; |
||||
memctl->memc_mamr = MxMR_OP_WARR; |
||||
for (i = 0; i < 64; i++) { |
||||
memctl->memc_mdr = UPMATable[i]; |
||||
*dummy = 0; |
||||
} |
||||
memctl->memc_mamr = 0x00044440; |
||||
#endif |
||||
return 0; |
||||
} |
||||
|
||||
int misc_init_r (void) |
||||
{ |
||||
volatile ioport_t *iop; |
||||
unsigned char temp; |
||||
#if 0 |
||||
/* DUMP UPMA RAM */ |
||||
volatile immap_t *immap; |
||||
volatile memctl8260_t *memctl; |
||||
volatile unsigned char *dummy; |
||||
unsigned char c; |
||||
int i; |
||||
|
||||
immap = (immap_t *) CFG_IMMR; |
||||
memctl = &immap->im_memctl; |
||||
|
||||
|
||||
dummy = (volatile unsigned char *) (memctl->memc_br7 & BRx_BA_MSK); |
||||
memctl->memc_mar = 0; |
||||
memctl->memc_mamr = MxMR_OP_RARR; |
||||
for (i = 0; i < 64; i++) { |
||||
c = *dummy; |
||||
printf( "UPMA[%02d]: 0x%08lx,0x%08lx: 0x%08lx\n",i, |
||||
memctl->memc_mamr, |
||||
memctl->memc_mar, |
||||
memctl->memc_mdr ); |
||||
} |
||||
memctl->memc_mamr = 0x00044440; |
||||
#endif |
||||
/* enable buffers (DSP, DPRAM) */ |
||||
iop = ioport_addr((immap_t *)CFG_IMMR, 0); |
||||
iop->pdat &= 0xfffbffff; /* PA13 = |EN_M_BCTL1 */ |
||||
|
||||
/* destroy DPRAM magic */ |
||||
*(volatile unsigned char *)0xf0500000 = 0x00; |
||||
|
||||
/* clear any pending DPRAM irq */ |
||||
temp = *(volatile unsigned char *)0xf05003ff; |
||||
|
||||
/* write module-id into DPRAM */ |
||||
*(volatile unsigned char *)0xf0500201 = 0x50; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
#if defined(CONFIG_HAVE_OWN_RESET) |
||||
int |
||||
do_reset (void *cmdtp, int flag, int argc, char *argv[]) |
||||
{ |
||||
volatile ioport_t *iop; |
||||
|
||||
iop = ioport_addr((immap_t *)CFG_IMMR, 2); |
||||
iop->pdat |= 0x00002000; /* PC18 = HW_RESET */ |
||||
return 1; |
||||
} |
||||
#endif /* CONFIG_HAVE_OWN_RESET */ |
||||
|
||||
#define ns2clk(ns) (ns / (1000000000 / CONFIG_8260_CLKIN) + 1) |
||||
|
||||
long int initdram (int board_type) |
||||
{ |
||||
#ifndef CFG_RAMBOOT |
||||
volatile immap_t *immap; |
||||
volatile memctl8260_t *memctl; |
||||
volatile uchar *ramaddr; |
||||
int i; |
||||
uchar c; |
||||
|
||||
immap = (immap_t *) CFG_IMMR; |
||||
memctl = &immap->im_memctl; |
||||
ramaddr = (uchar *) CFG_SDRAM_BASE; |
||||
c = 0xff; |
||||
|
||||
immap->im_siu_conf.sc_ppc_acr = 0x02; |
||||
immap->im_siu_conf.sc_ppc_alrh = 0x01267893; |
||||
immap->im_siu_conf.sc_ppc_alrl = 0x89abcdef; |
||||
immap->im_siu_conf.sc_tescr1 = 0x00000000; |
||||
immap->im_siu_conf.sc_tescr2 = 0x00000000; |
||||
|
||||
memctl->memc_mptpr = CFG_MPTPR; |
||||
memctl->memc_psrt = CFG_PSRT; |
||||
memctl->memc_or1 = CFG_OR1_PRELIM; |
||||
memctl->memc_br1 = CFG_SDRAM_BASE | CFG_BR1_PRELIM; |
||||
|
||||
/* Precharge all banks */ |
||||
memctl->memc_psdmr = CFG_PSDMR | 0x28000000; |
||||
*ramaddr = c; |
||||
|
||||
/* CBR refresh */ |
||||
memctl->memc_psdmr = CFG_PSDMR | 0x08000000; |
||||
for (i = 0; i < 8; i++) |
||||
*ramaddr = c; |
||||
|
||||
/* Mode Register write */ |
||||
memctl->memc_psdmr = CFG_PSDMR | 0x18000000; |
||||
*ramaddr = c; |
||||
|
||||
/* Refresh enable */ |
||||
memctl->memc_psdmr = CFG_PSDMR | 0x40000000; |
||||
*ramaddr = c; |
||||
#endif /* CFG_RAMBOOT */ |
||||
|
||||
return (CFG_SDRAM_SIZE); |
||||
} |
||||
|
||||
int checkboard (void) |
||||
{ |
||||
#ifdef CONFIG_CLKIN_66MHz |
||||
puts ("Board: Elmeg VoVPN Gateway Module (66MHz)\n"); |
||||
#else |
||||
puts ("Board: Elmeg VoVPN Gateway Module (100MHz)\n"); |
||||
#endif |
||||
return 0; |
||||
} |
@ -0,0 +1,406 @@ |
||||
/*
|
||||
* (C) Copyright 2004 |
||||
* Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de) |
||||
* |
||||
* Support for the Elmeg VoVPN Gateway Module |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/* define cpu used */ |
||||
#define CONFIG_MPC8272 1 |
||||
|
||||
/* define busmode: 8260 */ |
||||
#undef CONFIG_BUSMODE_60x |
||||
|
||||
/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ |
||||
#ifdef CONFIG_CLKIN_66MHz |
||||
#define CONFIG_8260_CLKIN 66666666 /* in Hz */ |
||||
#else |
||||
#define CONFIG_8260_CLKIN 100000000 /* in Hz */ |
||||
#endif |
||||
|
||||
/* call board_early_init_f */ |
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 |
||||
|
||||
/* have misc_init_r() function */ |
||||
#define CONFIG_MISC_INIT_R 1 |
||||
|
||||
/* have reset_phy_r() function */ |
||||
#define CONFIG_RESET_PHY_R 1 |
||||
|
||||
/* have special reset function */ |
||||
#define CONFIG_HAVE_OWN_RESET 1 |
||||
|
||||
/* allow serial and ethaddr to be overwritten */ |
||||
#define CONFIG_ENV_OVERWRITE |
||||
|
||||
/* watchdog disabled */ |
||||
#undef CONFIG_WATCHDOG |
||||
|
||||
/* include support for bzip2 compressed images */ |
||||
#undef CONFIG_BZIP2 |
||||
|
||||
/* status led */ |
||||
#undef CONFIG_STATUS_LED /* XXX jse */ |
||||
|
||||
/* vendor parameter protection */ |
||||
#define CONFIG_ENV_OVERWRITE |
||||
|
||||
/*
|
||||
* select serial console configuration |
||||
* |
||||
* if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then |
||||
* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 |
||||
* for SCC). |
||||
*/ |
||||
#define CONFIG_CONS_ON_SMC |
||||
#undef CONFIG_CONS_ON_SCC |
||||
#undef CONFIG_CONS_NONE |
||||
#define CONFIG_CONS_INDEX 1 |
||||
|
||||
/* serial port default baudrate */ |
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
/* echo on for serial download */ |
||||
#define CONFIG_LOADS_ECHO 1 |
||||
|
||||
/* don't allow baudrate change */ |
||||
#undef CFG_LOADS_BAUD_CHANGE |
||||
|
||||
/* supported baudrates */ |
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
||||
|
||||
/*
|
||||
* select ethernet configuration |
||||
* |
||||
* if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then |
||||
* CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 |
||||
* for FCC) |
||||
* |
||||
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be |
||||
* defined elsewhere (as for the console), or CFG_CMD_NET must be removed |
||||
* from CONFIG_COMMANDS to remove support for networking. |
||||
*/ |
||||
#undef CONFIG_ETHER_ON_SCC |
||||
#define CONFIG_ETHER_ON_FCC |
||||
#undef CONFIG_ETHER_NONE |
||||
|
||||
#ifdef CONFIG_ETHER_ON_FCC |
||||
|
||||
/* which SCC/FCC channel for ethernet */ |
||||
#define CONFIG_ETHER_INDEX 1 |
||||
|
||||
/* Marvell Switch SMI base addr */ |
||||
#define CFG_PHY_ADDR 0x10 |
||||
|
||||
/* FCC1 RMII REFCLK is CLK10 */ |
||||
#define CFG_CMXFCR_VALUE CMXFCR_TF1CS_CLK10 |
||||
#define CFG_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_TF1CS_MSK) |
||||
|
||||
/* BDs and buffers on 60x bus */ |
||||
#define CFG_CPMFCR_RAMTYPE 0 |
||||
|
||||
/* Local Protect, Full duplex, Flowcontrol, RMII */ |
||||
#define CFG_FCC_PSMR (FCC_PSMR_LPB|FCC_PSMR_FDE|\ |
||||
FCC_PSMR_FCE|FCC_PSMR_RMII) |
||||
|
||||
/* bit-bang MII PHY management */ |
||||
#define CONFIG_BITBANGMII |
||||
|
||||
#define MDIO_PORT 1 /* Port B */ |
||||
#define CFG_MDIO_PIN 0x00002000 /* PB18 */ |
||||
#define CFG_MDC_PIN 0x00001000 /* PB19 */ |
||||
#define MDIO_ACTIVE (iop->pdir |= CFG_MDIO_PIN) |
||||
#define MDIO_TRISTATE (iop->pdir &= ~CFG_MDIO_PIN) |
||||
#define MDIO_READ ((iop->pdat & CFG_MDIO_PIN) != 0) |
||||
#define MDIO(bit) if(bit) iop->pdat |= CFG_MDIO_PIN; \ |
||||
else iop->pdat &= ~CFG_MDIO_PIN |
||||
#define MDC(bit) if(bit) iop->pdat |= CFG_MDC_PIN; \ |
||||
else iop->pdat &= ~CFG_MDC_PIN |
||||
#define MIIDELAY udelay(1) |
||||
|
||||
#endif |
||||
|
||||
/* configure commands */ |
||||
#define CONFIG_COMMANDS ( CFG_CMD_AUTOSCRIPT | \ |
||||
CFG_CMD_BDI | \
|
||||
CFG_CMD_CONSOLE | \
|
||||
CFG_CMD_ECHO | \
|
||||
CFG_CMD_ENV | \
|
||||
CFG_CMD_FLASH | \
|
||||
CFG_CMD_IMI | \
|
||||
CFG_CMD_IMLS | \
|
||||
CFG_CMD_LOADB | \
|
||||
CFG_CMD_MEMORY | \
|
||||
CFG_CMD_MISC | \
|
||||
CFG_CMD_NET | \
|
||||
CFG_CMD_PING | \
|
||||
CFG_CMD_RUN ) |
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
/*
|
||||
* boot options & environment |
||||
*/ |
||||
#define CONFIG_BOOTDELAY 3 |
||||
#define CONFIG_BOOTCOMMAND "run flash_self" |
||||
#undef CONFIG_BOOTARGS |
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"clean_nv=erase fff20000 ffffffff\0" \
|
||||
"update_boss=tftp 100000 PPC/logic157.bin; protect off fff00000 ffffffff; erase fff00000 ffffffff; cp.b 100000 fff00000 $(filesize); tftp 100000 PPC/bootmon157.bin; cp.b 100000 fff20000 $(filesize)\0" \
|
||||
"update_lx=tftp 100000 $(kernel); erase $(kernel_addr) ffefffff; cp.b 100000 $(kernel_addr) $(filesize)\0" \
|
||||
"update_fs=tftp 100000 $(fs).$(fstype); erase ff840000 ffdfffff; cp.b 100000 ff840000 $(filesize)\0" \
|
||||
"update_ub=tftp 100000 $(uboot); protect off fff00000 fff1ffff; erase fff00000 fff1ffff; cp.b 100000 fff00000 $(filesize); protect off ff820000 ff83ffff; erase ff820000 ff83ffff\0" \
|
||||
"flashargs=setenv bootargs root=$(rootdev) rw rootfstype=$(fstype)\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath)\0" \
|
||||
"addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname):$(netdev):off\0" \
|
||||
"addmisc=setenv bootargs $(bootargs) console=$(console),$(baudrate) ethaddr=$(ethaddr) panic=1\0" \
|
||||
"net_nfs=tftpboot 400000 $(kernel); run nfsargs addip addmisc; bootm\0" \
|
||||
"net_self=tftpboot 400000 $(kernel); run flashargs addmisc; bootm\0" \
|
||||
"flash_self=run flashargs addmisc; bootm $(kernel_addr)\0" \
|
||||
"flash_nfs=run nfsargs addip addmisc; bootm $(kernel_addr)\0" \
|
||||
"fstype=cramfs\0" \
|
||||
"rootpath=/root_fs\0" \
|
||||
"uboot=PPC/u-boot.bin\0" \
|
||||
"kernel=PPC/uImage\0" \
|
||||
"kernel_addr=ffe00000\0" \
|
||||
"fs=PPC/root_fs\0" \
|
||||
"console=ttyS0\0" \
|
||||
"netdev=eth0\0" \
|
||||
"rootdev=31:3\0" \
|
||||
"ethaddr=00:09:4f:01:02:03\0" \
|
||||
"ipaddr=10.0.0.201\0" \
|
||||
"netmask=255.255.255.0\0" \
|
||||
"serverip=10.0.0.136\0" \
|
||||
"gatewayip=10.0.0.10\0" \
|
||||
"hostname=bastard\0" \
|
||||
"" |
||||
|
||||
|
||||
/*
|
||||
* miscellaneous configurable options |
||||
*/ |
||||
|
||||
/* undef to save memory */ |
||||
#define CFG_LONGHELP |
||||
|
||||
/* monitor command prompt */ |
||||
#define CFG_PROMPT "=> " |
||||
|
||||
/* console i/o buffer size */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 |
||||
#else |
||||
#define CFG_CBSIZE 256 |
||||
#endif |
||||
|
||||
/* print buffer size */ |
||||
#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) |
||||
|
||||
/* max number of command args */ |
||||
#define CFG_MAXARGS 16 |
||||
|
||||
/* boot argument buffer size */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE |
||||
|
||||
/* memtest works on */ |
||||
#define CFG_MEMTEST_START 0x00100000 |
||||
/* 1 ... 15 MB in DRAM */ |
||||
#define CFG_MEMTEST_END 0x00f00000 |
||||
/* full featured memtest */ |
||||
#define CFG_ALT_MEMTEST |
||||
|
||||
/* default load address */ |
||||
#define CFG_LOAD_ADDR 0x00100000 |
||||
|
||||
/* decrementer freq: 1 ms ticks */ |
||||
#define CFG_HZ 1000 |
||||
|
||||
/* configure flash */ |
||||
#define CFG_FLASH_BASE 0xff800000 |
||||
#define CFG_MAX_FLASH_BANKS 1 |
||||
#define CFG_MAX_FLASH_SECT 64 |
||||
#define CFG_FLASH_SIZE 8 |
||||
#undef CFG_FLASH_16BIT |
||||
#define CFG_FLASH_ERASE_TOUT 240000 |
||||
#define CFG_FLASH_WRITE_TOUT 500 |
||||
#define CFG_FLASH_LOCK_TOUT 500 |
||||
#define CFG_FLASH_UNLOCK_TOUT 10000 |
||||
#define CFG_FLASH_PROTECTION |
||||
|
||||
/* monitor in flash */ |
||||
#define CFG_MONITOR_OFFSET 0x00700000 |
||||
|
||||
/* environment in flash */ |
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00020000) |
||||
#define CFG_ENV_SIZE 0x00020000 |
||||
#define CFG_ENV_SECT_SIZE 0x00020000 |
||||
|
||||
/*
|
||||
* Initial memory map for linux |
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) |
||||
|
||||
/* hard reset configuration words */ |
||||
#ifdef CONFIG_CLKIN_66MHz |
||||
#define CFG_HRCW_MASTER 0x04643050 |
||||
#else |
||||
#error NO HRCW FOR 100MHZ SPECIFIED !!! |
||||
#endif |
||||
#define CFG_HRCW_SLAVE1 0x00000000 |
||||
#define CFG_HRCW_SLAVE2 0x00000000 |
||||
#define CFG_HRCW_SLAVE3 0x00000000 |
||||
#define CFG_HRCW_SLAVE4 0x00000000 |
||||
#define CFG_HRCW_SLAVE5 0x00000000 |
||||
#define CFG_HRCW_SLAVE6 0x00000000 |
||||
#define CFG_HRCW_SLAVE7 0x00000000 |
||||
|
||||
/* internal memory mapped register */ |
||||
#define CFG_IMMR 0xF0000000 |
||||
|
||||
/* definitions for initial stack pointer and data area (in DPRAM) */ |
||||
#define CFG_INIT_RAM_ADDR CFG_IMMR |
||||
#define CFG_INIT_RAM_END 0x2000 |
||||
#define CFG_GBL_DATA_SIZE 128 |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
/*
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0 |
||||
*/ |
||||
#define CFG_SDRAM_BASE 0x00000000 |
||||
#define CFG_SDRAM_SIZE (32*1024*1024) |
||||
#define CFG_MONITOR_BASE TEXT_BASE |
||||
#define CFG_MONITOR_FLASH (CFG_FLASH_BASE + CFG_MONITOR_OFFSET) |
||||
#define CFG_MONITOR_LEN 0x00020000 |
||||
#define CFG_MALLOC_LEN 0x00020000 |
||||
|
||||
/* boot flags */ |
||||
#define BOOTFLAG_COLD 0x01 /* normal power-on */ |
||||
#define BOOTFLAG_WARM 0x02 /* software reboot */ |
||||
|
||||
/* cache configuration */ |
||||
#define CFG_CACHELINE_SIZE 32 /* for MPC8260 */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of above */ |
||||
#endif |
||||
|
||||
/*
|
||||
* HIDx - Hardware Implementation-dependent Registers |
||||
*----------------------------------------------------------------------- |
||||
* HID0 also contains cache control - initially enable both caches and |
||||
* invalidate contents, then the final state leaves only the instruction |
||||
* cache enabled. Note that Power-On and Hard reset invalidate the caches, |
||||
* but Soft reset does not. |
||||
* |
||||
* HID1 has only read-only information - nothing to set. |
||||
*/ |
||||
#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|\ |
||||
HID0_ICFI|HID0_DCI|HID0_IFEM|HID0_ABE) |
||||
#define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE) |
||||
#define CFG_HID2 0 |
||||
|
||||
/* RMR - reset mode register - turn on checkstop reset enable */ |
||||
#define CFG_RMR RMR_CSRE |
||||
|
||||
/* BCR - bus configuration */ |
||||
#define CFG_BCR 0x00000000 |
||||
|
||||
/* SIUMCR - siu module configuration */ |
||||
#define CFG_SIUMCR 0x4905c000 |
||||
|
||||
/* SYPCR - system protection control */ |
||||
#if defined(CONFIG_WATCHDOG) |
||||
#define CFG_SYPCR 0xffffff87 |
||||
#else |
||||
#define CFG_SYPCR 0xffffff83 |
||||
#endif |
||||
|
||||
/* TMCNTSC - time counter status and control */ |
||||
/* clear interrupts XXX jse */ |
||||
//#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR)
|
||||
#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|\ |
||||
TMCNTSC_TCF|TMCNTSC_TCE) |
||||
|
||||
/* PISCR - periodic interrupt status and control */ |
||||
/* clear interrupts XXX jse */ |
||||
//#define CFG_PISCR (PISCR_PS)
|
||||
#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) |
||||
|
||||
/* SCCR - system clock control */ |
||||
#define CFG_SCCR 0x000001a9 |
||||
|
||||
/* RCCR - risc controller configuration */ |
||||
#define CFG_RCCR 0 |
||||
|
||||
/*
|
||||
* MEMORY MAP |
||||
* ---------- |
||||
* CS0 - FLASH 8MB/8Bit base=0xff800000 (boot: 0xfe000000, 8x mirrored) |
||||
* CS1 - SDRAM 32MB/64Bit base=0x00000000 |
||||
* CS2 - DSP/SL1 1MB/16Bit base=0xf0100000 |
||||
* CS3 - DSP/SL2 1MB/16Bit base=0xf0200000 |
||||
* CS4 - DSP/SL3 1MB/16Bit base=0xf0300000 |
||||
* CS5 - DSP/SL4 1MB/16Bit base=0xf0400000 |
||||
* CS7 - DPRAM 1KB/8Bit base=0xf0500000, size=32KB (32x mirrored) |
||||
* x - IMMR 384KB base=0xf0000000 |
||||
*/ |
||||
/* XXX jse 100MHz TODO */ |
||||
#define CFG_BR0_PRELIM 0xff800801 |
||||
#define CFG_OR0_PRELIM 0xff801e44 |
||||
#define CFG_BR1_PRELIM 0x00000041 |
||||
#define CFG_OR1_PRELIM 0xfe002ec0 |
||||
#if 1 |
||||
#define CFG_BR2_PRELIM 0xf0101001 |
||||
#define CFG_OR2_PRELIM 0xfff00ef4 |
||||
#define CFG_BR3_PRELIM 0xf0201001 |
||||
#define CFG_OR3_PRELIM 0xfff00ef4 |
||||
#define CFG_BR4_PRELIM 0xf0301001 |
||||
#define CFG_OR4_PRELIM 0xfff00ef4 |
||||
#define CFG_BR5_PRELIM 0xf0401001 |
||||
#define CFG_OR5_PRELIM 0xfff00ef4 |
||||
#else |
||||
#define CFG_BR2_PRELIM 0xf0101081 |
||||
#define CFG_OR2_PRELIM 0xfff00104 |
||||
#define CFG_BR3_PRELIM 0xf0201081 |
||||
#define CFG_OR3_PRELIM 0xfff00104 |
||||
#define CFG_BR4_PRELIM 0xf0301081 |
||||
#define CFG_OR4_PRELIM 0xfff00104 |
||||
#define CFG_BR5_PRELIM 0xf0401081 |
||||
#define CFG_OR5_PRELIM 0xfff00104 |
||||
#endif |
||||
#define CFG_BR7_PRELIM 0xf0500881 |
||||
#define CFG_OR7_PRELIM 0xffff8104 |
||||
#define CFG_MPTPR 0x2700 |
||||
#define CFG_PSDMR 0x822a2452 /* optimal */ |
||||
//#define CFG_PSDMR 0x822a48a3 /* relaxed */
|
||||
#define CFG_PSRT 0x1a |
||||
|
||||
/* "bad" address */ |
||||
#define CFG_RESET_ADDRESS 0x40000000 |
||||
|
||||
#endif /* __CONFIG_H */ |
Loading…
Reference in new issue